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Watchdog Timer Operation

12-5

Watchdog Timer, Watchdog Timer+

Note:

Modifying the Watchdog Timer

The WDT interval should be changed together with WDTCNTCL = 1 in a
single instruction to avoid an unexpected immediate PUC or interrupt.

The WDT should be halted before changing the clock source to avoid a
possible incorrect interval.

12.2.4 Watchdog Timer Interrupts

The WDT uses two bits in the SFRs for interrupt control.

-

The WDT interrupt flag, WDTIFG, located in IFG1.0

-

The WDT interrupt enable, WDTIE, located in IE1.0

When using the WDT in the watchdog mode, the WDTIFG flag sources a reset
vector interrupt. The WDTIFG can be used by the reset interrupt service
routine to determine if the watchdog caused the device to reset. If the flag is
set, then the watchdog timer initiated the reset condition either by timing out
or by a security key violation. If WDTIFG is cleared, the reset was caused by
a different source.

When using the WDT in interval timer mode, the WDTIFG flag is set after the
selected time interval and requests a WDT interval timer interrupt if the WDTIE
and the GIE bits are set. The interval timer interrupt vector is different from the
reset vector used in watchdog mode. In interval timer mode, the WDTIFG flag
is reset automatically when the interrupt is serviced, or can be reset with
software.

12.2.5 WDT+ Enhancements

The WDT+ module provides enhanced functionality over the WDT. The WDT+
provides a fail-safe clocking feature assuring the clock to the WDT+ cannot be
disabled while in watchdog mode. This means the low-power modes may be
affected by the choice for the WDT+ clock. For example, if ACLK is the WDT+
clock source, LPM4 will not be available, because the WDT+ will prevent
ACLK from being disabled. Also, if ACLK or SMCLK fail while sourcing the
WDT+, the WDT+ clock source is automatically switched to MCLK. In this
case, if MCLK is sourced from a crystal, and the crystal has failed, the FLL+
fail-safe feature will activate the DCO and use it as the source for MCLK.

When the WDT+ module is used in interval timer mode, there is no fail-safe
feature for the clock source.

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Summary of Contents for MSP430x4xx Family

Page 1: ...MSP430x4xx Family 2007 Mixed Signal Products User s Guide SLAU056G ...

Page 2: ......

Page 3: ...onsult the device specific data sheet for these details Related Documentation From Texas Instruments For related documentation see the web site http www ti com msp430 FCC Warning This equipment is intended for use in a laboratory test environment only It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to sub...

Page 4: ...Bit LSD Least Significant Digit LPM Low Power Mode See System Resets Interrupts and Operating Modes MAB Memory Address Bus MCLK Master Clock See FLL Module MDB Memory Data Bus MSB Most Significant Bit MSD Most Significant Digit NMI Non Maskable Interrupt See System Resets Interrupts and Operating Modes PC Program Counter See RISC 16 Bit CPU POR Power On Reset See System Resets Interrupts and Opera...

Page 5: ...ondition Register Bit Accessibility and Initial Condition Key Bit Accessibility rw Read write r Read only r0 Read as 0 r1 Read as 1 w Write only w0 Write as 0 w1 Write as 1 w No register bit implemented writing a 1 results in a pulse The register bit is always read as 0 h0 Cleared by hardware h1 Set by hardware 0 1 Condition after PUC 0 1 Condition after POR ...

Page 6: ...vi ...

Page 7: ...rupts and Operating Modes 2 1 2 1 System Reset and Initialization 2 2 2 1 1 Brownout Reset BOR 2 3 2 1 2 Device Initial Conditions After System Reset 2 4 2 2 Interrupts 2 5 2 2 1 Non Maskable Interrupts NMI 2 6 2 2 2 Maskable Interrupts 2 9 2 2 3 Interrupt Processing 2 10 2 2 4 Interrupt Vectors 2 12 2 2 5 Special Function Registers SFRs 2 12 2 3 Operating Modes 2 13 2 3 1 Entering and Exiting Low...

Page 8: ...ngths 3 72 3 4 5 Instruction Set Description 3 74 4 16 Bit MSP430X CPU 4 1 4 1 CPU Introduction 4 2 4 2 Interrupts 4 4 4 3 CPU Registers 4 5 4 3 1 The Program Counter PC 4 5 4 3 2 Stack Pointer SP 4 7 4 3 3 Status Register SR 4 9 4 3 4 The Constant Generator Registers CG1 and CG2 4 11 4 3 5 The General Purpose Registers R4 to R15 4 12 4 4 Addressing Modes 4 15 4 4 1 Register Mode 4 16 4 4 2 Indexe...

Page 9: ... Generator 6 6 6 3 2 Erasing Flash Memory 6 7 6 3 3 Writing Flash Memory 6 11 6 3 4 Flash Memory Access During Write or Erase 6 17 6 3 5 Stopping a Write or Erase Cycle 6 18 6 3 6 Marginal Read Mode 6 18 6 3 7 Configuring and Accessing the Flash Memory Controller 6 18 6 3 8 Flash Memory Controller Interrupts 6 19 6 3 9 Programming Flash Memory Devices 6 19 6 4 Flash Memory Registers 6 21 7 Supply ...

Page 10: ...sfers 10 14 10 2 5 DMA Channel Priorities 10 14 10 2 6 DMA Transfer Cycle Time 10 15 10 2 7 Using DMA with System Interrupts 10 16 10 2 8 DMA Controller Interrupts 10 16 10 2 9 Using the USCI_B I2C Module with the DMA Controller 10 18 10 2 10 Using ADC12 with the DMA Controller 10 18 10 2 11 Using DAC12 With the DMA Controller 10 18 10 2 12 Writing to Flash With the DMA Controller 10 18 10 3 DMA R...

Page 11: ...asic Timer1 Counter Two 13 4 13 2 3 16 Bit Counter Mode 13 4 13 2 4 Basic Timer1 Operation Signal fLCD 13 5 13 2 5 Basic Timer1 Interrupts 13 5 13 3 Basic Timer1 Registers 13 6 14 Real Time Clock 14 1 14 1 RTC Introduction 14 2 14 2 Real Time Clock Operation 14 4 14 2 1 Counter Mode 14 4 14 2 2 Calendar Mode 14 5 14 2 3 RTC and Basic Timer1 Interaction 14 5 14 2 4 Real Time Clock Interrupts 14 6 1...

Page 12: ...SART Operation UART Mode 17 4 17 2 1 USART Initialization and Reset 17 4 17 2 2 Character Format 17 4 17 2 3 Asynchronous Communication Formats 17 5 17 2 4 USART Receive Enable 17 9 17 2 5 USART Transmit Enable 17 10 17 2 6 USART Baud Rate Generation 17 11 17 2 7 USART Interrupts 17 17 17 3 USART Registers UART Mode 17 21 18 USART Peripheral Interface SPI Mode 18 1 18 1 USART Introduction SPI Mode...

Page 13: ...USCI Registers UART Mode 19 27 20 Universal Serial Communication Interface SPI Mode 20 1 20 1 USCI Overview 20 2 20 2 USCI Introduction SPI Mode 20 3 20 3 USCI Operation SPI Mode 20 5 20 3 1 USCI Initialization and Reset 20 6 20 3 2 Character Format 20 6 20 3 3 Master Mode 20 7 20 3 4 Slave Mode 20 9 20 3 5 SPI Enable 20 10 20 3 6 Serial Clock Control 20 11 20 3 7 Using the SPI Mode with Low Power...

Page 14: ... Comparator_A Operation 23 4 23 2 1 Comparator 23 4 23 2 2 Input Analog Switches 23 4 23 2 3 Output Filter 23 5 23 2 4 Voltage Reference Generator 23 5 23 2 5 Comparator_A Port Disable Register CAPD 23 6 23 2 6 Comparator_A Interrupts 23 6 23 2 7 Comparator_A Used to Measure Resistive Elements 23 7 23 3 Comparator_A Registers 23 9 24 LCD Controller 24 1 24 1 LCD Controller Introduction 24 2 24 2 L...

Page 15: ...2 5 Sample and Conversion Timing 26 7 26 2 6 Conversion Memory 26 10 26 2 7 ADC12 Conversion Modes 26 10 26 2 8 Using the Integrated Temperature Sensor 26 16 26 2 9 ADC12 Grounding and Noise Considerations 26 17 26 2 10 ADC12 Interrupts 26 18 26 3 ADC12 Registers 26 20 27 SD16 27 1 27 1 SD16 Introduction 27 2 27 2 SD16 Operation 27 4 27 2 1 ADC Core 27 4 27 2 2 Analog Input Range and PGA 27 4 27 2...

Page 16: ... the DAC12 Voltage Output 29 6 29 2 4 DAC12_xDAT Data Format 29 7 29 2 5 DAC12 Output Amplifier Offset Calibration 29 8 29 2 6 Grouping Multiple DAC12 Modules 29 9 29 2 7 DAC12 Interrupts 29 10 29 3 DAC12 Registers 29 11 30 Scan IF 30 1 30 1 Scan IF Introduction 30 2 30 2 Scan IF Operation 30 4 30 2 1 Scan IF Analog Front End 30 4 30 2 2 Scan IF Timing State Machine 30 14 30 2 3 Scan IF Processing...

Page 17: ... 1 Introduction Introduction This chapter describes the architecture of the MSP430 Topic Page 1 1 Architecture 1 2 1 2 Flexible Clock System 1 2 1 3 Embedded Emulation 1 3 1 4 Address Space 1 4 Chapter 1 ...

Page 18: ...ze J Large register file eliminates working file bottleneck J Compact core design reduces power consumption and cost J Optimized for modern high level programming J Only 27 core instructions and seven addressing modes J Extensive vectored interrupt capability In system programmable Flash permits flexible code changes field upgrades and data logging 1 2 Flexible Clock System The clock system is des...

Page 19: ...TAG 1 3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources The benefits of embedded emulation include Unobtrusive development and debug with full speed execution breakpoints and single steps in an application are supported Development is in system subject to the same characteristics as the final applicati...

Page 20: ...ipheral Modules Special Function Registers 0FFFFh 0FFDFh 0200h 01FFh 0100h 0FFh 010h 0Fh 0h Word Byte Word Byte Word Byte Byte Word Byte 10000h Flash ROM Access Word Byte 1 4 1 Flash ROM The start address of Flash ROM depends on the amount of Flash ROM present and varies by device The end address for Flash ROM is 0FFFFh for devices with less than 60kB of Flash ROM otherwise it is device dependent ...

Page 21: ...dictable data in the high byte If word data is written to a byte module only the low byte is written into the peripheral register ignoring the high byte 1 4 4 Special Function Registers SFRs Some peripheral functions are configured in the SFRs The SFRs are located in the lower 16 bytes of the address space and are organized by byte SFRs must be accessed using byte instructions only See the device ...

Page 22: ...ddress Space 1 6 Introduction Figure 1 3 Bits Bytes and Words in a Byte Organized Memory 15 7 14 6 Bits Bits 9 1 8 0 Byte Byte Word High Byte Word Low Byte xxxAh xxx9h xxx8h xxx7h xxx6h xxx5h xxx4h xxx3h ...

Page 23: ...rating Modes This chapter describes the MSP430x4xx system resets interrupts and operating modes Topic Page 2 1 System Reset and Initialization 2 2 2 2 Interrupts 2 5 2 3 Operating Modes 2 13 2 4 Principles for Low Power Applications 2 16 2 5 Connection of Unused Pins 2 16 Chapter 2 ...

Page 24: ...wd1 Resetwd2 S S Delay RST NMI WDTNMI WDTTMSEL WDTQn WDTIFG EQU MCLK POR PUC S from flash module KEYV SVS_POR 0 V VCC 0 V Brownout Reset From watchdog timer peripheral module 50us A POR is a device reset A POR is only generated by the following three events Powering up the device A low signal on the RST NMI pin when configured in the reset mode An SVS low condition when PORON 1 A PUC is always gen...

Page 25: ... becomes active when VCC crosses the VCC start level It remains active until VCC crosses the V B_IT threshold and the delay t BOR elapses The delay t BOR is adaptive being longer for a slow ramping VCC The hysteresis Vhys B_ IT ensures that the supply voltage must drop below V B_IT to generate another POR signal from the brownout reset circuitry Figure 2 2 Brownout Timing t BOR VCC start VCC V B_I...

Page 26: ...SR is reset The watchdog timer powers up active in watchdog mode Program counter PC is loaded with address contained at reset vector location 0FFFEh CPU execution begins at that address Software Initialization After a system reset user software must initialize the MSP430 for the application requirements The following must occur Initialize the SP typically to the top of RAM Initialize the watchdog ...

Page 27: ...e CPU NMIRS the higher the priority Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously There are three types of interrupts System reset Non maskable NMI Maskable Figure 2 3 Interrupt Priority Bus Grant Module 1 Module 2 WDT Timer Module m Module n 1 2 1 2 1 2 1 2 1 NMIRS GIE CPU OSCfault Reset NMI PUC Circuit PUC WDT Security Key Priority ...

Page 28: ...ction of the RST NMI pins is selected in the watchdog control register WDTCTL If the RST NMI pin is set to the reset function the CPU is held in the reset state as long as the RST NMI pin is held low After the input changes to a high state the CPU starts program execution at the word address stored in the reset vector 0FFFEh If the RST NMI pin is configured by user software to the NMI function a s...

Page 29: ...enerator BOR POR PUC WDTQn EQU PUC POR PUC POR NMIRS Clear S WDTIFG IRQ WDTIE Clear IE1 0 PUC POR IRQA WDTTMSEL Counter IFG1 0 WDTNMI WDTTMSEL WDTNMIES Watchdog Timer Module Clear S IFG1 4 PUC Clear IE1 4 PUC NMIIFG NMIIE S IFG1 1 Clear IE1 1 PUC OFIFG OFIE OSCFault NMI_IRQA IRQA Interrupt Request Accepted RST NMI S FCTL3 2 Clear IE1 5 ACCVIFG ACCVIE PUC ACCV WDT SVS_POR ...

Page 30: ...etermine if the NMI was caused by an oscillator fault A PUC signal can trigger an oscillator fault because the PUC switches the LFXT1 to LF mode therefore switching off the HF mode The PUC signal also switches off the XT2 oscillator Flash Access Violation The flash ACCVIFG flag is set when a flash access violation occurs The flash access violation can be enabled to generate an NMI interrupt by set...

Page 31: ... Oscillator Fault Handler User s Software Flash Access Violation Handler User s Software External NMI Handler Optional RETI End of NMI Interrupt Handler Note Enabling NMI Interrupts with ACCVIE NMIIE and OFIE To prevent nested NMI interrupts the ACCVIE NMIIE and OFIE enable bits should not be set inside of an NMI interrupt service routine 2 2 2 Maskable Interrupts Maskable interrupts are caused by...

Page 32: ...rently executing instruction is completed 2 The PC which points to the next instruction is pushed onto the stack 3 The SR is pushed onto the stack 4 The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service 5 The interrupt request flag resets automatically on single source flags Multiple source flags remain set for s...

Page 33: ... All previous settings of GIE CPUOFF etc are now in effect regardless of the settings used during the interrupt service routine 2 The PC pops from the stack and begins execution at the point where it was interrupted Figure 2 7 Return From Interrupt Item1 Item2 SP TOS Item1 Item2 SP TOS PC SR Before After PC SR Return From Interrupt Interrupt nesting is enabled if the GIE bit is set inside an inter...

Page 34: ...V Reset 0FFFEh 15 highest NMI oscillator fault flash memory access violation NMIIFG OFIFG ACCVIFG non maskable non maskable non maskable 0FFFCh 14 device specific 0FFFAh 13 device specific 0FFF8h 12 device specific 0FFF6h 11 Watchdog timer WDTIFG maskable 0FFF4h 10 device specific 0FFF2h 9 device specific 0FFF0h 8 device specific 0FFEEh 7 device specific 0FFECh 6 device specific 0FFEAh 5 device sp...

Page 35: ...tus register The advantage of including the CPUOFF OSCOFF SCG0 and SCG1 mode control bits in the status register is that the present operating mode is saved onto the stack during an interrupt service routine Program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine Program flow can be returned to a different operating mode by mani...

Page 36: ...lation WDT Active Time Expired Overflow WDTIFG 1 WDTIFG 1 RST NMI Reset Active VCC On WDTIFG 0 LPM1 CPU Off FLL Off 41x 42x MCLK On 43x 44x MCLK off ACLK On CPUOFF 1 SCG0 1 SCG1 1 SCG1 SCG0 OSCOFF CPUOFF Mode CPU and Clocks Status 0 0 0 0 Active CPU is active all enabled clocks are active 0 0 0 1 LPM0 CPU MCLK are disabled 41x 42x peripheral MCLK remains on SMCLK ACLK are active 0 1 0 1 LPM1 CPU M...

Page 37: ... CPUOFF 0 SP Exit LPM0 on RETI RETI Enter LPM3 Example BIS GIE CPUOFF SCG1 SCG0 SR Enter LPM3 Program stops here Exit LPM3 Interrupt Service Routine BIC CPUOFF SCG1 SCG0 0 SP Exit LPM3 on RETI RETI Extended Time in Low Power Modes The negative temperature coefficient of the DCO should be considered when the DCO is disabled for extended low power mode periods If the temperature changes significantl...

Page 38: ...iven functions For example Timer_A and Timer_B can automatically generate PWM and capture external timing with no CPU resources Calculated branching and fast table look ups should be used in place of flag polling and long software calculations Avoid frequent subroutine and function calls due to overhead For longer software routines single cycle CPU registers should be used 2 5 Connection of Unused...

Page 39: ...it CPU RISC 16 Bit CPU This chapter describes the MSP430 CPU addressing modes and instruction set Topic Page 3 1 CPU Introduction 3 2 3 2 CPU Registers 3 4 3 3 Addressing Modes 3 9 3 4 Instruction Set 3 17 Chapter 3 ...

Page 40: ...y instruction usable with every addressing mode Full register access including program counter status registers and stack pointer Single cycle register operations Large 16 bit register file reduces fetches to memory 16 bit address bus allows direct access and branching throughout entire memory range 16 bit data bus allows direct manipulation of word wide arguments Constant generator provides six m...

Page 41: ... N 16 bit ALU dst src R8 General Purpose R9 General Purpose R10 General Purpose R11 General Purpose R12 General Purpose R13 General Purpose R14 General Purpose R15 General Purpose R4 General Purpose R5 General Purpose R6 General Purpose R7 General Purpose R3 CG2 Constant Generator R2 SR CG1 Status R1 SP Stack Pointer R0 PC Program Counter 0 0 16 MCLK ...

Page 42: ...an even number of bytes two four or six and the PC is incremented accordingly Instruction accesses in the 64 KB address space are performed on word boundaries and the PC is aligned to even addresses Figure 3 2 shows the program counter Figure 3 2 Program Counter 0 15 0 Program Counter Bits 15 to 1 1 The PC can be addressed with all instructions and addressing modes A few examples MOV LABEL PC Bran...

Page 43: ...0 15 0 Stack Pointer Bits 15 to 1 1 MOV 2 SP R6 Item I2 R6 MOV R7 0 SP Overwrite TOS with R7 PUSH 0123h Put 0123h onto TOS POP R8 R8 0123h Figure 3 4 Stack Usage I3 I1 I2 I3 0xxxh 0xxxh 2 0xxxh 4 0xxxh 6 0xxxh 8 I1 I2 SP 0123h SP I1 I2 I3 SP PUSH 0123h POP R8 Address 0123h The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 3 5 Figure...

Page 44: ...ive otherwise reset SCG1 System clock generator 1 This bit when set turns off the DCO dc generator if DCOCLK is not used for MCLK or SMCLK SCG0 System clock generator 0 This bit when set turns off the FLL loop control OSCOFF Oscillator Off This bit when set turns off the LFXT1 crystal oscillator when LFXT1CLK is not use for MCLK or SMCLK CPUOFF CPU off This bit when set turns off the CPU GIE Gener...

Page 45: ...enerator advantages are No special instructions required No additional code word for the six constants No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act as source only registers Constan...

Page 46: ... Byte Register Operations Unused High Byte Low Byte Byte Register Byte Operation 0h High Byte Low Byte Byte Byte Register Operation Register Memory Register Memory Example Register Byte Operation Example Byte Register Operation R5 0A28Fh R5 01202h R6 0203h R6 0223h Mem 0203h 012h Mem 0223h 05Fh ADD B R5 0 R6 ADD B R6 R5 08Fh 05Fh 012h 002h 0A1h 00061h Mem 0203h 0A1h R5 00061h C 0 Z 0 N 1 C 0 Z 0 N...

Page 47: ...llowing the instruction contains the absolute address X is stored in the next word Indexed mode X SR is used 10 Indirect register mode Rn Rn is used as a pointer to the operand 11 Indirect autoincrement Rn Rn is used as a pointer to the operand Rn is incremented afterwards by 1 for B instructions and by 2 for W instructions 11 Immediate mode N The word following the instruction contains the immedi...

Page 48: ...ove the content of R10 to R11 R10 is not affected Comment Valid for source and destination Example MOV R10 R11 0A023h R10 R11 Before After PC 0FA15h PCold 0A023h R10 R11 PC PCold 2 0A023h Note Data in Registers The data in the register can be accessed using word or byte instructions If byte instructions are used the high byte is always 0 in the result The status bits are handled according to the r...

Page 49: ...cted In indexed mode the program counter is incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV 2 R5 6 R6 00006h Address Space 00002h 04596h PC 0FF16h 0FF14h 0FF12h 0xxxxh 05555h 01094h 01092h 01090h 0xxxxh 0xxxxh 01234h 01084h 01082h 01080h 0xxxxh 01080h 0108Ch R5 R6 0108Ch 0006h 01092h 01080h 0002h 01082h Re...

Page 50: ...e assembler computes and inserts offsets X and Y automatically With symbolic mode the program counter PC is incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV EDE TONI Source address EDE 0F016h Dest address TONI 01114h 011FEh Address Space 0F102h 04090h PC 0FF16h 0FF14h 0FF12h 0xxxxh 0A123h 0F018h 0F016h 0F01...

Page 51: ...tion continues with the next instruction Comment Valid for source and destination Example MOV EDE TONI Source address EDE 0F016h dest address TONI 01114h 01114h Address Space 0F016h 04292h PC 0FF16h 0FF14h 0FF12h 0xxxxh 0A123h 0F018h 0F016h 0F014h 0xxxxh 0xxxxh 01234h 01116h 01114h 01112h 0xxxxh Register Before 01114h Address Space 0F016h 04292h PC 0FF16h 0FF14h 0FF12h 0xxxxh 0A123h 0F018h 0F016h ...

Page 52: ...address contents of R11 The registers are not modified Comment Valid only for source operand The substitute for destination operand is 0 Rd Example MOV B R10 0 R11 0000h Address Space 04AEBh PC 0FF16h 0FF14h 0FF12h 0xxxxh 05BC1h 0xxxxh 0xxh 012h 0xxh 0FA33h 002A7h R10 R11 Register Before 0000h Address Space 04AEBh PC 0FF16h 0FF14h 0FF12h 0xxxxh 05BC1h 0FA34h 0FA32h 0FA30h 0xxxxh 0xxh 05Bh 002A8h 0...

Page 53: ...eful for table processing Comment Valid only for source operand The substitute for destination operand is 0 Rd plus second instruction INCD Rd Example MOV R10 0 R11 00000h Address Space 04ABBh PC 0FF16h 0FF14h 0FF12h 0xxxxh 05BC1h 0FA34h 0FA32h 0FA30h 0xxxxh 0xxxxh 01234h 010AAh 010A8h 010A6h 0xxxxh 0FA32h 010A8h R10 R11 Register Before Address Space 0xxxxh 05BC1h 0FA34h 0FA32h 0FA30h 0xxxxh 0xxxx...

Page 54: ...ich is contained in the word following the instruction to destination address TONI When fetching the source the program counter points to the word following the instruction and moves the contents to the destination Comment Valid only for a source operand Example MOV 45h TONI 01192h Address Space 00045h 040B0h PC 0FF16h 0FF14h 0FF12h 0xxxxh 01234h 0xxxxh 0FF16h 01192h 010A8h Register Before 01192h ...

Page 55: ...d to access word data or word peripherals If no extension is used the instruction is a word instruction The source and destination of an instruction are defined by the following fields src The source operand defined by As and S reg dst The destination operand defined by Ad and D reg As The addressing bits responsible for the addressing mode used for the source src S reg The working register used f...

Page 56: ...rc dst src dst ADD B src dst src dst dst ADDC B src dst src dst C dst SUB B src dst dst not src 1 dst SUBC B src dst dst not src C dst CMP B src dst dst src DADD B src dst src dst C dst decimally BIT B src dst src and dst 0 BIC B src dst not src and dst dst BIS B src dst src or dst dst XOR B src dst src xor dst dst AND B src dst src and dst dst 0 The status bit is affected The status bit is not af...

Page 57: ...Reg D Reg Operation Status Bits D Reg V N Z C RRC B dst C MSB LSB C RRA B dst MSB MSB LSB C 0 PUSH B src SP 2 SP src SP SWPB dst Swap bytes CALL dst SP 2 SP PC 2 SP dst PC RETI TOS SR SP 2 SP TOS PC SP 2 SP SXT dst Bit 7 Bit 8 Bit 15 0 The status bit is affected The status bit is not affected 0 The status bit is cleared 1 The status bit is set All addressing modes are possible for the CALL instruc...

Page 58: ...ro bit is reset JC Label Jump to label if carry bit is set JNC Label Jump to label if carry bit is reset JN Label Jump to label if negative bit is set JGE Label Jump to label if N XOR V 0 JL Label Jump to label if N XOR V 1 JMP Label Jump to label unconditionally Conditional jumps support program branching relative to the PC and do not affect the status bits The possible jump range is from 511 to ...

Page 59: ...tive Z Set if result is zero reset otherwise C Set if dst was incremented from 0FFFFh to 0000 reset otherwise Set if dst was incremented from 0FFh to 00 reset otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed to by R12 ADD R13 0 R12 Add LSDs ADC 2 R12 Ad...

Page 60: ...tatus Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the result cleared if not V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is increased by 10 The jump to TONI is performed on a carry ADD 10 R5 JC TONI Carry occurred No carry Example R5 is increased by 10...

Page 61: ...herwise C Set if there is a carry from the MSB of the result reset otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 32 bit counter pointed to by R13 is added to a 32 bit counter eleven words 20 2 2 2 above the pointer in R13 ADD R13 20 R13 ADD LSDs with no carry in ADDC R13 20 R13 ADD MSDs with carry resulting from the LS...

Page 62: ...ise C Set if result is not zero reset otherwise NOT Zero V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits set in R5 are used as a mask 0AA55h for the word addressed by TOM If the result is zero a branch is taken to label TONI MOV 0AA55h R5 Load mask into register R5 AND R5 TOM mask word addressed by TOM with R5 JZ TONI Result is not zero or AND 0AA55h TOM JZ TONI Example T...

Page 63: ...perand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The six MSBs of the RAM word LEO are cleared BIC 0FC00h LEO Clear 6 MSBs in MEM LEO Example The five MSBs of the RAM byte LEO are cleared BIC B 0F8h LEO Clear 5 MSBs in R...

Page 64: ... the destination operand are logically ORed The result is placed into the destination The source operand is not affected Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The six LSBs of the RAM word TOM are set BIS 003Fh TOM set the six LSBs in RAM location TOM Example The three MSBs of RAM byte TOM are set BIS B 0E0h TOM set the 3 MSBs in RAM locat...

Page 65: ... R8 bit 9 of R8 set JNZ TOM Yes branch to TOM No proceed Example If bit 3 of R8 is set a branch is taken to label TOM BIT B 8 R8 JC TOM Example A serial communication receive bit RCV is tested Because the carry bit is equal to the state of the tested bit while using the BIT instruction to test a single bit the carry bit is used by the subsequent instruction the read information is shifted into reg...

Page 66: ...o the address contained in absolute address EXEC Core instruction MOV X 0 PC Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC Indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer in R5 afterwards Th...

Page 67: ...ained in EXEC SP 2 SP PC 2 SP X PC PC Indirect address CALL EXEC Call on the address contained in absolute address EXEC SP 2 SP PC 2 SP X 0 PC Indirect address CALL R5 Call on the address contained in R5 SP 2 SP PC 2 SP R5 PC Indirect R5 CALL R5 Call on the address contained in the word pointed to by R5 SP 2 SP PC 2 SP R5 PC Indirect indirect R5 CALL R5 Call on the address contained in the word po...

Page 68: ...st or CLR W dst CLR B dst Operation 0 dst Emulation MOV 0 dst MOV B 0 dst Description The destination operand is cleared Status Bits Status bits are not affected Example RAM word TONI is cleared CLR TONI 0 TONI Example Register R5 is cleared CLR R5 Example RAM byte TONI is cleared CLR B TONI 0 TONI ...

Page 69: ... a word instruction Status Bits N Not affected Z Not affected C Cleared V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit decimal counter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C 0 defines start DADD R13 0 R12 add 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter ...

Page 70: ... result is placed into the destination The clear negative bit instruction is a word instruction Status Bits N Reset to 0 Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The Negative bit in the status register is cleared This avoids special treatment with negative numbers of the subroutine called CLRN CALL SUBR SUBR JN SUBRET If input is negativ...

Page 71: ...nt 02h is inverted 0FFFDh and logically ANDed with the destination operand The result is placed into the destination The clear zero bit instruction is a word instruction Status Bits N Not affected Z Reset to 0 C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The zero bit in the status register is cleared CLRZ ...

Page 72: ... result reset otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 and R6 are compared If they are equal the program continues at the label EQUAL CMP R5 R6 R5 R6 JEQ EQUAL YES JUMP Example Two RAM blocks are compared If they are not equal the program branches to the label ERROR MOV NUM R5 number of words to be compared MOV BLO...

Page 73: ...9 to 0000 reset otherwise Set if destination increments from 99 to 00 reset otherwise V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example The four digit decimal number contained in R5 is added to an eight digit deci mal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD R5 0 R8 Add LSDs C DADC 2 R8 Add carry to MSD Example The two digit dec...

Page 74: ...ost The result is not defined for non BCD numbers Status Bits N Set if the MSB is 1 reset otherwise Z Set if result is zero reset otherwise C Set if the result is greater than 9999 Set if the result is greater than 99 V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example The eight digit BCD number contained in R5 and R6 is added decimally to an eight digit BCD number contained in R3...

Page 75: ...rs otherwise reset Set if initial value of destination was 08000h otherwise reset Set if initial value of destination was 080h otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination addr...

Page 76: ... occurs otherwise reset Set if initial value of destination was 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 words from memory location starting with EDE to memory location starting with TONI Tables should not over...

Page 77: ...ted Example The general interrupt enable GIE bit in the status register is cleared to allow a nondisrupted move of a 32 bit counter This ensures that the counter is not modified during the move by any interrupt DINT All interrupt events using the GIE bit are disabled NOP MOV COUNTHI R5 Copy counter MOV COUNTLO R6 EINT All interrupt events using the GIE bit are enabled Note Disable Interrupt If any...

Page 78: ...orts P1 2 to P1 7 P1IN is the address of the register where all port bits are read P1IFG is the address of the register where all interrupt events are latched PUSH B P1IN BIC B SP P1IFG Reset only accepted flags EINT Preset port 1 interrupt flags stored on stack other interrupts are allowed BIT Mask SP JEQ MaskOK Flags are present identically to mask jump MaskOK BIC Mask SP INCD SP Housekeeping in...

Page 79: ... is negative reset if positive Z Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise C Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise V Set if dst contained 07FFFh reset otherwise Set if dst contained 07Fh reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The status byte STATUS of a process is increment...

Page 80: ...herwise C Set if dst contained 0FFFEh or 0FFFFh reset otherwise Set if dst contained 0FEh or 0FFh reset otherwise V Set if dst contained 07FFEh or 07FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation which is...

Page 81: ...t otherwise Set if dst contained 0FFh reset otherwise C Set if result is not zero reset otherwise NOT Zero Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example Content of R5 is negated twos complement MOV 00AEh R5 R5 000AEh INV R5 Invert R5 R5 0FF51h INC R5 R5 is now negated R5 ...

Page 82: ...ter If C is reset the next instruction following the jump is executed JC jump if carry higher or same is used for the comparison of unsigned numbers 0 to 65536 Status Bits Status bits are not affected Example The P1IN 1 signal is used to define or control the program flow BIT 01h P1IN State of signal Carry JC PROGA If carry 1 then execute program routine A Carry 0 execute program here Example R5 i...

Page 83: ...s added to the program counter If Z is not set the instruction following the jump is executed Status Bits Status bits are not affected Example Jump to address TONI if R7 contains zero TST R7 Test R7 JZ TONI if zero JUMP Example Jump to address LEO if R6 is equal to the table contents CMP R6 Table R5 Compare content of R6 with content of MEM table address content of R5 JEQ LEO Jump if both data are...

Page 84: ...sted If both N and V are set or reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If only one is set the instruction following the jump is executed This allows comparison of signed integers Status Bits Status bits are not affected Example When the content of R6 is greater or equal to the memory pointed to by R7 the program continues at label EDE CMP R...

Page 85: ...d If only one is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If both N and V are set or reset the instruction following the jump is executed This allows comparison of signed integers Status Bits Status bits are not affected Example When the content of R6 is less than the memory pointed to by R7 the program continues at label EDE CMP R7 R6 R6 R7 co...

Page 86: ... 2 offset PC Description The 10 bit signed offset contained in the instruction LSBs is added to the program counter Status Bits Status bits are not affected Hint This one word instruction replaces the BRANCH instruction in the range of 511 to 512 words relative to the current program counter ...

Page 87: ...d in the instruction LSBs is added to the program counter If N is reset the next instruction following the jump is executed Status Bits Status bits are not affected Example The result of a computation in R5 is to be subtracted from COUNT If the result is negative COUNT is to be cleared and the program continues execution in another path SUB R5 COUNT COUNT R5 COUNT JN L 1 If negative continue with ...

Page 88: ... C is set the next instruction following the jump is executed JNC jump if no carry lower is used for the comparison of unsigned numbers 0 to 65536 Status Bits Status bits are not affected Example The result in R6 is added in BUFFER If an overflow occurs an error handling routine at address ERROR is used ADD R6 BUFFER BUFFER R6 BUFFER JNC CONT No carry jump to CONT ERROR Error handler start CONT Co...

Page 89: ...he status register zero bit Z is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is set the next instruction following the jump is executed Status Bits Status bits are not affected Example Jump to address TONI if R7 and R8 have different contents CMP R7 R8 COMPARE R7 WITH R8 JNE TONI if different jump if equal continue ...

Page 90: ... contents of table EDE word data are copied to table TOM The length of the tables must be 020h locations MOV EDE R10 Prepare pointer MOV 020h R9 Prepare counter Loop MOV R10 TOM EDE 2 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter 0 continue copying Copying completed Example The contents of table EDE byte data are copied to table TOM The length of the tables shoul...

Page 91: ...ing Note Emulating No Operation Instruction Other instructions can emulate the NOP function while providing different numbers of instruction cycles and code words Some examples are Examples MOV 0 R3 1 cycle 1 word MOV 0 R4 0 R4 6 cycles 3 words MOV R4 0 R4 5 cycles 2 words BIC 0 EDE R4 4 cycles 2 words JMP 2 2 cycles 1 word BIC 0 R5 1 cycle 1 word However care should be taken when using these exam...

Page 92: ...POP SR Restore status register Example The contents of RAM byte LEO is restored from the stack POP B LEO The low byte of the stack is moved to LEO Example The contents of R7 is restored from the stack POP B R7 The low byte of the stack is moved to R7 the high byte of R7 is 00h Example The contents of the memory pointed to by R7 and the status register are restored from the stack POP B 0 R7 The low...

Page 93: ... pointer TOS Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The contents of the status register and R8 are saved on the stack PUSH SR save status register PUSH R8 save R8 Example The contents of the peripheral TCDAT is saved on the stack PUSH B TCDAT save data from 8 bit peripheral module address TCDAT onto stack Note The System Stack Pointer The ...

Page 94: ...ax RET Operation SP PC SP 2 SP Emulation MOV SP PC Description The return address pushed onto the stack by a CALL instruction is moved to the program counter The program continues at the code address following the subroutine call Status Bits Status bits are not affected ...

Page 95: ...s the consecutive step after the interrupted program flow Restoration is performed by replacing the present PC contents with the TOS memory contents The stack pointer SP is incremented Status Bits N restored from system stack Z restored from system stack C restored from system stack V restored from system stack Mode Bits OSCOFF CPUOFF and GIE are restored from system stack Example Figure 3 13 illu...

Page 96: ...e Word 0 An overflow occurs if dst 040h and dst 0C0h before the operation is performed the result has changed sign Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 04000h dst 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h dst 0C0h...

Page 97: ... reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 04000h dst 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h dst 0C0h reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is shifted left one position RLC R5 R5 x 2 C R5 Example The input P1IN 1 information is shifted into the LSB of R5 BIT ...

Page 98: ...et if result is zero reset otherwise C Loaded from the LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 RRA R5 R5 2 R5 The value in R5 is multiplied by 0 75 0 5 0 25 PUSH R5 Hold R5 temporarily using stack RRA R5 R5 0 5 R5 ADD SP R5 R5 0 5 R5 1 5 R5 R5 RRA R5 1 5 R5 0...

Page 99: ...d into the carry bit C Figure 3 17 Destination Operand Carry Right Shift 15 0 7 0 C Byte Word Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Loaded from the LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC R5 R5 2 8000h R5 Example R5 is s...

Page 100: ...if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit counter pointed to by R13 is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 Subtract LSDs SBC 2 R12 Subtract carry fro...

Page 101: ...cted Mode Bits OSCOFF CPUOFF and GIE are not affected Example Emulation of the decimal subtraction Subtract R5 from R6 decimally Assume that R5 03987h and R6 04137h DSUB ADD 06666h R5 Move content R5 from 0 9 to 6 0Fh R5 03987h 06666h 09FEDh INV R5 Invert this result back to 0 9 R5 NOT R5 06012h SETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 010000h R5 1 R6 R6 R5 1 R6 0150h ...

Page 102: ...16 Bit CPU SETN Set negative bit Syntax SETN Operation 1 N Emulation BIS 4 SR Description The negative bit N is set Status Bits N Set Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected ...

Page 103: ...ISC 16 Bit CPU SETZ Set zero bit Syntax SETZ Operation 1 Z Emulation BIS 2 SR Description The zero bit Z is set Status Bits N Not affected Z Set C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected ...

Page 104: ...and is not affected The previous contents of the destination are lost Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example See example a...

Page 105: ...Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Two floating point mantissas 24 bits are subtracted LSBs are in R13 and R10 MSBs are in R12 and R...

Page 106: ...tatus Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Figure 3 18 Destination Operand Byte Swap 15 8 7 0 Example MOV 040BFh R7 0100000010111111 R7 SWPB R7 1011111101000000 in R7 Example The value in R5 is multiplied by 256 The result is stored in R5 R4 SWPB R5 MOV R5 R4 Copy the swapped value to R4 BIC 0FF00h R5 Correct the result BIC 00FFh R4 Correct the result ...

Page 107: ...ositive Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Figure 3 19 Destination Operand Sign Extension 15 8 7 0 Example R7 is loaded with the P1IN value The operation of the sign extend instruction expands bit 8 to bit 15 with the value of bit 7 R7 is then added to R6 MOV B P1IN R7 P1IN 080h 1000 ...

Page 108: ...rwise C Set V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS R7 is positive but not zero R7NEG R7 is negative R7ZERO R7 is zero Example The low byte of R7 is tested If it is negative continue at R7NEG if it is positive b...

Page 109: ...Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Set if both operands are negative Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits set in R6 toggle the bits in the RAM word TONI XOR R6 TONI Toggle bits of word TONI on the bits set in R6 Example The bits set in R6 toggle the bits in the RAM byte TONI XOR B R6 TONI Toggle bits of byte T...

Page 110: ... and Lengths Table 3 15 lists the length and CPU cycles for all addressing modes of format II instructions Table 3 15 Format II Instruction Cycles and Lengths No of Cycles Addressing Mode RRA RRC SWPB SXT PUSH CALL Length of Instruction Example Rn 1 3 4 1 SWPB R5 Rn 3 4 4 1 RRC R9 Rn 3 5 5 1 SWPB R10 N See note 4 5 2 CALL 0F00h X Rn 4 5 5 2 CALL 2 R7 EDE 4 5 5 2 PUSH EDE EDE 4 5 5 2 SXT EDE Note I...

Page 111: ...DE Rn Rm 2 1 AND R4 R5 PC 2 1 BR R8 x Rm 5 2 XOR R5 8 R6 EDE 5 2 MOV R5 EDE EDE 5 2 XOR R5 EDE Rn Rm 2 1 ADD R5 R6 PC 3 1 BR R9 x Rm 5 2 XOR R5 8 R6 EDE 5 2 MOV R9 EDE EDE 5 2 MOV R9 EDE N Rm 2 2 MOV 20 R9 PC 3 2 BR 2AEh x Rm 5 3 MOV 0300h 0 SP EDE 5 3 ADD 33 EDE EDE 5 3 ADD 33 EDE x Rn Rm 3 2 MOV 2 R5 R7 PC 3 2 BR 2 R6 TONI 6 3 MOV 4 R7 TONI x Rm 6 3 ADD 4 R4 6 R9 TONI 6 3 MOV 2 R4 TONI EDE Rm 3 ...

Page 112: ...x 4xxx 8xxx Cxxx 1xxx 14xx 18xx 1Cxx 20xx 24xx 28xx 2Cxx 30xx 34xx 38xx 3Cxx 4xxx 5xxx 6xxx 7xxx 8xxx 9xxx Axxx Bxxx Cxxx Dxxx Exxx Fxxx RRC RRC B SWPB RRA RRA B SXT PUSH PUSH B CALL RETI 000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0 JNE JNZ JEQ JZ JNC JC JN JGE JL JMP MOV MOV B ADD ADD B ADDC ADDC B SUBC SUBC B SUB SUB B CMP CMP B DADD DADD B BIT BIT B BIC BIC B BIS BIS B XOR XO...

Page 113: ...estination dst 1 dst INCD B dst Double increment destination dst 2 dst INV B dst Invert destination not dst dst JC JHS label Jump if C set Jump if higher or same JEQ JZ label Jump if equal Jump if Z set JGE label Jump if greater or equal JL label Jump if less JMP label Jump PC 2 x offset PC JN label Jump if N set JNC JLO label Jump if C not set Jump if lower JNE JNZ label Jump if not equal Jump if...

Page 114: ...3 76 RISC 16 Bit CPU ...

Page 115: ...ess its addressing modes and instruction set The MSP430X CPU is implemented in all MSP430 devices that exceed 64 KB of address space Topic Page 4 1 CPU Introduction 4 2 4 2 Interrupts 4 4 4 3 CPU Registers 4 5 4 4 Addressing Modes 4 15 4 5 MSP430 and MSP430X Instructions 4 36 4 6 Instruction Set Description 4 58 Chapter 4 ...

Page 116: ...s completely backwards compatible with the MSP430 CPU The MSP430X CPU features include RISC architecture Orthogonal architecture Full register access including program counter status register and stack pointer Single cycle register operations Large register file reduces fetches to memory 20 bit address bus allows direct access and branching throughout the entire memory range without paging 16 bit ...

Page 117: ...Counter 19 R1 SP Pointer Stack General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose Memory Address Bus MAB MDB Memory Data Bus 16 20 16 20 bit ALU src dst Zero Z Carry C Overflow V Negative N MCLK 0 16 15 R2 SR Status Register ...

Page 118: ...lower 64 KB memory This means all interrupt handlers must start in the lower 64 KB memory even in MSP430X devices During an interrupt the program counter and the status register are pushed onto the stack as shown in Figure 4 2 The MSP430X architecture efficiently stores the complete 20 bit PC value by automatically appending the PC bits 19 16 to the stored SR value on the stack When the RETI instr...

Page 119: ...9 15 1 0 16 The PC can be addressed with all instructions and addressing modes A few examples MOV W LABEL PC Branch to address LABEL lower 64 KB MOVA LABEL PC Branch to address LABEL 1MB memory MOV W LABEL PC Branch to address in word LABEL lower 64 KB MOV W R14 PC Branch indirect to address in R14 lower 64 KB ADDA 4 PC Skip two words 1 MB memory The BR and CALL instructions reset the upper four P...

Page 120: ...the program counter with the return address after a CALLA instruction A CALL instruction stores only bits 15 0 of the PC Figure 4 4 Program Counter Storage on the Stack for CALLA Item n PC 19 16 PC 15 0 SPold SP The RETA instruction restores bits 19 0 of the program counter and adds 4 to the stack pointer The RET instruction restores bits 15 0 to the program counter and adds 2 to the stack pointer...

Page 121: ...ed into RAM by the user and is always aligned to even addresses Figure 4 6 shows the stack usage Figure 4 7 shows the stack usage when 20 bit address words are pushed Figure 4 5 Stack Pointer 0 Stack Pointer Bits 19 to 1 19 1 0 MOV W 2 SP R6 Copy Item I2 to R6 MOV W R7 0 SP Overwrite TOS with R7 PUSH 0123h Put 0123h on stack POP R8 R8 0123h Figure 4 6 Stack Usage I3 I1 I2 I3 0xxxh 0xxxh 2 0xxxh 4 ...

Page 122: ...instructions are described and shown in Figure 4 8 Figure 4 8 PUSH SP POP SP Sequence SP1 SPold SP1 PUSH SP The stack pointer is changed after a PUSH SP instruction SP1 SP2 POP SP The stack pointer is not changed after a POP SP instruction The POP SP instruction places SP1 into the stack pointer SP SP2 SP1 ...

Page 123: ...flows the signed variable range ADD B ADDX B A ADDC B ADDCX B A ADDA Set when positive positive negative negative negative positive otherwise reset SUB B SUBX B A SUBC B SUBCX B A SUBA CMP B CMPX B A CMPA Set when positive negative negative negative positive positive otherwise reset SCG1 System clock generator 1 This bit when set turns off the DCO dc generator if DCOCLK is not used for MCLK or SMC...

Page 124: ...PU Bit Description Z Zero bit This bit is set when the result of an operation is zero and cleared when the result is not zero C Carry bit This bit is set when the result of an operation produced a carry and cleared when no carry occurred ...

Page 125: ...he constant generator advantages are No special instructions required No additional code word for the six constants No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act as source only regi...

Page 126: ...w the handling of byte word and address word data Note the reset of the leading MSBs if a register is the destination of a byte or word instruction Figure 4 10 shows byte handling 8 bit data B suffix The handling is shown for a source register and a destination memory byte and for a source memory byte and a destination register Figure 4 10 Register Byte Byte Register Operation Unused High Byte Low...

Page 127: ...destination memory word and for a source memory word and a destination register Figure 4 11 Register Word Operation High Byte Low Byte Register Word Operation Register Memory Operation Memory Un used 19 16 15 0 8 7 Figure 4 12 Word Register Operation High Byte Low Byte Word Register Operation Register Memory Operation 0 Register Un used 19 16 15 0 8 7 ...

Page 128: ...nd for a source memory address word and a destination register Figure 4 13 Register Address Word Operation High Byte Low Byte Register Address Word Operation Register Memory Operation Memory Unused 0 Memory 2 Memory 2 19 16 15 0 8 7 Figure 4 14 Address Word Register Operation High Byte Low Byte Address Word Register Operation Register Memory Operation Register Unused Memory 2 19 16 15 0 8 7 ...

Page 129: ...uction contains the absolute address X is stored in the next word or stored in combination of the preceding extension word and the next word Indexed mode X SR is used 10 Indirect register mode Rn Rn is used as a pointer to the operand 11 Indirect autoincrement Rn Rn is used as a pointer to the operand Rn is incremented afterwards by 1 for B instructions by 2 for W instructions and by 4 for A instr...

Page 130: ...stination register Rdst The bits Rdst 19 16 are cleared The register Rsrc is not modified Address Word operation Address word operation reads the 20 bits of the source register Rsrc and writes the result to the 20 bits of the destination register Rdst The register Rsrc is not modified SXT Exception The SXT instruction is the only exception for register operation The sign of the low byte in bit 7 i...

Page 131: ... The extension word contains the A L bit for 20 bit data The instruction word uses byte mode with bits A L B W 01 The result of the instruction is xxxxh Address Space D546h PC 21036h 21034h AA550h 11111h R5 R6 Register Before Address Space PC AA550h BB551h R5 R6 Register After AA550h or 11111h BB551h 1800h 21032h xxxxh D546h 21036h 21034h 1800h 21032h ...

Page 132: ...ot overflow or underflow out of the lower 64 KB memory space The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4 15 Figure 4 15 Indexed Mode in Lower 64 KB 16 bit signed index CPU Register Rn 16 bit signed add 0 Memory address ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ FFFFF 00000 Lower 64KB 0FFFF 10000 Rn 19 0 Lower 64...

Page 133: ... R5 1000h results in address 0479Ch 1000h 0579Ch after truncation to a 16 bit address Destination The byte pointed to by R6 F000h results in address 01778h F000h 00778h after truncation to a 16 bit address xxxxh Address Space F000h 1000h PC 1103Ah 11038h 11036h 0479Ch 01778h R5 R6 01778h F000h 00778h Register Before Address Space Register After 55D6h 11034h xxxxh F000h 1000h PC 1103Ah 11038h 11036...

Page 134: ...overflow or underflow into the lower 64 KB memory space See Figure 4 16 and Figure 4 17 Figure 4 16 Indexed Mode in Upper Memory 16 bit signed index sign extended to 20 bits CPU Register Rn 20 bit signed add Memory address FFFFF 00000 Lower 64 KB 0FFFF 10000 Upper Memory Rn 19 16 0 16 bit byte index 1 15 19 16 15 0 S Rn 32 KB S Rn 19 0 Figure 4 17 Overflow and Underflow for the Indexed Mode ÇÇÇÇÇÇ...

Page 135: ...nd places the 16 bit result into the destination Source and destination operand can be located in the entire address range Source The word pointed to by R5 8346h The negative index 8346h is sign extended which results in address 23456h F8346h 1B79Ch Destination The word pointed to by R6 2100h results in address 15678h 2100h 17778h Figure 4 18 Example for the Indexed Mode xxxxh Address Space 2100h ...

Page 136: ...e extension word the 16 LSBs are contained in the word following the instruction The CPU register is not modified Comment Valid for source and destination The assembler calculates the register index and inserts it Example ADDX A 12346h R5 32100h R6 This instruction adds the 20 bit data contained in the source and the destination addresses and places the result into the destination Source Two words...

Page 137: ...bits A L B W 01 2100h Address Space 2346h 55D6h PC 21038h 21036h 21034h 23456h 45678h R5 R6 45678h 32100h 77778h Register Before Address Space Register After PC 23456h 45678h R5 R6 0001h 2345h 7777Ah 77778h 0007h 7777h 7777Ah 77778h 65432h 12345h 77777h src dst Sum 0006h 5432h 3579Eh 3579Ch 0006h 5432h 3579Eh 3579Ch 1883h 21032h xxxxh 2103Ah 2100h 2346h 55D6h 21038h 21036h 21034h 1883h 21032h xxxx...

Page 138: ...rflow out of the lower 64 KB memory space The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4 15 Figure 4 19 Symbolic Mode Running in Lower 64 KB 16 bit signed PC index Program counter PC 16 bit signed add 0 Memory address ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ FFFFF 00000 Lower 64 KB 0FFFF 10000 PC 19 0 Lower 64 KB...

Page 139: ...6h 04766h Address 01036h is the location of the index for this example Destination Byte TONI located at address 00778h pointed to by PC F740h is the truncated 16 bit result of 00778h 1038h FF740h Address 01038h is the location of the index for this example xxxxh Address Space F740h 4766h PC 0103Ah 01038h 01036h 01038h 0F740h 00778h Before Address Space After 05D0h 01034h xxxxh F740h 4766h PC 0103A...

Page 140: ...low into the lower 64 KB memory space as shown in Figure 4 20 and Figure 4 21 Figure 4 20 Symbolic Mode Running in Upper Memory 16 bit signed PC index sign extended to 20 bits Program counter PC 20 bit signed add Memory address FFFFF 00000 Lower 64 KB 0FFFF 10000 PC 19 0 Upper Memory PC 19 16 0 16 bit byte index 1 15 19 16 15 0 S PC 32 KB S Figure 4 21 Overflow and Underflow for the Symbolic Mode ...

Page 141: ... destination word TONI and places the 16 bit result into the destination word TONI For this example the instruction is located at address 2 F034h Source Word EDE at address 3379Ch pointed to by PC 4766h which is the 16 bit result of 3379Ch 2F036h 04766h Address 2F036h is the location of the index for this example Destination Word TONI located at address 00778h pointed to by the absolute address 00...

Page 142: ...ned in source byte EDE and destination byte TONI and places the result into the destination byte TONI Source Byte EDE located at address 3579Ch pointed to by PC 14766h is the 20 bit result of 3579Ch 21036h 14766h Address 21036h is the address of the index in this example Destination Byte TONI located at address 77778h pointed to by PC 56740h is the 20 bit result of 77778h 21038h 56740h Address 210...

Page 143: ... Absolute Mode The Absolute mode uses the contents of the word following the instruction as the address of the operand The Absolute mode has two addressing possibilities Absolute mode in lower 64 KB memory MSP430X instruction with Absolute mode ...

Page 144: ...e words Operation The operand is the content of the addressed memory location Comment Valid for source and destination The assembler calculates the index from 0 and inserts it Example ADD W EDE TONI This instruction adds the 16 bit data contained in the absolute source and destination addresses and places the result into the destination Source Word at address EDE Destination Word at address TONI x...

Page 145: ...dressed memory location Comment Valid for source and destination The assembler calculates the index from 0 and inserts it Example ADDX A EDE TONI This instruction adds the 20 bit data contained in the absolute source and destination addresses and places the result into the destination Source Two words beginning with address EDE Destination Two words beginning with address TONI 7778h Address Space ...

Page 146: ...X W R5 2100h R6 This instruction adds the two 16 bit operands contained in the source and the destination addresses and places the result into the destination Source Word pointed to by R5 R5 contains address 3 579Ch for this example Destination Word pointed to by R6 2100h which results in address 45678h 2100h 7778h xxxxh Address Space 2100h 55A6h PC 21038h 21036h 21034h 3579Ch 45678h R5 R6 45678h ...

Page 147: ...peration The operand is the content of the addressed memory location Comment Valid only for the source operand Example ADD B R5 0 R6 This instruction adds the 8 bit data contained in the source and the destination addresses and places the result into the destination Source Byte pointed to by R5 R5 contains address 3 579Ch for this example Destination Byte pointed to by R6 0h which results in addre...

Page 148: ...P430 instruction is used with Immediate addressing mode the constant is an 8 or 16 bit value and is stored in the word following the instruction Length Two or three words One word less if a constant of the constant generator can be used for the immediate operand Operation The 16 bit immediate source operand is used together with the 16 bit destination operand Comment Valid only for the source oper...

Page 149: ... operand Operation The 20 bit immediate source operand is used together with the 20 bit destination operand Comment Valid only for the source operand Example ADDX A 23456h TONI This instruction adds the 20 bit immediate operand 23456h to the data in the destination address TONI Source 20 bit immediate value 23456h Destination Two words beginning with address TONI 7778h Address Space 3456h 50F2h PC...

Page 150: ...is can be done if a few simple rules are met J Placement of all constants variables arrays tables and data in the lower 64 KB This allows the use of MSP430 instructions with 16 bit addressing for all data accesses No pointers with 20 bit addresses are needed J Placement of subroutine constants immediately after the subroutine code This allows the use of the symbolic addressing mode with its 16 bit...

Page 151: ...ic Absolute and Immediate modes Table 4 4 lists the twelve MSP430 double operand instructions Figure 4 22 MSP430 Double Operand Instruction Format 15 12 11 8 7 6 5 4 0 Op code Rsrc Ad B W As Rdst Source or Destination 15 0 Destination 15 0 Table 4 4 MSP430 Double Operand Instructions Mnemonic S Reg Operation Status Bits g D Reg V N Z C MOV B src dst src dst ADD B src dst src dst dst ADDC B src dst...

Page 152: ... Operand Instructions 15 7 6 5 4 0 Op code B W Ad Rdst Destination 15 0 Table 4 5 MSP430 Single Operand Instructions Mnemonic S Reg D Reg Operation Status Bits D Reg V N Z C RRC B dst C MSB LSB C RRA B dst MSB MSB LSB C 0 PUSH B src SP 2 SP src SP SWPB dst bit 15 bit 8 bit 7 bit 0 CALL dst Call subroutine in lower 64 KB RETI TOS SR SP 2 SP TOS PC SP 2 SP SXT dst Register mode bit 7 bit 8 bit 19 Ot...

Page 153: ...ffect the status bits Table 4 6 lists and describes the eight jump instructions Figure 4 24 Format of the Conditional Jump Instructions 15 Op Code 13 12 10 9 8 0 Condition S 10 Bit Signed PC Offset Table 4 6 Conditional Jump Instructions Mnemonic S Reg D Reg Operation JEQ JZ Label Jump to label if zero bit is set JNE JNZ Label Jump to label if zero bit is reset JC Label Jump to label if carry bit ...

Page 154: ...0 dst CLRC Clear Carry bit BIC 1 SR 0 CLRN Clear Negative bit BIC 4 SR 0 CLRZ Clear Zero bit BIC 2 SR 0 DADC B dst Add Carry to dst decimally DADD B 0 dst DEC B dst Decrement dst by 1 SUB B 1 dst DECD B dst Decrement dst by 2 SUB B 2 dst DINT Disable interrupt BIC 8 SR EINT Enable interrupt BIS 8 SR INC B dst Increment dst by 1 ADD B 1 dst INCD B dst Increment dst by 2 ADD B 2 dst INV B dst Invert...

Page 155: ...ction Cycles and Length for Interrupt Reset and Subroutines Table 4 8 lists the length and the CPU cycles for reset interrupts and subroutines Table 4 8 Interrupt Return and Reset Cycles and Length Action Execution Time MCLK Cycles Length of Instruction Words Return from interrupt RETI 3 1 Return from subroutine RET 3 1 Interrupt request service cycles needed before 1st instruction 5 WDT reset 4 R...

Page 156: ...Example Addressing Mode RRA RRC SWPB SXT PUSH CALL Length of Instruction Example Rn 1 3 3 1 SWPB R5 Rn 3 3 4 1 RRC R9 Rn 3 3 4 1 SWPB R10 N n a 3 4 2 CALL LABEL X Rn 4 4 4 2 CALL 2 R7 EDE 4 4 4 2 PUSH EDE EDE 4 4 4 2 SXT EDE The cycle count in MSP430 CPU is 4 The cycle count in MSP430 CPU is 5 Also the cycle count is 5 for X Rn addressing mode when Rn SP Jump Instructions Cycles and Lengths All ju...

Page 157: ... 2 1 AND R4 R5 PC 3 1 BR R8 x Rm 5 2 XOR R5 8 R6 EDE 5 2 MOV R5 EDE EDE 5 2 XOR R5 EDE Rn Rm 2 1 ADD R5 R6 PC 3 1 BR R9 x Rm 5 2 XOR R5 8 R6 EDE 5 2 MOV R9 EDE EDE 5 2 MOV R9 EDE N Rm 2 2 MOV 20 R9 PC 3 2 BR 2AEh x Rm 5 3 MOV 0300h 0 SP EDE 5 3 ADD 33 EDE EDE 5 3 ADD 33 EDE x Rn Rm 3 2 MOV 2 R5 R7 PC 3 2 BR 2 R6 TONI 6 3 MOV 4 R7 TONI x Rm 6 3 ADD 4 R4 6 R9 TONI 6 3 MOV 2 R4 TONI EDE Rm 3 2 AND ED...

Page 158: ... word of op code called the extension word Some extended instructions do not require an additional word and are noted in the instruction description All addresses indexes and immediate numbers have 20 bit values when preceded by the extension word There are two types of extension word Register register mode for Format I instructions and register mode for Format II instructions Extension word for a...

Page 159: ...struction uses the carry bit as 0 The carry bit will be defined by the result of the final operation after instruction execu tion Repetition bit 0 The number of instruction repetitions is set by extension word bits 3 0 1 The number of instructions repetitions is defined by the value of the four LSBs of Rn See description for bits 3 0 A L Data length extension bit Together with the B W bits of the ...

Page 160: ...ur MSBs of the 20 bit source Depending on the source addressing mode these four MSBs may belong to an immedi ate operand an index or to an absolute address A L Data length extension bit Together with the B W bits of the fol lowing MSP430 instruction the AL bit defines the used data length of the instruction A L B W Comment 0 0 Reserved 0 1 20 bit address word 1 0 16 bit word 1 1 8 bit byte 5 4 Res...

Page 161: ...se Carry 1 Repetition count in bits 3 0 01 Address word Destination register mode Source register mode Destination R8 Figure 4 28 Example for an Extended Immediate Indexed Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 Source 19 16 A L Rsvd Destination 19 16 Op code Rsrc Ad B W As Rdst XORX A 12345h 45678h R15 0 0 0 1 1 1 0 0 4 14 XOR 0 PC 1 1 3 15 R15 18xx extension word 12345h PC X ...

Page 162: ...c dst src dst ADDX B A src dst src dst dst ADDCX B A src dst src dst C dst SUBX B A src dst dst not src 1 dst SUBCX B A src dst dst not src C dst CMPX B A src dst dst src DADDX B A src dst src dst C dst decimal BITX B A src dst src and dst 0 Z BICX B A src dst not src and dst dst BISX B A src dst src or dst dst XORX B A src dst src xor dst dst Z ANDX B A src dst src and dst dst 0 Z The status bit ...

Page 163: ... 0 0 0 1 1 A L Op code B W dst src 15 0 src 19 16 0 0 src Ad As 0 0 0 1 1 A L Op code B W dst dst 15 0 0 0 src Ad 0 0 0 1 1 A L dst 19 16 Op code B W dst src 15 0 0 0 src Ad 0 0 0 0 dst 19 16 0 0 0 0 As src 19 16 As dst 15 0 If the 20 bit address of a source or destination operand is located in memory not in a CPU register then two words are used for this operand as shown in Figure 4 30 Figure 4 3...

Page 164: ...PUSHM W n Rsrc Push n 16 bit registers to stack 1 16 PUSHX B A src Push 8 16 20 bit source to stack RRCM A n Rdst Rotate right Rdst n bits through carry 16 20 bit register 1 4 0 RRUM A n Rdst Rotate right Rdst n bits unsigned 16 20 bit register 1 4 0 RRAM A n Rdst Rotate right Rdst n bits arithmetically 16 20 bit register 1 4 RLAM A n Rdst Rotate left Rdst n bits arithmetically 16 20 bit register ...

Page 165: ... 1 0 A L n 1 Rn Op code B W dst 0 ZC 0 0 0 0 0 1 1 A L Op code B W dst 0 0 0 0 0 1 1 A L Op code B W dst dst 15 0 0 0 0 0 0 0 dst 19 16 0 0 0 0 0 0 0 0 0 0 1 x x 1 Extended Format II Instruction Format Exceptions Exceptions for the Format II instruction formats are shown below Figure 4 32 PUSHM POPM Instruction Format 15 8 7 4 3 0 Op code n 1 Rdst n 1 Figure 4 33 RRCM RRAM RRUM and RLAM Instructio...

Page 166: ...BRA Instruction Format 15 12 11 8 7 4 3 0 C Rsrc Op code 0 PC C imm abs19 16 Op code 0 PC C Rsrc Op code 0 PC imm15 0 abs15 0 index15 0 Figure 4 35 CALLA Instruction Format 15 4 3 0 Op code Rdst Op code Rdst Op code imm ix abs19 16 index15 0 imm15 0 index15 0 abs15 0 ...

Page 167: ...A 0 dst DADCX B A dst Add carry to dst decimally DADDX B A 0 dst DECX B A dst Decrement dst by 1 SUBX B A 1 dst DECDA Rdst Decrement dst by 2 SUBA 2 Rdst DECDX B A dst Decrement dst by 2 SUBX B A 2 dst INCX B A dst Increment dst by 1 ADDX B A 1 dst INCDA Rdst Increment Rdst by 2 ADDA 2 Rdst INCDX B A dst Increment dst by 2 ADDX B A 2 dst INVX B A dst Invert dst XORX B A 1 dst RLAX B A dst Shift le...

Page 168: ...p code improving code density and execution time Address instructions should be used any time an MSP430X instruction is needed with the corresponding restricted addressing mode Table 4 16 Address Instructions Operate on 20 bit Registers Data Status Bits Mnemonic Operands Operation V N Z C ADDA Rsrc Rdst imm20 Rdst Add source to destination register MOVA Rsrc Rdst imm20 Rdst z16 Rsrc Rdst EDE Rdst ...

Page 169: ...ormat II Instruction Cycles and Length Execution Cycles Length of Instruction Words Instruction Rn Rn Rn N X Rn EDE EDE RRAM n 1 RRCM n 1 RRUM n 1 RLAM n 1 PUSHM 2 n 1 PUSHM A 2 2n 1 POPM 2 n 1 POPM A 2 2n 1 CALLA 4 1 5 1 5 1 4 2 6 2 6 2 6 2 RRAX B 1 n 2 4 2 4 2 5 3 5 3 5 3 RRAX A 1 n 2 6 2 6 2 7 3 7 3 7 3 RRCX B 1 n 2 4 2 4 2 5 3 5 3 5 3 RRCX A 1 n 2 6 2 6 2 7 3 7 3 7 3 PUSHX B 4 2 4 2 4 2 4 3 5 ...

Page 170: ... PC 4 4 3 ADDX A FE000h PC X Rm 6 8 4 ANDX 1234 4 R6 EDE 6 8 4 XORX A5A5h EDE EDE 6 8 4 BITX B 12 EDE X Rn Rm 4 5 3 BITX 2 R5 R8 PC 5 6 3 SUBX A 2 R6 PC X Rm 7 10 4 ANDX 4 R7 4 R6 EDE 7 10 4 XORX B 2 R6 EDE EDE 7 10 4 BITX 8 SP EDE EDE Rm 4 5 3 BITX B EDE R8 PC 5 6 3 ADDX A EDE PC X Rm 7 10 4 ANDX EDE 4 R6 EDE 7 10 4 ANDX EDE TONI TONI 7 10 4 BITX EDE TONI EDE Rm 4 5 3 BITX EDE R8 PC 5 6 3 ADDX A ...

Page 171: ...n Time MCLK Cycles Length of Instruction Words Source Destination MOVA BRA CMPA ADDA SUBA MOVA CMPA ADDA SUBA Example Rn Rn 1 1 1 1 CMPA R5 R8 PC 2 2 1 1 SUBA R9 PC x Rm 4 2 MOVA R5 4 R6 EDE 4 2 MOVA R8 EDE EDE 4 2 MOVA R5 EDE Rn Rm 3 1 MOVA R5 R8 PC 3 1 MOVA R9 PC Rn Rm 3 1 MOVA R5 R8 PC 3 1 MOVA R9 PC N Rm 2 3 2 2 CMPA 20 R8 PC 3 3 2 2 SUBA FE000h PC x Rn Rm 4 2 MOVA 2 R5 R8 PC 4 2 MOVA 2 R6 PC ...

Page 172: ... 9xxx Axxx Bxxx Cxxx Dxxx Exxx Fxxx RRC RRC B SWPB RRA RRA B SXT PUSH PUSH B CALL RETI 000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0 JNE JNZ JEQ JZ JNC JC JN JGE JL JMP MOV MOV B ADD ADD B ADDC ADDC B SUBC SUBC B SUB SUB B CMP CMP B DADD DADD B BIT BIT B BIC BIC B BIS BIS B XOR XOR B AND AND B MOVA CMPA ADDA SUBA RRCM RRAM RLAM RRUM CALLA PUSHM A POPM A PUSHM W POPM W Extension W...

Page 173: ...0 0 0 0 imm 19 16 1 0 0 1 dst CMPA imm20 Rdst imm 15 0 ADDA 0 0 0 0 imm 19 16 1 0 1 0 dst ADDA imm20 Rdst imm 15 0 SUBA 0 0 0 0 imm 19 16 1 0 1 1 dst SUBA imm20 Rdst imm 15 0 MOVA 0 0 0 0 src 1 1 0 0 dst MOVA Rsrc Rdst CMPA 0 0 0 0 src 1 1 0 1 dst CMPA Rsrc Rdst ADDA 0 0 0 0 src 1 1 1 0 dst ADDA Rsrc Rdst SUBA 0 0 0 0 src 1 1 1 1 dst SUBA Rsrc Rdst Instruction Group Bit loc Inst ID Instruction Ide...

Page 174: ... 0 0 0 1 0 0 1 1 0 1 1 1 dst CALLA Rdst 0 0 0 1 0 0 1 1 1 0 0 0 abs 19 16 CALLA abs20 abs 15 0 0 0 0 1 0 0 1 1 1 0 0 1 x 19 16 CALLA EDE x 15 0 CALLA x PC 0 0 0 1 0 0 1 1 1 0 1 1 imm 19 16 CALLA imm20 imm 15 0 Reserved 0 0 0 1 0 0 1 1 1 0 1 0 x x x x Reserved 0 0 0 1 0 0 1 1 1 1 x x x x x x PUSHM A 0 0 0 1 0 1 0 0 n 1 dst PUSHM A n Rdst PUSHM W 0 0 0 1 0 1 0 1 n 1 dst PUSHM W n Rdst POPM A 0 0 0 1...

Page 175: ...MSP430 Instructions 4 61 16 Bit MSP430X CPU 4 6 2 MSP430 Instructions The MSP430 instructions are listed and described on the following pages ...

Page 176: ...positive Z Set if result is zero reset otherwise C Set if dst was incremented from 0FFFFh to 0000 reset otherwise Set if dst was incremented from 0FFh to 00 reset otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed to by R12 ADD R13 0 R12 Add LSDs ADC 2 R1...

Page 177: ...f two positive operands is negative or if the result of two negative numbers is positive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Ten is added to the 16 bit counter CNTR located in lower 64 K ADD W 10 CNTR Add 10 to 16 bit counter Example A table word pointed to by R5 20 bit address in R5 is added to R6 The jump to label TONI is performed on a carry ADD W R5 R6 Add ...

Page 178: ...s is negative or if the result of two negative numbers is positive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Constant value 15 and the carry of the previous instruction are added to the 16 bit counter CNTR located in lower 64 K ADDC W 15 CNTR Add 15 C to 16 bit CNTR Example A table word pointed to by R5 20 bit address and the carry C are added to R6 The jump to label...

Page 179: ...f result is zero reset otherwise C Set if the result is not zero reset otherwise C not Z V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits set in R5 16 bit data are used as a mask AA55h for the word TOM located in the lower 64 K If the result is zero a branch is taken to label TONI R5 19 16 0 MOV AA55h R5 Load 16 bit mask to R5 AND R5 TOM TOM and R5 TOM JZ TONI Jump if resu...

Page 180: ...aced into the destination The source operand is not affected Status Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits 15 14 of R5 16 bit data are cleared R5 19 16 0 BIC 0C000h R5 Clear R5 19 14 bits Example A table word pointed to by R5 20 bit address is used to clear bits in R7 R7 19 16 0 BIC W R5 R7 Clear bits in R7...

Page 181: ...e destination The source operand is not affected Status Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Bits 15 and 13 of R5 16 bit data are set to one R5 19 16 0 BIS A000h R5 Set R5 bits Example A table word pointed to by R5 20 bit address is used to set bits in R7 R7 19 16 0 BIS W R5 R7 Set bits in R7 Example A table byte ...

Page 182: ...ise C not Z V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example Test if one or both of bits 15 and 14 of R5 16 bit data is set Jump to label TONI if this is the case R5 19 16 are not affected BIT C000h R5 Test R5 15 14 bits JNZ TONI At least one bit is set in R5 Both bits are reset Example A table word pointed to by R5 20 bit address is used to test bits in R7 Jump to label TONI if at...

Page 183: ...ess BR EXEC Branch to the address contained in absolute address EXEC Core instruction MOV X 0 PC Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC Indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer...

Page 184: ...ffected Examples Examples for all addressing modes are given Immediate Mode Call a subroutine at label EXEC lower 64 K or call directly to address CALL EXEC Start address EXEC CALL 0AA04h Start address 0AA04h Symbolic Mode Call a subroutine at the 16 bit address contained in address EXEC EXEC is located at the address PC X where X is within PC 32 K CALL EXEC Start address at EXEC z16 PC Absolute M...

Page 185: ...R dst or CLR W dst CLR B dst Operation 0 dst Emulation MOV 0 dst MOV B 0 dst Description The destination operand is cleared Status Bits Status bits are not affected Example RAM word TONI is cleared CLR TONI 0 TONI Example Register R5 is cleared CLR R5 Example RAM byte TONI is cleared CLR B TONI 0 TONI ...

Page 186: ... is a word instruction Status Bits N Not affected Z Not affected C Cleared V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit decimal counter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C 0 defines start DADD R13 0 R12 add 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter ...

Page 187: ...The result is placed into the destination The clear negative bit instruction is a word instruction Status Bits N Reset to 0 Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The Negative bit in the status register is cleared This avoids special treatment with negative numbers of the subroutine called CLRN CALL SUBR SUBR JN SUBRET If input is nega...

Page 188: ...t in the status register is cleared CLRZ Indirect Auto Increment mode Call a subroutine at the 16 bit address con tained in the word pointed to by register R5 20 bit address and increment the 16 bit address in R5 afterwards by 2 The next time the software uses R5 as a pointer it can alter the program execution due to access to the next word ad dress in the table pointed to by R5 CALL R5 Start addr...

Page 189: ... delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example Compare word EDE with a 16 bit constant 1800h Jump to label TONI if EDE equals the constant The address of EDE is within PC 32 K CMP 01800h EDE Compare word EDE with 1800h ...

Page 190: ... 9999 to 0000 reset otherwise Set if destination increments from 99 to 00 reset otherwise V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example The four digit decimal number contained in R5 is added to an eight digit deci mal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD R5 0 R8 Add LSDs C DADC 2 R8 Add carry to MSD Example The two digit...

Page 191: ... Set if result is zero reset otherwise C Set if the BCD result is too large word 9999h byte 99h reset otherwise V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example Decimal 10 is added to the 16 bit BCD counter DECCNTR DADD 10h DECCNTR Add 10 to 4 digit BCD counter Example The eight digit BCD number contained in 16 bit RAM addresses BCD and BCD 2 is added decimally to an eight digi...

Page 192: ...ccurs otherwise reset Set if initial value of destination was 08000h otherwise reset Set if initial value of destination was 080h otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination a...

Page 193: ...low occurs otherwise reset Set if initial value of destination was 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 words from memory location starting with EDE to memory location starting with TONI Tables should not o...

Page 194: ...fected Example The general interrupt enable GIE bit in the status register is cleared to allow a nondisrupted move of a 32 bit counter This ensures that the counter is not modified during the move by any interrupt DINT All interrupt events using the GIE bit are disabled NOP MOV COUNTHI R5 Copy counter MOV COUNTLO R6 EINT All interrupt events using the GIE bit are enabled Note Disable Interrupt If ...

Page 195: ...of ports P1 2 to P1 7 P1IN is the address of the register where all port bits are read P1IFG is the address of the register where all interrupt events are latched PUSH B P1IN BIC B SP P1IFG Reset only accepted flags EINT Preset port 1 interrupt flags stored on stack other interrupts are allowed BIT Mask SP JEQ MaskOK Flags are present identically to mask jump MaskOK BIC Mask SP INCD SP Housekeepin...

Page 196: ...ult is negative reset if positive Z Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise C Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise V Set if dst contained 07FFFh reset otherwise Set if dst contained 07Fh reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The status byte STATUS of a process is increm...

Page 197: ...t otherwise C Set if dst contained 0FFFEh or 0FFFFh reset otherwise Set if dst contained 0FEh or 0FFh reset otherwise V Set if dst contained 07FFEh or 07FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation whic...

Page 198: ...reset otherwise Set if dst contained 0FFh reset otherwise C Set if result is not zero reset otherwise NOT Zero Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example Content of R5 is negated twos complement MOV 00AEh R5 R5 000AEh INV R5 Invert R5 R5 0FF51h INC R5 R5 is now negated...

Page 199: ...y range If C is reset the instruction after the jump is executed JC is used for the test of the carry bit C JHS is used for the comparison of unsigned numbers Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The state of the port 1 pin P1IN 1 bit defines the program flow BIT B 2 P1IN Port 1 bit 1 set Bit C JC Label1 Yes proceed at Label1 No continue...

Page 200: ...t the instruction after the jump is executed JZ is used for the test of the Zero bit Z JEQ is used for the comparison of operands Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The state of the P2IN 0 bit defines the program flow BIT B 1 P2IN Port 2 bit 0 reset JZ Label1 Yes proceed at Label1 No set continue Example If R5 15000h 20 bit data the pr...

Page 201: ...e decision made by the JGE instruction is correct Note JGE emulates the non implemented JP jump if positive instruction if used after the instructions AND BIT RRA SXTX and TST These instructions clear the V bit Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example If byte EDE lower 64 K contains positive data go to Label1 Software can run in the full mem...

Page 202: ... comparison of signed operands also for incorrect results due to overflow the decision made by the JL instruction is correct Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example If byte EDE contains a smaller signed operand than byte TONI continue at Label1 The address EDE is within PC 32 K CMP B TONI EDE Is EDE TONI JL Label1 Yes No TONI EDE Example If...

Page 203: ...to the program counter Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The byte STATUS is set to 10 Then a jump to label MAINLOOP is made Data in lower 64 K program in full memory range MOV B 10 STATUS Set STATUS to 10 JMP MAINLOOP Go to main loop Example The interrupt vector TAIV of Timer_A3 is read and used for the program flow Program in full me...

Page 204: ...s executed Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The byte COUNT is tested If it is negative program execution continues at Label0 Data in lower 64 K program in full memory range TST B COUNT Is byte COUNT negative JN Label0 Yes proceed at Label0 COUNT 0 Example R6 is subtracted from R5 If the result is negative program continues at Label2 ...

Page 205: ...e to the PC in the full memory range If C is set the instruction after the jump is executed JNC is used for the test of the carry bit C JLO is used for the comparison of unsigned numbers Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example If byte EDE 15 the program continues at Label2 Unsigned data Data in lower 64 K program in full memory range CMP B ...

Page 206: ...the test of the Zero bit Z JNE is used for the comparison of operands Status Bits Status bits are not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The byte STATUS is tested If it is not zero the program continues at Label3 The address of STATUS is within PC 32 K TST B STATUS Is STATUS 0 JNZ Label3 No proceed at Label3 Yes continue here Example If word EDE 1500 the program cont...

Page 207: ...to EDE Example The contents of table EDE word data 16 bit addresses are copied to table TOM The length of the tables is 030h words Both tables reside in the lower 64K MOV EDE R10 Prepare pointer 16 bit address Loop MOV R10 TOM EDE 2 R10 R10 points to both tables R10 2 CMP EDE 60h R10 End of table reached JLO Loop Not yet Copy completed Example The contents of table EDE byte data 16 bit addresses a...

Page 208: ...operation Syntax NOP Operation None Emulation MOV 0 R3 Description No operation is performed The instruction may be used for the elimination of instructions during the software check or for defined waiting times Status Bits Status bits are not affected ...

Page 209: ...R7 POP SR Restore status register Example The contents of RAM byte LEO is restored from the stack POP B LEO The low byte of the stack is moved to LEO Example The contents of R7 is restored from the stack POP B R7 The low byte of the stack is moved to R7 the high byte of R7 is 00h Example The contents of the memory pointed to by R7 and the status register are restored from the stack POP B 0 R7 The ...

Page 210: ... then copied to the RAM word addressed by the SP A pushed byte is stored in the low byte the high byte is not affected Status Bits Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Save the two 16 bit registers R9 and R10 on the stack PUSH R9 Save R9 and R10 XXXXh PUSH R10 YYYYh Example Save the two bytes EDE and TONI on the stack The addresses EDE and TONI are within PC 32 K P...

Page 211: ...Bs of the program counter PC 19 16 are cleared Status Bits Not affected PC 19 16 Cleared Mode Bits OSCOFF CPUOFF and GIE are not affected Example Call a subroutine SUBR in the lower 64 K and return to the address in the lower 64K after the CALL CALL SUBR Call subroutine starting at SUBR Return by RET to here SUBR PUSH R14 Save R14 16 bit data Subroutine code POP R14 Restore R14 RET Return to lower...

Page 212: ...ion as the status bits and PC 15 0 The 20 bit program counter is restored to the value at the beginning of the interrupt service routine The program continues at the address following the last executed instruction when the interrupt was granted The stack pointer is incremented by two afterwards Status Bits N restored from stack Z restored from stack C restored from stack V restored from stack Mode...

Page 213: ... Byte Word 0 An overflow occurs if dst 040h and dst 0C0h before the operation is performed the result has changed sign Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 04000h dst 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h dst ...

Page 214: ...zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 04000h dst 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h dst 0C0h reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is shifted left one position RLC R5 R5 x 2 C R5 Example The input P1IN 1 information is shifted into the LSB of R5 ...

Page 215: ...d and shifted into the MSB 1 The LSB 1 is shifted into the LSB The previous LSB is shifted into the carry bit C Status Bits N Set if result is negative MSB 1 reset otherwise MSB 0 Z Set if result is zero reset otherwise C Loaded from the LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The signed 16 bit number in R5 is shifted arithmetically right one position RRA R5 R5 2 R5 Ex...

Page 216: ...arry bit C is shifted into the MSB and the LSB is shifted into the carry bit C Status Bits N Set if result is negative MSB 1 reset otherwise MSB 0 Z Set if result is zero reset otherwise C Loaded from the LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example RAM word EDE is shifted right one bit position The MSB is loaded with 1 SETC Prepare carry for MSB RRC EDE EDE EDE 1 8000h Fig...

Page 217: ...Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 16 bit counter pointed to by R13 is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 Subtract LSDs SBC 2 R12 Subtract carry...

Page 218: ...affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Emulation of the decimal subtraction Subtract R5 from R6 decimally Assume that R5 03987h and R6 04137h DSUB ADD 06666h R5 Move content R5 from 0 9 to 6 0Fh R5 03987h 06666h 09FEDh INV R5 Invert this result back to 0 9 R5 NOT R5 06012h SETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 010000h R5 1 R6 R6 R5 1 R6 0150h...

Page 219: ...it MSP430X CPU SETN Set negative bit Syntax SETN Operation 1 N Emulation BIS 4 SR Description The negative bit N is set Status Bits N Set Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected ...

Page 220: ...16 Bit MSP430X CPU SETZ Set zero bit Syntax SETZ Operation 1 Z Emulation BIS 2 SR Description The zero bit Z is set Status Bits N Not affected Z Set C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected ...

Page 221: ...et if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example A 16 bit constant 7654h is subtracted from RAM word EDE SUB 7654h EDE Subtract 7654h ...

Page 222: ...ative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example A 16 bit constant 7654h is subtracted from R5 with the carry from the previous instruction R5 19 16 0 SUBC W 7654h ...

Page 223: ...Status Bits Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Exchange the bytes of RAM word EDE lower 64 K MOV 1234h EDE 1234h EDE SWPB EDE 3412h EDE Figure 4 42 Swap Bytes in Memory 15 8 7 0 15 8 7 0 Low Byte Low Byte High Byte High Byte Before SWPB After SWPB Figure 4 43 Swap Bytes in a Register 15 8 7 0 15 8 7 0 Low Byte Low Byte High Byte High Byte Before SWPB After SWPB 0...

Page 224: ...h byte FFh afterwards Status Bits N Set if result is negative reset otherwise Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise C not Z V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The signed 8 bit data in EDE lower 64 K is sign extended and added to the 16 bit signed data in R7 MOV B EDE R5 EDE R5 00XXh SXT R5 Sign extend low byte to R5 19 8 A...

Page 225: ...otherwise C Set V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS R7 is positive but not zero R7NEG R7 is negative R7ZERO R7 is zero Example The low byte of R7 is tested If it is negative continue at R7NEG if it is positi...

Page 226: ...eset otherwise C Set if result is not zero reset otherwise C not Z V Set if both operands are negative before execution reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Toggle bits in word CNTR 16 bit data with information bit 1 in address word TONI Both operands are located in lower 64 K XOR TONI CNTR Toggle bits in CNTR Example A table word pointed to by R5 20 bit address...

Page 227: ...e MSP430X instructions require an additional word of op code called the extension word All addresses indexes and immediate numbers have 20 bit values when preceded by the extension word The MSP430X extended instructions are listed and described in the following pages For MSP430X instructions that do not require the extension word it is noted in the instruction description ...

Page 228: ...rand The previous contents of the destination are lost Status Bits N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise V Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not ...

Page 229: ...t of two positive operands is negative or if the result of two negative numbers is positive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Ten is added to the 20 bit pointer CNTR located in two words CNTR LSBs and CNTR 2 MSBs ADDX A 10 CNTR Add 10 to 20 bit pointer Example A table word 16 bit pointed to by R5 20 bit address is added to R6 The jump to label TONI is perform...

Page 230: ...y from the MSB of the result reset otherwise V Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Constant 15 and the carry of the previous instruction are added to the 20 bit counter CNTR located in two words ADDCX A 15 CNTR Add 15 C to 20 bit CNTR Example A table word...

Page 231: ... Status Bits N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if the result is not zero reset otherwise C not Z V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits set in R5 20 bit data are used as a mask AAA55h for the address word TOM located in two words If the result is zero a branch is taken to label TONI MOVA AAA55h...

Page 232: ...ically ANDed The result is placed into the destination The source operand is not affected Both operands may be located in the full address space Status Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example The bits 19 15 of R5 20 bit data are cleared BICX A 0F8000h R5 Clear R5 19 15 bits Example A table word pointed to by R5 20 bi...

Page 233: ...ically ORed The result is placed into the destination The source operand is not affected Both operands may be located in the full address space Status Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Bits 16 and 15 of R5 20 bit data are set to one BISX A 018000h R5 Set R5 16 15 bits Example A table word pointed to by R5 20 bi...

Page 234: ...esult is zero reset otherwise C Set if the result is not zero reset otherwise C not Z V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example Test if bit 16 or 15 of R5 20 bit data is set Jump to label TONI if so BITX A 018000h R5 Test R5 16 15 bits JNZ TONI At least one bit is set Both are reset Example A table word pointed to by R5 20 bit address is used to test bits in R7 Jump to label...

Page 235: ...nation word CLRX B Clear destination byte Syntax CLRX A dst CLRX dst or CLRX W dst CLRX B dst Operation 0 dst Emulation MOVX A 0 dst MOVX 0 dst MOVX B 0 dst Description The destination operand is cleared Status Bits Status bits are not affected Example RAM address word TONI is cleared CLRX A TONI 0 TONI ...

Page 236: ...from a positive destination operand delivers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example Compare EDE with a 20 bit constant 18000h Jump to label TONI if EDE equals the constant CMPX A 018000h EDE Compare EDE with 18000h JEQ TON...

Page 237: ...DDX B 0 dst Description The carry bit C is added decimally to the destination Status Bits N Set if MSB of result is 1 address word 79999h word 7999h byte 79h reset if MSB is 0 Z Set if result is zero reset otherwise C Set if the BCD result is too large address word 99999h word 9999h byte 99h reset otherwise V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 40 bit counter poi...

Page 238: ...the full address space Status Bits N Set if MSB of result is 1 address word 79999h word 7999h byte 79h reset if MSB is 0 Z Set if result is zero reset otherwise C Set if the BCD result is too large address word 99999h word 9999h byte 99h reset otherwise V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Example Decimal 10 is added to the 20 bit BCD counter DECCNTR located in two words DA...

Page 239: ... A 1 dst SUBX 1 dst SUBX B 1 dst Description The destination operand is decremented by one The original contents are lost Status Bits N Set if result is negative reset if positive Z Set if dst contained 1 reset otherwise C Reset if dst contained 0 set otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example RAM address word TONI is d...

Page 240: ...tion SUBX A 2 dst SUBX 2 dst SUBX B 2 dst Description The destination operand is decremented by two The original contents are lost Status Bits N Set if result is negative reset if positive Z Set if dst contained 2 reset otherwise C Reset if dst contained 0 or 1 set otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example RAM address ...

Page 241: ... N Set if result is negative reset if positive Z Set if dst contained 0FFFFFh reset otherwise Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise C Set if dst contained 0FFFFFh reset otherwise Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise V Set if dst contained 07FFFh reset otherwise Set if dst contained 07FFFh reset otherwi...

Page 242: ...ve reset if positive Z Set if dst contained 0FFFFEh reset otherwise Set if dst contained 0FFFEh reset otherwise Set if dst contained 0FEh reset otherwise C Set if dst contained 0FFFFEh or 0FFFFFh reset otherwise Set if dst contained 0FFFEh or 0FFFFh reset otherwise Set if dst contained 0FEh or 0FFh reset otherwise V Set if dst contained 07FFFEh or 07FFFFh reset otherwise Set if dst contained 07FFE...

Page 243: ...lt is negative reset if positive Z Set if dst contained 0FFFFFh reset otherwise Set if dst contained 0FFFFh reset otherwise Set if dst contained 0FFh reset otherwise C Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example 20 bit content of R5 is negated twos complement INVX A R5 ...

Page 244: ...IE are not affected Example Move a 20 bit constant 18000h to absolute address word EDE MOVX A 018000h EDE Move 18000h to EDE Example The contents of table EDE word data 20 bit addresses are copied to table TOM The length of the table is 030h words MOVA EDE R10 Prepare pointer 20 bit address Loop MOVX W R10 TOM EDE 2 R10 R10 points to both tables R10 2 CMPA EDE 60h R10 End of table reached JLO Loop...

Page 245: ...st Immediate Reg MOVX A abs20 Rdst MOVA abs20 Rdst Absolute Reg MOVX A Rsrc Rdst MOVA Rsrc Rdst Indirect Reg MOVX A Rsrc Rdst MOVA Rsrc Rdst Indirect Auto Reg MOVX A Rsrc abs20 MOVA Rsrc abs20 Reg Absolute The next four replacements are possible only if 16 bit indexes are sufficient for the addressing MOVX A z20 Rsrc Rdst MOVA z16 Rsrc Rdst Indexed Reg MOVX A Rsrc z20 Rdst MOVA Rsrc z16 Rdst Reg I...

Page 246: ... are restored to the CPU registers Note This does not use the extension word Description POPM A The CPU registers pushed on the stack are moved to the extended CPU registers starting with the CPU register Rdst n 1 The stack pointer is incremented by n 4 after the operation POPM W The 16 bit registers pushed on the stack are moved back to the CPU registers starting with CPU register Rdst n 1 The st...

Page 247: ...ription PUSHM A The n CPU registers starting with Rdst backwards are stored on the stack The stack pointer is decremented by n 4 after the operation The data Rn 19 0 of the pushed CPU registers is not affected PUSHM W The n registers starting with Rdst backwards are stored on the stack The stack pointer is decremented by n 2 after the operation The data Rn 19 0 of the pushed CPU registers is not a...

Page 248: ...and word operands and by four address word operand Emulation MOVX B A SP dst Description The item on TOS is written to the destination operand Register Mode Indexed Mode Symbolic Mode and Absolute Mode are possible The stack pointer is incremented by two or four Note the stack pointer is incremented by two also for byte operations Status Bits Not affected Mode Bits OSCOFF CPUOFF and GIE are not af...

Page 249: ...erands or by four address word operand before the write operation Description The stack pointer is decremented by two byte and word operands or by four address word operand Then the source operand is written to the TOS All seven addressing modes are possible for the source operand Note This instruction does not use the extension word Status Bits Not affected Mode Bits OSCOFF CPUOFF and GIE are not...

Page 250: ... unsigned with 2 4 8 or 16 The word instruction RLAM W clears the bits Rdst 19 16 Note This instruction does not use the extension word Status Bits N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the MSB n 1 MSB 1 n 2 MSB 2 n 3 MSB 3 n 4 V Undefined Mode Bits OSCOFF CPUOFF and GIE are not affected Examp...

Page 251: ...lled with 0 The RLAX instruction acts as a signed multiplication by 2 Figure 4 45 Destination Operand Arithmetic Shift Left MSB 0 C 0 Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 040000h dst 0C0000h reset otherwise Set if an arithmetic overflow occurs the initial v...

Page 252: ... 46 Destination Operand Carry Left Shift MSB 0 C Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 040000h dst 0C0000h reset otherwise Set if an arithmetic overflow occurs the initial value is 04000h dst 0C000h reset otherwise Set if an arithmetic overflow occurs the in...

Page 253: ...e carry bit C The word instruction RRAM W clears the bits Rdst 19 16 Note This instruction does not use the extension word Status Bits N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LSB 3 n 4 V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The signed ...

Page 254: ...he byte instruction RRAX B clears the bits Rdst 19 8 The MSB retains its value sign the LSB is shifted into the carry bit RRAX here operates equal to a signed division by 2 All other modes for the destination the destination operand is shifted right arithmetically by one bit position as shown in Figure 4 49 The MSB retains its value sign the LSB is shifted into the carry bit RRAX here operates equ...

Page 255: ...X A R5 R5 16 R5 Example The signed 8 bit value in EDE is multiplied by 0 5 RRAX B EDE EDE 2 EDE Figure 4 48 Rotate Right Arithmetically RRAX B A Register Mode C 0 MSB 7 LSB C 15 0 MSB LSB C 19 0 MSB LSB 8 19 0 0 19 16 0000 Figure 4 49 Rotate Right Arithmetically RRAX B A Non Register Mode C 0 MSB 7 LSB C 15 0 MSB LSB C 19 0 MSB LSB 31 20 0 0 ...

Page 256: ...e This instruction does not use the extension word Status Bits N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LSB 3 n 4 V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The address word in R5 is shifted right by three positions The MSB 2 is loaded with...

Page 257: ... W clears the bits Rdst 19 16 the byte instruction RRCX B clears the bits Rdst 19 8 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit All other modes for the destination the destination operand is shifted right by one bit position as shown in Figure 4 52 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit All addressing modes with the ex ceptio...

Page 258: ... RRCX A EDE EDE EDE 1 80000h Example The word in R6 is shifted right by twelve positions RPT 12 RRCX W R6 R6 R6 12 R6 19 16 0 Figure 4 51 Rotate Right Through Carry RRCX B A Register Mode C 19 0 MSB 0 0 7 LSB C 19 0 MSB LSB 8 C 15 0 MSB LSB 19 16 0 0 0 0 Figure 4 52 Rotate Right Through Carry RRCX B A Non Register Mode C 0 MSB 7 LSB C 15 0 MSB LSB C 19 0 MSB LSB 31 20 0 0 ...

Page 259: ...ision by 2 4 8 or 16 The word instruction RRUM W clears the bits Rdst 19 16 Note This instruction does not use the extension word Status Bits N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LSB 3 n 4 V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The ...

Page 260: ...uction RRUX W clears the bits Rdst 19 16 The byte instruction RRUX B clears the bits Rdst 19 8 Zero is shifted into the MSB the LSB is shifted into the carry bit Status Bits N Set if result is negative A dst 19 1 reset if dst 19 0 W dst 15 1 reset if dst 15 0 B dst 7 1 reset if dst 7 0 Z Set if result is zero reset otherwise C Loaded from LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affecte...

Page 261: ...to the destination operand minus one The previous contents of the destination are lost Status Bits N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Exam...

Page 262: ...erwise V Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example A 20 bit constant 87654h is subtracted from EDE LSBs and EDE 2 MSBs SUBX A ...

Page 263: ... C Set if there is a carry from the MSB reset otherwise V Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example A 20 bit constant 87654h i...

Page 264: ... the destination address are cleared bits 19 16 are left unchanged and bits 15 8 are swapped with bits 7 0 When the W extension is used bits 15 8 are swapped with bits 7 0 of the addressed word Status Bits Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Exchange the bytes of RAM address word EDE MOVX A 23456h EDE 23456h EDE SWPBX A EDE 25634h EDE Example Exchange the bytes of...

Page 265: ...ter SWPBX A X 19 16 31 20 X 15 8 7 0 High Byte Low Byte 0 19 16 31 20 X Figure 4 57 Swap Bytes SWPBX W Register Mode 15 8 7 0 15 8 7 0 Low Byte Low Byte High Byte High Byte Before SWPBX After SWPBX X 0 19 19 16 16 Figure 4 58 Swap Bytes SWPBX W In Memory 15 8 7 0 15 8 7 0 Low Byte Low Byte High Byte High Byte Before SWPBX After SWPBX ...

Page 266: ...s extended into dst 19 8 The bits dst 31 20 are cleared SXTX W the sign of the low byte of the operand dst 7 is extended into dst 15 8 Status Bits N Set if result is negative reset otherwise Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise C not Z V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The signed 8 bit data in EDE 7 0 is sign extended to...

Page 267: ...Extended Instructions 4 153 16 Bit MSP430X CPU Figure 4 60 Sign Extend SXTX W 15 8 7 6 0 S 15 8 7 6 0 19 16 S 19 16 SXTX W Rdst SXTX W dst ...

Page 268: ... status bits are set according to the result The destination is not affected Status Bits N Set if destination is negative reset if positive Z Set if destination contains zero reset otherwise C Set V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example RAM byte LEO is tested PC is pointing to upper memory If it is negative continue at LEONEG if it is positive but not zero continue at LEOP...

Page 269: ...ss space Status Bits N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise carry not Zero V Set if both operands are negative before execution reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example Toggle bits in address word CNTR 20 bit data with information in address word TONI 20 bit addres...

Page 270: ...e restricted addressing modes The addressing modes are restricted to the Register mode and the Immediate mode except for the MOVA instruction Restricting the addressing modes removes the need for the additional extension word op code improving code density and execution time The MSP430X address instructions are listed and described in the following pages ...

Page 271: ...ffected Status Bits N Set if result is negative Rdst 19 1 reset if positive Rdst 19 0 Z Set if result is zero reset otherwise C Set if there is a carry from the 20 bit result reset otherwise V Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is increased by 0A4320h...

Page 272: ...les Examples for all addressing modes are given Immediate Mode Branch to label EDE located anywhere in the 20 bit address space or branch directly to address BRA EDE MOVA imm20 PC BRA 01AA04h Symbolic Mode Branch to the 20 bit address contained in addresses EXEC LSBs and EXEC 2 MSBs EXEC is located at the address PC X where X is within 32 K Indirect addressing BRA EXEC MOVA z16 PC PC Note if the 1...

Page 273: ...W flow uses R5 as a pointer it can alter the program execution due to access to the next address in the table pointed to by R5 Indi rect indirect R5 BRA R5 MOVA R5 PC R5 4 Indexed Mode Branch to the 20 bit address contained in the address pointed to by register R5 X e g a table with addresses starting at X R5 X points to the LSBs R5 X 2 points to the MSBs of the address X is within R5 32 K Indirec...

Page 274: ...is made with the instruction RETA Status Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Examples Examples for all addressing modes are given Immediate Mode Call a subroutine at label EXEC or call directly an address CALLA EXEC Start address EXEC CALLA 01AA04h Start address 01AA04h Symbolic Mode Call a subroutine at the 20 bit addre...

Page 275: ...increment the 20 bit address in R5 afterwards by 4 The next time the S W flow uses R5 as a pointer it can alter the program execution due to access to the next word address in the table pointed to by R5 Indirect indirect R5 CALLA R5 Start address at R5 R5 4 Indexed Mode Call a subroutine at the 20 bit address contained in the ad dress pointed to by register R5 X e g a table with addresses starting...

Page 276: ...PU CLRA Clear 20 bit destination register Syntax CLRA Rdst Operation 0 Rdst Emulation MOVA 0 Rdst Description The destination register is cleared Status Bits Status bits are not affected Example The 20 bit value in R10 is cleared CLRA R10 0 R10 ...

Page 277: ... dst C Set if there is a carry from the MSB reset otherwise V Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example A 20 bit immediate opera...

Page 278: ...gister is decremented by two The original contents are lost Status Bits N Set if result is negative reset if positive Z Set if Rdst contained 2 reset otherwise C Reset if Rdst contained 0 or 1 set otherwise V Set if an arithmetic overflow occurs otherwise reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 20 bit value in R5 is decremented by 2 DECDA R5 Decrement R5 by two ...

Page 279: ...e Set if Rdst contained 0FFFEh reset otherwise Set if Rdst contained 0FEh reset otherwise C Set if Rdst contained 0FFFFEh or 0FFFFFh reset otherwise Set if Rdst contained 0FFFEh or 0FFFFh reset otherwise Set if Rdst contained 0FEh or 0FFh reset otherwise V Set if Rdst contained 07FFFEh or 07FFFFh reset otherwise Set if Rdst contained 07FFEh or 07FFFh reset otherwise Set if Rdst contained 07Eh or 0...

Page 280: ...F and GIE are not affected Examples Copy 20 bit value in R9 to R8 MOVA R9 R8 R9 R8 Write 20 bit immediate value 12345h to R12 MOVA 12345h R12 12345h R12 Copy 20 bit value addressed by R9 100h to R8 Source operand in ad dresses R9 100h LSBs and R9 102h MSBs MOVA 100h R9 R8 Index 32 K 2 words transferred Move 20 bit value in 20 bit absolute addresses EDE LSBs and EDE 2 MSBs to R12 MOVA EDE R12 EDE R...

Page 281: ...sferred Copy 20 bit value in R8 to destination addressed by R9 100h Destination operand in addresses R9 100h LSBs and R9 102h MSBs MOVA R8 100h R9 Index 32 K 2 words transferred Move 20 bit value in R13 to 20 bit absolute addresses EDE LSBs and EDE 2 MSBs MOVA R13 EDE R13 EDE 2 words transferred Move 20 bit value in R13 to 20 bit addresses EDE LSBs and EDE 2 MSBs PC index 32 K MOVA R13 EDE R13 EDE...

Page 282: ...ddress following the subroutine call The status register bits SR 11 0 are not affected This allows the transfer of information with these bits Status Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Call a subroutine SUBR from anywhere in the 20 bit address space and return to the address after the CALLA CALLA SUBR Call subro...

Page 283: ...ination register is not affected Status Bits N Set if destination register is negative reset if positive Z Set if destination register contains zero reset otherwise C Set V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example The 20 bit value in R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TSTA R7 Test R7 JN R7NEG R7 is negative JZ R7Z...

Page 284: ...N Set if result is negative src dst reset if positive src dst Z Set if result is zero src dst reset otherwise src dst C Set if there is a carry from the MSB Rdst 19 reset otherwise V Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a po...

Page 285: ...the clocks for MSP430x4xx devices This chapter discusses the FLL clock module The FLL clock module is implemented in all MSP430x4xx devices Topic Page 5 1 FLL Clock Module Introduction 5 2 5 2 FLL Clock Module Operation 5 6 5 3 FLL Clock Module Registers 5 13 Chapter 5 ...

Page 286: ...r that can be used with standard crystals resonators or external clock sources in the 450 kHz to 8 MHz range In MSP430F47x devices the upper limit is 16 MHz See the device specific data sheet for details DCOCLK Internal digitally controlled oscillator DCO with RC type characteristics stabilized by the FLL Four clock signals are available from the FLL module ACLK Auxiliary clock The ACLK is the LFX...

Page 287: ...enerator OSCOFF FNx SCG1 off SCG0 Enable PUC Reset ACLK MCLK XTS_FLL DCOPLUS FLL_DIVx FLLDx ACLK n CPUOFF XT20FF SELS SELMx 10 M fCrystal SMCLK SMCLKOFF XIN XOUT XT2IN XT2OUT XT2 Oscillator fDCO fDCO D N 1 0 1 1 0 1 0 1 0 00 01 10 11 00 01 10 11 Divider 1 2 4 8 Divider 1 2 4 8 4 LFXT1 Oscillator LF XT 0 V LFOff XT1Off 0 V fDCOCLK XCAPxPF ...

Page 288: ...rator DCO Modulator DC Generator OSCOFF FNx SCG1 off SCG0 Enable PUC Reset ACLK XTS_FLL DCOPLUS FLL_DIVx FLLDx ACLK n CPUOFF 10 M fCrystal SMCLK XIN XOUT fDCO fDCO D N 1 0 1 1 0 Divider 1 2 4 8 Divider 1 2 4 8 4 LFXT1 Oscillator LF XT 0 V LFOff XT1Off 0 V fDCOCLK XCAPxPF MCLK to CPU MCLK to Peripherals ...

Page 289: ...f SCG0 Enable PUC Reset ACLK MCLK XTS_FLL DCOPLUS FLL_DIVx FLLDx ACLK n CPUOFF XT20FF SELS SELMx 10 M fCrystal SMCLK SMCLKOFF XIN XOUT XT2IN XT2OUT XT2 Oscillator fDCO fDCO D N 1 0 1 1 0 1 0 1 0 00 01 10 11 00 01 10 11 Divider 1 2 4 8 Divider 1 2 4 8 4 LFXT1 Oscillator LF XT 0 V LFOff XT1Off 0 V fDCOCLK XCAPxPF supporting upto 16MHz XT2Sx ...

Page 290: ...lications Conflicting requirements typically exist in battery powered MSP430x4xx applications Low clock frequency for energy conservation and time keeping High clock frequency for fast reaction to events and fast burst processing capability Clock stability over operating temperature and supply voltage The FLL clock module addresses the above conflicting requirements by allowing the user to select ...

Page 291: ...internal pin capacitance plus the parasitic 2 pF pin capacitance combine serially to form the load capacitance The load capacitance can be selected as 1 6 8 or 10 pF Additional external capacitors can be added if necessary Software can disable LFXT1 by setting OSCOFF if this signal does not source MCLK SELM 3 or CPUOFF 1 Note LFXT1 Oscillator Characteristics Low frequency crystals often require hu...

Page 292: ...nly will cause the LFOF fault flag to remain set not allowing for the OFIFG to ever be cleared XT2 Oscillator in MSP430x47x Devices The MSP430x47x devices have a second crystal oscillator XT2 that supports crystals with up to 16MHz XT2 sources XT2CLK The XT2Sx bits select the range of operation of XT2 The XT2OFF bit disables the XT2 oscillator if XT2CLK is not used for MCLK or SMCLK as described a...

Page 293: ...ng frequency See the device specific datasheet for parameters Table 5 1 DCO Range Control Bits FN_8 FN_4 FN_3 FN_2 Typical fDCO Range 0 0 0 0 0 65 6 1 0 0 0 1 1 3 12 1 0 0 1 X 2 17 9 0 1 X X 2 8 26 6 1 X X X 4 2 46 5 2 5 Frequency Locked Loop FLL The FLL continuously counts up or down a 10 bit frequency integrator The output of the frequency integrator that drives the DCO can be read in SCFI1 and ...

Page 294: ...wo adjacent frequencies across 32 DCOCLK clock cycles The error of the effective frequency is zero every 32 DCOCLK cycles and does not accumulate The modulator settings and DCO control are automatically controlled by the FLL hardware Figure 5 4 illustrates the modulator operation Figure 5 4 Modulator Patterns Lower DCO Tap Frequency fDCO 31 24 16 15 5 4 3 2 1 0 Upper DCO Tap Frequency fDCO 1 One A...

Page 295: ...F and OSCOFF if set but does not clear SCG0 This means that FLL operation from within an interrupt service routine entered from LPM1 2 3 or 4 the FLL remains disabled and the DCO operates at the previous setting as defined in SCFI0 and SCFI1 SCG0 can be cleared by user software if FLL operation is required 5 2 9 Buffered Clock Output ACLK may be divided by 1 2 4 or 8 and buffered out of the device...

Page 296: ...F is also generated if the N multiplier value is set too high for the selected DCO frequency range resulting the DCO tap to move to the highest position SCFI1 7 to SCFI1 3 are set The DCOF is cleared automatically if the DCO tap is not in the lowest or the highest positions The OFIFG oscillator fault interrupt flag is set and latched at POR or when an oscillator fault LFOF XT1OF XT2OF or DCOF set ...

Page 297: ...clock frequency integrator 0 SCFI0 Read write 050h 040h with PUC System clock frequency integrator 1 SCFI1 Read write 051h Reset with PUC FLL control register 0 FLL_CTL0 Read write 053h 003h with PUC FLL control register 1 FLL_CTL1 Read write 054h Reset with PUC FLL control register 2 F47x only FLL_CTL2 Read write 055h Reset with PUC SFR interrupt enable register 1 IE1 Read write 0000h Reset with ...

Page 298: ...al SCFI0 System Clock Frequency Integrator Register 0 7 6 5 4 3 2 1 0 FLLDx FN_x MODx LSBs rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 FLLDx Bits 7 6 FLL loop divider These bits divide fDCOCLK in the FLL feedback loop This results in an additional multiplier for the multiplier bits See also multi plier bits 00 1 01 2 10 4 11 8 FN_x Bits 5 2 DCO Range Control These bits select the fDCO operating range ...

Page 299: ... 2 1 0 DCOx MODx MSBs rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 DCOx Bits 7 3 These bits select the DCO tap and are modified automatically by the FLL MODx Bit 2 Most significant modulator bits Bit 2 is the modulator MSB These bits af fect the modulator pattern All MODx bits are modified automatically by the FLL ...

Page 300: ... 1 High frequency mode XCAPxPF Bits 5 4 Oscillator capacitor selection These bits select the effective capacitance seen by the LFXT1 crystal or resonator Should be set to 00 if the high frequency mode is selected for LFXT1 with XTS_FLL 1 00 1 pF 01 6 pF 10 8 pF 11 10 pF XT2OF Bit 3 XT2 oscillator fault Not present in MSP430x41x MSP430x42x devices 0 No fault condition present 1 Fault condition pres...

Page 301: ... and MSP430x47x devices 0 Crystal input selected 1 Digital clock input selected SMCLKOFF Bit 6 SMCLK off This bit turns off SMCLK Not present in MSP430x41x MSPx42x devices 0 SMCLK is on 1 SMCLK is off XT2OFF Bit 5 XT2 off This bit turns off the XT2 oscillator Not present in MSP430x41x MSPx42x devices 0 XT2 is on 1 XT2 is off if it is not used for MCLK or SMCLK SELMx Bits 4 3 Select MCLK These bits...

Page 302: ...16MHz clock source Reserved Bits 5 0 Reserved IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 OFIE rw 0 Bits 7 2 These bits may be used by other modules See device specific datasheet OFIE Bit 1 Oscillator fault interrupt enable This bit enables the OFIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions ra...

Page 303: ...device specific datasheet OFIFG Bit 1 Oscillator fault interrupt flag Because other bits in IFG1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending Bits 0 This bit may be used by other modules See device specific datasheet ...

Page 304: ...5 20 FLL Clock Module ...

Page 305: ...ry Controller This chapter describes the operation of the MSP430 flash memory controller Topic Page 6 1 Flash Memory Introduction 6 2 6 2 Flash Memory Segmentation 6 4 6 3 Flash Memory Operation 6 6 6 4 Flash Memory Registers 6 21 Chapter 6 ...

Page 306: ...30 flash memory features include Internal programming voltage generation Bit byte or word programmable Ultralow power operation Segment erase and mass erase Marginal 0 and marginal 1 read mode implemented in F47x devices only see the device specific data sheet The block diagram of the flash memory and controller is shown in Figure 6 1 Note Minimum VCC During Flash Write or Erase The minimum VCC vo...

Page 307: ...er Figure 6 1 Flash Memory Module Block Diagram Enable Data Latch Enable Address Latch Address Latch Data Latch MAB MDB FCTL1 FCTL2 FCTL3 Timing Generator Programming Voltage Generator Flash Memory Array 1 Flash Memory Array 2 MSP430FG461x devices only ...

Page 308: ... the segment size and the physical addresses The information memory has four 64 byte segments on F47x devices or two 128 byte segments on all other 4xx devices The main memory has two or more 512 byte segments See the device specific data sheet for the complete memory map of a device The segments are further divided into blocks Figure 6 2 shows the flash segmentation using an example of 4 KB flash...

Page 309: ...any other flash memory segment and all information memory is erased during a mass erase or production programming The state of the LOCKA bit is toggled when a 1 is written to it Writing a 0 to LOCKA has no effect This allows existing flash programming routines to be used unchanged Unlock SegmentA BIT LOCKA FCTL3 Test LOCKA JZ SEGA_UNLOCKED Already unlocked MOV FWKEY LOCKA FCTL3 No unlock SegmentA ...

Page 310: ...d during the write or erase the code to be executed must be in RAM Any flash update can be initiated from within flash memory or RAM 6 3 1 Flash Memory Timing Generator Write and erase operations are controlled by the flash timing generator shown in Figure 6 3 The flash timing generator operating frequency fFTG must be in the range from 257 kHz to 476 kHz see device specific data sheet Figure 6 3 ...

Page 311: ...ry and information seg ments of both memory arrays Table 6 2 MSP430F47x Erase Modes MERAS ERASE Erase Mode 0 1 Segment erase 1 0 Mass erase all main memory segments 1 1 LOCKA 0 Erase main and information flash memory LOCKA 1 Erase only main flash memory Table 6 3 Erase Modes MERAS ERASE Erase Mode 0 1 Segment erase 1 0 Mass erase all main memory segments 1 1 Erase all flash memory main and informa...

Page 312: ...lobal Mass Erase see device specific data sheet Erase Time VCC Current Consumption is Increased Generate Programming Voltage Remove Programming Voltage A dummy write to an address not in the range to be erased does not start the erase cycle does not affect the flash memory and is not flagged in any way This errant dummy write is ignored ...

Page 313: ...ycle from within flash memory it is possible to erase the code needed for execution after the erase If this occurs CPU execution will be unpredictable after the erase cycle The flow to initiate an erase from flash is shown in Figure 6 5 Figure 6 5 Erase Cycle from Within Flash Memory Setup flash controller and erase mode Disable watchdog Set LOCK 1 re enable watchdog Dummy write Segment Erase from...

Page 314: ... be unpredictable The flow to initiate an erase from RAM is shown in Figure 6 6 Figure 6 6 Erase Cycle from Within RAM yes BUSY 1 yes BUSY 1 Disable watchdog Setup flash controller and erase mode Dummy write Set LOCK 1 re enable watchdog Segment Erase from RAM 514 kHz SMCLK 952 kHz Assumes ACCVIE NMIIE OFIE 0 MOV WDTPW WDTHOLD WDTCTL Disable WDT L1 BIT BUSY FCTL3 Test BUSY JNZ L1 Loop while busy M...

Page 315: ...on is initiated from RAM the CPU must not access flash while BUSY 1 Otherwise an access violation occurs ACCVIFG is set and the flash write is unpredictable Byte Word Write A byte word write operation can be initiated from within flash memory or from RAM When initiating from within flash memory all timing is controlled by the flash controller and the CPU is held while the write completes After the...

Page 316: ...y address within the block See the device specific data sheet for specifications Initiating a Byte Word Write from Within Flash Memory The flow to initiate a byte word write from flash is shown in Figure 6 8 Figure 6 8 Initiating a Byte Word Write from Flash Setup flash controller and set WRT 1 Disable watchdog Set WRT 0 LOCK 1 re enable watchdog Write byte or word Byte word write from flash 514 k...

Page 317: ...e byte or word Set WRT 0 LOCK 1 re enable watchdog Byte word write from RAM 514 kHz SMCLK 952 kHz Assumes 0FF1Eh is already erased Assumes ACCVIE NMIIE OFIE 0 MOV WDTPW WDTHOLD WDTCTL Disable WDT L1 BIT BUSY FCTL3 Test BUSY JNZ L1 Loop while busy MOV FWKEY FSSEL1 FN0 FCTL2 SMCLK 2 MOV FWKEY FCTL3 Clear LOCK MOV FWKEY WRT FCTL1 Enable write MOV 0123h 0FF1Eh 0123h 0FF1Eh L2 BIT BUSY FCTL3 Test BUSY ...

Page 318: ...ting each byte or word in the block When WAIT is set the next byte or word of the block can be written When writing successive blocks the BLKWRT bit must be cleared after the current block is complete BLKWRT can be set initiating the next block write after the required flash recovery time given by tEnd BUSY is cleared following each block write completion indicating the next block can be written F...

Page 319: ... block write flow is shown in Figure 6 11 and the following example Figure 6 11 Block Write Flow yes BUSY 1 Disable watchdog Setup flash controller Set BLKWRT WRT 1 Write byte or word no Block Border yes WAIT 0 yes BUSY 1 Set BLKWRT 0 yes Another Block Set WRT 0 LOCK 1 re enable WDT ...

Page 320: ...L Disable WDT L1 BIT BUSY FCTL3 Test BUSY JNZ L1 Loop while busy MOV FWKEY FSSEL1 FN0 FCTL2 SMCLK 2 MOV FWKEY FCTL3 Clear LOCK MOV FWKEY BLKWRT WRT FCTL1 Enable block write L2 MOV Write_Value 0 R6 Write location L3 BIT WAIT FCTL3 Test WAIT JZ L3 Loop while WAIT 0 INCD R6 Point to next word DEC R5 Decrement write counter JNZ L2 End of block MOV FWKEY FCTL1 Clear WRT BLKWRT L4 BIT BUSY FCTL3 Test BU...

Page 321: ...JMP PC instruction Any 0 ACCVIFG 1 LOCK 1 Read 1 ACCVIFG 0 03FFFh is the value read Block write Write 1 ACCVIFG 0 Flash is written Instruction fetch 1 ACCVIFG 1 LOCK 1 Interrupts are automatically disabled during any flash operation on F47x devices when EEI 0 and EEIEX 0 and on all other devices where EEI and EEIEX are not present After the flash operation has completed interrupts are automaticall...

Page 322: ... and copying back from RAM to flash The program checking the flash memory contents must be executed from RAM Executing code from flash will automatically disable the marginal read mode The marginal read modes are controlled by the MRG0 and MRG1 bits Setting MRG1 is used to detect insufficiently programmed flash cells containing a 1 erased bits Setting MRG0 is used to detect insufficiently programm...

Page 323: ...equires four signals ground and optionally VCC and RST NMI The JTAG port is protected with a fuse Blowing the fuse completely disables the JTAG port and is not reversible Further access to the device via JTAG is not possible For more details see the Application report Programming a Flash Based MSP430 Using the JTAG Interface at www msp430 com Programming Flash Memory via the Bootstrap loader BSL E...

Page 324: ... Memory Operation 6 20 Flash Memory Controller Figure 6 12 User Developed Programming Solution Host Flash Memory UART Px x SPI etc CPU executes user software Commands data etc Read write flash memory MSP430 ...

Page 325: ...Address Initial State Flash memory control register 1 FCTL1 Read write 0128h 09600h with PUC Flash memory control register 2 FCTL2 Read write 012Ah 09642h with PUC Flash memory control register 3 FCTL3 Read write 012Ch 09618h with PUC Flash memory control register 4 F47x devices only FCTL4 Read write 01BEh 0000h with PUC Interrupt Enable 1 IE1 Read write 000h Reset with PUC 09658h in F47x devices ...

Page 326: ...de BLKWRT is automatically reset when EMEX is set 0 Block write mode is off 1 Block write mode is on WRT Bit 6 Write This bit is used to select any write mode WRT is automatically reset when EMEX is set 0 Write mode is off 1 Write mode is on Reserved Bit 5 Reserved Always read as 0 EEIEX Bit 4 Enable Emergency Interrupt Exit Setting this bit enables an interrupt to cause an emergency exit from a f...

Page 327: ...t when EMEX is set or the erase operation completes GMERAS MERAS ERASE Erase Cycle 0 0 0 No erase X 0 1 Erase individual segment only 0 1 0 Erase main memory segment of selected array 0 1 1 Erase main memory segments and infor mation segments of selected array 1 1 0 Erase main memory segments of all memory arrays 1 1 1 Erase all main memory and information segments of all memory arrays Reserved Bi...

Page 328: ...0 rw 1 rw 0 FWKEYx Bits 15 8 FCTLx password Always read as 096h Must be written as 0A5h or a PUC will be generated FSSELx Bits 7 6 Flash controller clock source select 00 ACLK 01 MCLK 10 SMCLK 11 SMCLK FNx Bits 5 0 Flash controller clock divider These six bits select the divider for the flash controller clock The divisor value is FNx 1 For example when FNx 00h the divisor is 1 When FNx 03Fh the di...

Page 329: ...it to change its state Writing 0 has no effect 0 Segment A unlocked and all information memory is erased during a mass erase 1 Segment A locked and all information memory is protected from erasure during a mass erase EMEX Bit 5 Emergency exit 0 No emergency exit 1 Emergency exit LOCK Bit 4 Lock This bit unlocks the flash memory for writing or erasing The LOCK bit can be set anytime during a byte w...

Page 330: ...tes an incorrect FCTLx password was written to any flash control register and generates a PUC when set KEYV must be reset with software 0 FCTLx password was written correctly 1 FCTLx password was written incorrectly BUSY Bit 0 Busy This bit indicates the status of the flash timing generator 0 Not Busy 1 Busy ...

Page 331: ... read 1 mode This bit enables the marginal 1 read mode The marginal read 1 bit is cleared if the CPU starts execution from the flash memory If both MRG1 and MRG0 are set MRG1 is active and MRG0 is ignored 0 Marginal 1 read mode is disabled 1 Marginal 1 read mode is enabled MRG0 Bit 4 Marginal read 0 mode This bit enables the marginal 0 read mode The marginal mode 0 is cleared if the CPU starts exe...

Page 332: ...r modules See device specific data sheet ACCVIE Bit 5 Flash memory access violation interrupt enable This bit enables the ACCVIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled ...

Page 333: ...upervisor Supply Voltage Supervisor This chapter describes the operation of the SVS The SVS is implemented in all MSP430x4xx devices Topic Page 7 1 SVS Introduction 7 2 7 2 SVS Operation 7 4 7 3 SVS Registers 7 7 Chapter 7 ...

Page 334: ...eatures include AVCC monitoring Selectable generation of POR Output of SVS comparator accessible by software Low voltage condition latched and accessible by software 14 selectable threshold levels External channel to monitor external voltage The SVS block diagram is shown in Figure 7 1 Note MSP430x412 and MSP430x413 Voltage Level Detect The MSP430x412 and MSP430x413 devices implement only one volt...

Page 335: ...upply Voltage Supervisor Figure 7 1 SVS Block Diagram 1 2V Brownout Reset VCC Set SVSFG tReset 50us Reset SVSCTL Bits 0001 0010 1011 1111 1101 1100 G D S SVSOUT G D S VLD SVSON PORON SVSOP SVSFG 50us SVS_POR SVSIN AVCC AVCC ...

Page 336: ...SVS is on When VLDx 1111 the external SVSIN channel is selected The voltage on SVSIN is compared to an internal level of approximately 1 2 V 7 2 2 SVS Comparator Operation A low voltage condition exists when AVCC drops below the selected threshold or when the external voltage drops below its 1 2 V threshold Any low voltage condition sets the SVSFG bit The PORON bit enables or disables the device r...

Page 337: ...rt the SVS automatic settling delay td SVSon and switch the SVS to active mode immediately In doing so the SVS circuitry might not be settled resulting in unpredictable behavior When the VLDx bits are changed from any non zero value to any other non zero value the circuitry requires the time tsettle to settle The settling time tsettle is a maximum of 12 μs See the device specific data sheet There ...

Page 338: ... to the threshold The SVS operation and SVS Brownout interoperation are shown in Figure 7 2 Figure 7 2 Operating Levels for SVS and Brownout Reset Circuit V CC start AV CC V B_IT Brownout Region V SVSstart V SVS_IT td SVSR undefined Vhys SVS_IT 0 1 td BOR Brownout 0 1 td SVSon td BOR 0 1 Set SVS_POR Brown Out Region SVS Circuit Active SVSOUT Vhys B_IT Software Sets VLD 0 ...

Page 339: ...2 3 V 0101 2 4 V 0110 2 5 V 0111 2 65 V 1000 2 8 V 1001 2 9 V 1010 3 05 1011 3 2 V 1100 3 35 V 1101 3 5 V 1110 3 7 V 1111 Compares external input voltage SVSIN to 1 2 V PORON Bit 3 POR on This bit enables the SVSFG flag to cause a POR device reset 0 SVSFG does not cause a POR 1 SVSFG causes a POR SVSON Bit 2 SVS on This bit reflects the status of SVS operation This bit DOES NOT turn on the SVS The...

Page 340: ...7 8 Supply Voltage Supervisor ...

Page 341: ...ier This chapter describes the 16 bit hardware multiplier The hardware multiplier is implemented in MSP430x44x devices Topic Page 8 1 Hardware Multiplier Introduction 8 2 8 2 Hardware Multiplier Operation 8 3 8 3 Hardware Multiplier Registers 8 7 Chapter 8 ...

Page 342: ...nstructions The hardware multiplier supports Unsigned multiply Signed multiply Unsigned multiply accumulate Signed multiply accumulate 16 16 bits 16 8 bits 8 16 bits 8 8 bits The hardware multiplier block diagram is shown in Figure 8 1 Figure 8 1 Hardware Multiplier Block Diagram OP2 138h 16 x 16 Multipiler 32 bit Adder 32 bit Multiplexer 0 15 15 0 Multiplexer C MPY 130h MPYS 132h MAC 134h MACS 13...

Page 343: ...ct addressing for the result a NOP is required before the result is ready 8 2 1 Operand Registers The operand one register OP1 has four addresses shown in Table 8 1 used to select the multiply mode Writing the first operand to the desired address selects the type of multiply operation but does not start any operation Writing the second operand to the operand two register OP2 initiates the multiply...

Page 344: ...MPYS SUMEXT contains the extended sign of the result 00000h Result was positive or zero 0FFFFh Result was negative MAC SUMEXT contains the carry of the result 0000h No carry for result 0001h Result has a carry MACS SUMEXT contains the extended sign of the result 00000h Result was positive or zero 0FFFFh Result was negative MACS Underflow and Overflow The multiplier does not automatically detect un...

Page 345: ...esults 8x8 Signed Multiply Absolute addressing MOV B 012h 0132h Load first operand SXT MPYS Sign extend first operand MOV B 034h 0138h Load 2nd operand SXT OP2 Sign extend 2nd operand triggers 2nd multiplication Process results 16x16 Unsigned Multiply Accumulate MOV 01234h MAC Load first operand MOV 05678h OP2 Load 2nd operand Process results 8x8 Unsigned Multiply Accumulate Absolute addressing MO...

Page 346: ...Load 2nd operand NOP Need one cycle MOV R5 xxx Move RESLO MOV R5 xxx Move RESHI 8 2 5 Using Interrupts If an interrupt occurs after writing OP1 but before writing OP2 and the multiplier is used in servicing that interrupt the original multiplier mode selection is lost and the results are unpredictable To avoid this disable interrupts before using the hardware multiplier or do not use the multiplie...

Page 347: ...State Operand one multiply MPY Read write 0130h Unchanged Operand one signed multiply MPYS Read write 0132h Unchanged Operand one multiply accumulate MAC Read write 0134h Unchanged Operand one signed multiply accumulate MACS Read write 0136h Unchanged Operand two OP2 Read write 0138h Unchanged Result low word RESLO Read write 013Ah Undefined Result high word RESHI Read write 013Ch Undefined Sum Ex...

Page 348: ...8 8 16 Bit Hardware Multiplier ...

Page 349: ...cribes the 32 bit hardware multiplier MPY32 The 32 bit hardware multiplier is implemented in the MSP430x47x devices Topic Page 9 1 32 Bit Hardware Multiplier Introduction 9 2 9 2 32 Bit Hardware Multiplier Operation 9 4 9 3 32 Bit Hardware Multiplier Registers 9 21 Chapter 9 ...

Page 350: ...ters are peripheral registers that are loaded and read with CPU instructions The hardware multiplier supports Unsigned multiply Signed multiply Unsigned multiply accumulate Signed multiply accumulate 8 bit 16 bit 24 bit and 32 bit operands Saturation Fractional Numbers 8 bit and 16 bit operation compatible with 16 bit hardware multiplier 8 bit and 24 bit multiplications without requiring a sign ex...

Page 351: ...ccessible Register 32 bit Adder RES0 RESLO OP1 low word OP2 high word 15 OP2 low word 16 OP2 OP2L OP2H MACS32L MAC32L MPYS32L MPY32L MACS32H MAC32H MPYS32H MPY32H MACS MAC MPYS MPY RES1 RESHI RES2 RES3 SUMEXT 31 0 15 16 31 0 32 bit De Multiplexer 32 bit Multiplexer 16 bit Multiplexer 16 bit Multiplexer OP1_32 OP2_32 MPYMx MPYSAT MPYFRAC MPYC 2 Control Logic ...

Page 352: ...with the next instruction after writing to OP2 except when using an indirect addressing mode to access the result When using indirect addressing for the result a NOP is required before the result is ready The result of a 24 bit or 32 bit operation can be read with successive instructions after writing OP2 or OP2H starting with RES0 except when using an indirect addressing mode to access the result...

Page 353: ...tions It is not necessary to rewrite the OP1 value to perform the operations Table 9 2 OP1 registers OP1 Register Name Operation MPY Unsigned Multiply operand bits 0 up to 15 MPYS Signed Multiply operand bits 0 up to 15 MAC Unsigned Multiply Accumulate operand bits 0 up to 15 MACS Signed Multiply Accumulate operand bits 0 up to 15 MPY32L Unsigned Multiply operand bits 0 up to 15 MPY32H Unsigned Mu...

Page 354: ...y the register that is used to write the low word because this register defines if the operation is unsigned or signed The high word of a 32 bit operand remains unchanged when changing the size of the operand to 16 bit either by modifying the operand size bits or by writing to the respective operand register During the execution of the 16 bit operation the content of the high word is ignored Note ...

Page 355: ... registers SUMEXT contents depend on the multiply operation and are listed in Table 9 4 If all operands are 16 bits wide or less the 32 bit result is used to determine sign and carry If one of the operands is larger than 16 bits the 64 bit result is used The MPYC bit reflects the multiplier s carry as listed in Table 9 4 and thus can be used as 33rd or 65th bit of the result if fractional or satur...

Page 356: ...w occurs when the sum of two negative numbers yields a result that is in the range for a positive number An overflow occurs when the sum of two positive numbers yields a result that is in the range for a negative number The SUMEXT register contains the sign of the result in both cases described above 0FFFFh for a 32 bit overflow and 0000h for a 32 bit underflow The MPYC bit in MPY32CTL0 can be use...

Page 357: ...igh word of 1st operand MOV 05678h OP2L Load low word of 2nd operand MOV 05678h OP2H Load high word of 2nd operand Process results 16x16 Unsigned Multiply MOV 01234h MPY Load 1st operand MOV 05678h OP2 Load 2nd operand Process results 8x8 Unsigned Multiply Absolute addressing MOV B 012h MPY_B Load 1st operand MOV B 034h OP2_B Load 2nd operand Process results 32x32 Signed Multiply MOV 01234h MPYS32...

Page 358: ...st significant bit is used as the sign bit The most negative number is 08000h and the maximum positive number is 07FFFh This gives a range from 1 0 to 0 999969482 1 0 for the signed Q15 format with 16 bits Figure 9 2 Q15 Format Representation S 1 2 1 4 1 8 1 16 Decimal number equivalent Decimal point Sign bit 15 bits The range can be increased by shifting the decimal point to the right as shown in...

Page 359: ... using software the value is left shifted 1 bit resulting in the final Q formatted result This allows user software to switch between reading both the shifted fractional and the un shifted result The fractional mode should only be enabled when required and disabled after use In fractional mode the SUMEXT register contains the sign extended bits 32 and 33 of the shifted result for 16x16 bit operati...

Page 360: ... significant 32 bits i e the result registers RES0 and RES1 Using the saturation mode in MAC or MACS operations that mix 16x16 operations with 32x32 16x32 or 32x16 operations will lead to unpredictable results With 32x32 16x32 and 32x16 operations the saturated result can only be calculated when RES3 is ready In non 5xx devices reading RES0 to RES2 prior to the complete result being ready will del...

Page 361: ...00h RES0 00000h MPYFRAC 1 Yes No No Yes unshifted RES1 bit 15 0 and bit 14 1 Overflow RES3 unchanged RES2 unchanged RES1 07FFFh RES0 0FFFFh Yes No unshifted RES1 bit 15 1 and bit 14 0 Underflow RES3 unchanged RES2 unchanged RES1 08000h RES0 00000h Yes No 32 bit Saturation completed 64 bit Saturation MPYC 0 and unshifted RES3 bit 15 1 Overflow RES3 07FFFh RES2 0FFFFh RES1 0FFFFh RES0 0FFFFh Yes No ...

Page 362: ...lt is saturated because already the result not converted into a fractional number shows an overflow The multiplication of the two positive numbers 00050h and 00012h gives 005A0h 005A0h added to 07FFF FA60h results in 8000 059F without MPYC being set Since the MSB of the unmodified result RES1 is 1 and MPYC 0 the result is saturated according to the saturation flow chart in Figure 9 4 Note Validity...

Page 363: ...PY or MPYS Operation Perform 16x16 MAC or MACS Operation Yes No Yes No Yes No MPYFRAC 1 32 bit Saturation Shift 64 bit result Calculate SUMEXT based on MPYC and bit 15 of unshifted RES1 MPYSAT 1 Yes No 32 bit Saturation Yes No Multiplication completed MAC or MACS MPYSAT 1 Clear Result RES3 00000h RES2 00000h RES1 00000h RES0 00000h Perform MPY or MPYS Operation Perform MAC or MACS Operation Yes No...

Page 364: ...ACS Signed MAC operation MOV 0FFB6h OP2 16x16 bit operation MOV RESLO R6 R6 0FFFFh MOV RESHI R7 R7 07FFFh The second operation gives a saturated result because the 32 bit value used for the 16x16 bit MACS operation was already saturated when the operation was started the carry bit MPYC was 0 from the previous operation but the most significant bit in result register RES1 is set As one can see in t...

Page 365: ...ruction is needed between loading the second operand and accessing the result registers Access multiplier 16x16 results with indirect addressing MOV RES0 R5 RES0 address in R5 for indirect MOV OPER1 MPY Load 1st operand MOV OPER2 OP2 Load 2nd operand NOP Need one cycle MOV R5 xxx Move RES0 MOV R5 xxx Move RES1 In case of a 32x16 multiplication there is also one instruction required between reading...

Page 366: ...able To avoid this disable interrupts before using the hardware multiplier do not use the multiplier in interrupt service routines or use the save and restore functionality of the 32 bit multiplier Disable interrupts before using the hardware multiplier DINT Disable interrupts NOP Required for DINT MOV xxh MPY Load 1st operand MOV xxh OP2 Load 2nd operand EINT Interrupts may be enabled before proc...

Page 367: ..._USING_ISR PUSH MPY32CTL0 Save multiplier mode etc BIC MPYSAT MPYFRAC MPY32CTL0 Clear MPYSAT MPYFRAC PUSH RES3 Save result 3 PUSH RES2 Save result 2 PUSH RES1 Save result 1 PUSH RES0 Save result 0 PUSH MPY32H Save operand 1 high word PUSH MPY32L Save operand 1 low word PUSH OP2H Save operand 2 high word PUSH OP2L Save operand 2 low word Main part of ISR Using standard MPY routines POP OP2L Restore...

Page 368: ... start reading the re sult with MPY32RES0 successively up to MPY32RES3 Not all registers need to be read The trigger timing is such that the DMA controller starts reading MPY32RES0 when its ready and that the MPY32RES3 can be read exactly in the clock cycle when it is available to allow fastest access via DMA The sig nal into the DMA controller is Multiplier ready Please refer to the DMA user s gu...

Page 369: ...d 32 bit operand 1 multiply high word MPY32H Read write 0142h Unchanged 24 bit operand 1 multiply high byte MPY32H_B Read write 0142h Unchanged 32 bit operand 1 signed multiply low word MPYS32L Read write 0144h Unchanged 32 bit operand 1 signed multiply high word MPYS32H Read write 0146h Unchanged 24 bit operand 1 signed multiply high byte MPYS32H_B Read write 0146h Unchanged 32 bit operand 1 mult...

Page 370: ...t operand one multiply MPY_B MPYS32L_B 16 bit operand one signed multiply MPYS MPYS32L 8 bit operand one signed multiply MPYS_B MPYS32L_B 16 bit operand one multiply accumulate MAC MAC32L 8 bit operand one multiply accumulate MAC_B MAC32L_B 16 bit operand one signed multiply accumulate MACS MACS32L 8 bit operand one signed multiply accumulate MACS_B MACS32L_B 16x16 bit result low word RESLO RES0 1...

Page 371: ... bits MPYMx Bits 5 4 Multiplier mode 00 MPY Multiply 01 MPYS Signed multiply 10 MAC Multiply accumulate 11 MACS Signed multiply accumulate MPYSAT Bit 3 Saturation mode 0 Saturation mode disabled 1 Saturation mode enabled MPYFRAC Bit 2 Fractional mode 0 Fractional mode disabled 1 Fractional mode enabled Reserved Bit 1 Reserved MPYC Bit 0 Carry of the multiplier It can be considered as 33rd or 65th ...

Page 372: ...9 24 32 Bit Hardware Multiplier ...

Page 373: ...another without CPU intervention This chapter describes the operation of the DMA controller One DMA channel is implemented in MSP430FG43x and three DMA channels are implemented in MSP430FG461x devices Topic Page 10 1 DMA Introduction 10 2 10 2 DMA Operation 10 4 10 3 DMA Registers 10 19 Chapter 10 ...

Page 374: ...evices Using the DMA controller can increase the throughput of peripheral modules It can also reduce system power consumption by allowing the CPU to remain in a low power mode without having to awaken to move data to or from a peripheral The DMA controller features include Up to three independent transfer channels Configurable DMA channel priorities Requires only two MCLK clock cycles per transfer...

Page 375: ... received DMAE0 4 DMA0IFG 0000 0001 0010 0011 0100 0101 1111 1110 0110 0111 1000 1001 1010 DMAE0 4 DMA1IFG 0000 0001 0010 0011 0100 0101 1111 1110 0110 0111 1000 1001 1010 0000 0001 0010 0011 0100 0101 1111 1110 0110 0111 1000 1001 1010 Multiplier ready Serial data received Serial transmit ready DAC12_0IFG DMAREQ TACCR2_CCIFG TBCCR2_CCIFG Serial data received Serial transmit ready USART1 transmit ...

Page 376: ...The addressing modes are configured with the DMASRCINCRx and DMADSTINCRx control bits The DMASRCINCRx bits select if the source address is incremented decremented or unchanged after each transfer The DMADSTINCRx bits select if the destination address is incremented decremented or unchanged after each transfer Transfers may be byte to byte word to word byte to word or word to byte When transferring...

Page 377: ...er byte or word data It is also possible to transfer byte to byte word to word or any combination Table 10 1 DMA Transfer Modes DMADTx Transfer Mode Description 000 Single transfer Each transfer requires a trigger DMAEN is automatically cleared when DMAxSZ transfers have been made 001 Block transfer A complete block is transferred with one trigger DMAEN is automatically cleared at the end of the b...

Page 378: ...rs occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer The DMAxSZ register is decremented after each transfer When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set When DMADTx 0 the DMAEN bit is cleared a...

Page 379: ...L 1 DMAABORT 0 DMAABORT 1 2 x MCLK DMAEN 0 Modify T_SourceAdd Modify T_DestAdd Decrement DMAxSZ ENNMI 1 AND NMI event OR DMALEVEL 1 AND Trigger 0 DMADTx 0 AND DMAxSZ 0 OR DMAEN 0 DMAxSZ T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAREQ 0 DMAxSZ 0 AND DMAEN 1 DMAEN 0 DMAEN 1 T_Size DMAxSZ DMAxSA T_SourceAdd DMAxDA T_DestAdd DMADTx 4 AND DMAxSZ 0 AND DMAEN 1 DMAEN 0 DMAREQ 0 T_Size DMAxSZ ...

Page 380: ...Z 0 no transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it is reloaded from its tem...

Page 381: ...ALEVEL 1 DMAABORT 0 DMAABORT 1 2 x MCLK DMAEN 0 Modify T_SourceAdd Modify T_DestAdd Decrement DMAxSZ DMAxSZ 0 ENNMI 1 AND NMI event OR DMALEVEL 1 AND Trigger 0 DMADTx 1 AND DMAxSZ 0 OR DMAEN 0 DMAxSZ T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAREQ 0 T_Size DMAxSZ DMAxSA T_SourceAdd DMAxDA T_DestAdd DMADTx 5 AND DMAxSZ 0 AND DMAEN 1 DMAEN 0 DMAEN 1 DMAEN 0 DMAREQ 0 T_Size DMAxSZ ...

Page 382: ...er each transfer of the block If DMAxSZ 0 no transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decremen...

Page 383: ...MALEVEL 1 DMAABORT 0 DMAABORT 1 2 x MCLK DMAEN 0 Modify T_SourceAdd Modify T_DestAdd Decrement DMAxSZ DMADTx 6 7 AND DMAxSZ 0 ENNMI 1 AND NMI event OR DMALEVEL 1 AND Trigger 0 DMADTx 2 3 AND DMAxSZ 0 OR DMAEN 0 DMAxSZ T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd T_Size DMAxSZ DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAEN 0 DMAEN 1 DMAxSZ 0 DMAxSZ 0 AND a multiple of 4 words bytes were transferred DMAxSZ...

Page 384: ...cted as the trigger DMA transfers are triggered as long as the trigger signal is high and the DMAEN bit remains set The trigger signal must remain high for a block or burst block transfer to complete If the trigger signal goes low during a block or burst block transfer the DMA controller is held in its current state until the trigger goes back high or until the DMA registers are modified by softwa...

Page 385: ...nel conversions are performed the corresponding ADC12IFGx is the trigger When sequences are used the ADC12IFGx for the last conversion in the sequence is the trigger A transfer is triggered when the conversion is completed and the ADC12IFGx is set Setting the ADC12IFGx with software will not trigger a transfer All ADC12IFGx flags are automatically reset when the associated ADC12MEMx register is ac...

Page 386: ...rity channel then the third priority channel Transfers in progress are not halted if a higher priority channel is triggered The higher priority channel waits until the transfer in progress completes before starting The DMA channel priorities are configurable with the ROUNDROBIN bit When the ROUNDROBIN bit is set the channel that completes a transfer becomes the lowest priority The order of the pri...

Page 387: ...the DMA controller will temporarily restart MCLK sourced with DCOCLK for the single transfer or complete block or burst block transfer The CPU remains off and after the transfer completes MCLK is turned off The maximum DMA cycle time for all operating modes is shown in Table 10 3 Table 10 3 Maximum Single Transfer DMA Cycle Time CPU Operating Mode Clock Source Maximum DMA Cycle Time Active mode MC...

Page 388: ...G and other flags to determine the source of the interrupt The DMAIFG flags are not reset automatically and must be reset by software DMAIV DMA Interrupt Vector Generator MSP430FG461x devices implement the interrupt vector register DMAIV In this case all DMAIFG flags are prioritized and combined to source a single interrupt vector The interrupt vector register DMAIV is used to determine which flag...

Page 389: ... but not the task handling itself Interrupt handler for DMA0IFG DMA1IFG DMA2IFG Cycles DMA_HND Interrupt latency 6 ADD DMAIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP DMA0_HND Vector 2 DMA channel 0 2 JMP DMA1_HND Vector 4 DMA channel 1 2 JMP DMA2_HND Vector 6 DMA channel 2 2 RETI Vector 8 Reserved 5 RETI Vector 10 Reserved 5 RETI Vector 12 Reserved 5 RETI Vector 14 Reserved 5...

Page 390: ...uence can trigger a DMA transfer Any ADC12IFGx flag is automatically cleared when the DMA controller accesses the corresponding ADC12MEMx 10 2 11 Using DAC12 With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data to the DAC12_xDAT register DMA transfers are done without CPU intervention and independently of any low power modes The DMA controller increa...

Page 391: ...s DMA2SA Read write 01F2h Unchanged DMA channel 2 destination address DMA2DA Read write 01F4h Unchanged DMA channel 2 transfer size DMA2SZ Read write 01F6h Unchanged Table 10 5 DMA Registers MSP430FG461x devices Register Short Form Register Type Address Initial State DMA control 0 DMACTL0 Read write 0122h Reset with POR DMA control 1 DMACTL1 Read write 0124h Reset with POR DMA interrupt vector DMA...

Page 392: ...it 0010 TBCCR2 CCIFG bit 0011 URXIFG0 MSP430FG43x UCA0RXIFG MPS430FG461x 0100 UTXIFG0 MSP430FG43x UCA0TXIFG MSP430FG461x 0101 DAC12_0CTL DAC12IFG bit 0110 ADC12 ADC12IFGx bit 0111 TACCR0 CCIFG bit 1000 TBCCR0 CCIFG bit 1001 URXIFG1 bit 1010 UTXIFG1 bit 1011 Multiplier ready 1100 No action MSP430FG43x UCB0RXIFG MSP430FG461x 1101 No action MSP430FG43x UCB0TXIFG MSP430FG461x 1110 DMA0IFG bit triggers...

Page 393: ...ransfer occurs on next instruction fetch after the trigger ROUND ROBIN Bit 1 Round robin This bit enables the round robin DMA channel priorities 0 DMA channel priority is DMA0 DMA1 DMA2 1 DMA channel priority changes with each transfer ENNMI Bit 0 Enable NMI This bit enables the interruption of a DMA transfer by an NMI interrupt When an NMI interrupts a DMA transfer the current transfer is complet...

Page 394: ...DMADSTBYTE 0 the destination address increments decrements by two The DMAxDA is copied into a temporary register and the temporary register is incremented or decremented DMAxDA is not incremented or decremented 00 Destination address is unchanged 01 Destination address is unchanged 10 Destination address is decremented 11 Destination address is incremented DMA SRCINCRx Bits 9 8 DMA source incremen...

Page 395: ... sensitive high level DMAEN Bit 4 DMA enable 0 Disabled 1 Enabled DMAIFG Bit 3 DMA interrupt flag 0 No interrupt pending 1 Interrupt pending DMAIE Bit 2 DMA interrupt enable 0 Disabled 1 Enabled DMA ABORT Bit 1 DMA Abort This bit indicates if a DMA transfer was interrupt by an NMI 0 DMA transfer not interrupted 1 DMA transfer was interrupted by NMI DMAREQ Bit 0 DMA request Software controlled DMA ...

Page 396: ...ource address register points to the DMA source address for single transfers or the first source address for block transfers The source address register remains unchanged during block and burst block transfers Devices that have addressable memory range 64 KB or below contain a single word for the DMAxSA MSP430FG461x devices implement two words for the DMAxSA register as shown Bits 31 20 are reserv...

Page 397: ...ress The destination address register points to the destination address for single transfers or the first address for block transfers The DMAxDA register remains unchanged during block and burst block transfers Devices that have addressable memory range 64 KB or below contain a single word for the DMAxDA MSP430FG461x devices implement two words for the DMAxDA register as shown Bits 31 20 are reser...

Page 398: ...ize register defines the number of byte word data per block transfer DMAxSZ register decrements with each word or byte transfer When DMAxSZ decrements to 0 it is immediately and automatically reloaded with its previously initialized value 00000h Transfer is disabled 00001h One byte or word to be transferred 00002h Two bytes or words have to be transferred 0FFFFh 65535 bytes or words have to be tra...

Page 399: ...6 5 4 3 2 1 0 0 0 0 0 DMAIVx 0 r0 r0 r0 r0 r 0 r 0 r 0 r0 DMAIVx Bits 15 0 DMA Interrupt Vector value DMAIV Contents Interrupt Source Interrupt Flag Interrupt Priority 00h No interrupt pending 02h DMA channel 0 DMA0IFG Highest 04h DMA channel 1 DMA1IFG 06h DMA channel 2 DMA2IFG 08h Reserved 0Ah Reserved 0Ch Reserved 0Eh Reserved Lowest ...

Page 400: ...10 28 DMA Controller ...

Page 401: ...Digital I O Digital I O This chapter describes the operation of the digital I O ports Topic Page 11 1 Digital I O Introduction 11 2 11 2 Digital I O Operation 11 3 11 3 Digital I O Registers 11 7 Chapter 11 ...

Page 402: ...and P2 have interrupt capability Each interrupt for the P1 and P2 I O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal All P1 I O lines source a single interrupt vector and all P2 I O lines source a different single interrupt vector The digital I O features include Independently programmable individual I Os Any combination...

Page 403: ... and P10IN read simultaneously as 16 bit port 11 2 1 Input Register PxIN Each bit in each PxIN register reflects the value of the input signal at the corresponding I O pin when the pin is configured as I O function Bit 0 The input is low Bit 1 The input is high Note Writing to Read Only Registers PxIN Writing to these read only registers results in increased current consumption while the write att...

Page 404: ...n Setting PxSELx 1 does not automatically set the pin direction Other peripheral module functions may require the PxDIRx bits to be configured according to the direction needed for the module function See the pin schematics in the device specific datasheet Output ACLK on P1 5 on MSP430F41x BIS B 020h P1SEL Select ACLK function for pin BIS B 020h P1DIR Set direction to output Required Note P1 and P...

Page 405: ... Each PxIFG flag must be reset with software Software can also set each PxIFG flag providing a way to generate a software initiated interrupt Bit 0 No interrupt is pending Bit 1 An interrupt is pending Only transitions not static levels cause interrupts If any PxIFGx flag becomes set during a Px interrupt service routine or is set after the RETI instruction of a Px interrupt service routine is exe...

Page 406: ...upt flags PxIESx PxINx PxIFGx 0 1 0 May be set 0 1 1 Unchanged 1 0 0 Unchanged 1 0 1 May be set Interrupt Enable P1IE P2IE Each PxIE bit enables the associated PxIFG interrupt flag Bit 0 The interrupt is disabled Bit 1 The interrupt is enabled 11 2 7 Configuring Unused Port Pins Unused I O pins should be configured as I O function output direction and left unconnected on the PC board to reduce pow...

Page 407: ...write Reset with PUC Port Select P2SEL 02Eh Read write 0C0h with PUC Resistor Enable P2REN 02Fh Read write Reset with PUC P3 Input P3IN 018h Read only Output P3OUT 019h Read write Unchanged Direction P3DIR 01Ah Read write Reset with PUC Port Select P3SEL 01Bh Read write Reset with PUC Resistor Enable P3REN 010h Read write Reset with PUC P4 Input P4IN 01Ch Read only Output P4OUT 01Dh Read write Unc...

Page 408: ...Dh Read write Reset with PUC Port Select P8SEL 03Fh Read write Reset with PUC Resistor Enable P8REN 015h Read write Reset with PUC P9 PB Input P9IN 008h Read only PB Output P9OUT 00Ah Read write Unchanged Direction P9DIR 00Ch Read write Reset with PUC Port Select P9SEL 00Eh Read write Reset with PUC Resistor Enable P9REN 016h Read write Reset with PUC P10 Input P10IN 009h Read only Output P10OUT 0...

Page 409: ...hapter describes the watchdog timer The watchdog timer is implemented in all MSP430x4xx devices except those with the enhanced watchdog timer WDT The WDT is implemented in the MSP430x42x MSP430FE42xx MSP430FG461x and MSP430F47x devices Topic Page 12 1 Watchdog Timer Introduction 12 2 12 2 Watchdog Timer Operation 12 4 12 3 Watchdog Timer Registers 12 7 Chapter 12 ...

Page 410: ...t selected time intervals Features of the watchdog timer module include Four software selectable time intervals Watchdog mode Interval mode Access to WDT control register is password protected Control of RST NMI pin function Selectable clock source Can be stopped to conserve power Clock fail safe feature in WDT The WDT block diagram is shown in Figure 12 1 Note Watchdog Timer Powers Up Active Afte...

Page 411: ...1 1 A EN PUC SMCLK ACLK Clear Password Compare 0 0 0 0 1 1 1 1 WDTCNTCL WDTTMSEL WDTNMI WDTNMIES WDTIS1 WDTSSEL WDTIS0 WDTHOLD EQU EQU Write Enable Low Byte R W MDB LSB MSB WDTCTL Asyn Int Flag Pulse Generator SMCLK Active MCLK Active ACLK Active 16 bit MSP430x42x MSP430FE42x MSP430FG461x and MSP430F47x devices only Fail Safe Logic Clock Request Logic MCLK ...

Page 412: ...lected with the WDTSSEL bit 12 2 2 Watchdog Mode After a PUC condition the WDT module is configured in the watchdog mode with an initial 32768 cycle reset interval using the DCOCLK The user must setup halt or clear the WDT prior to the expiration of the initial reset interval or another PUC will be generated When the WDT is configured to operate in watchdog mode either writing to WDTCTL with an in...

Page 413: ...al timer mode the WDTIFG flag is set after the selected time interval and requests a WDT interval timer interrupt if the WDTIE and the GIE bits are set The interval timer interrupt vector is different from the reset vector used in watchdog mode In interval timer mode the WDTIFG flag is reset automatically when the interrupt is serviced or can be reset with software 12 2 5 WDT Enhancements The WDT ...

Page 414: ... 3 because SMCLK is not active in LPM3 and the WDT would not function In this case with the WDT SMCLK would remain enabled increasing the current consumption of LPM3 When the watchdog timer is not required the WDTHOLD bit can be used to hold the WDTCNT reducing power consumption 12 2 7 Software Examples Any write operation to WDTCTL must be a word operation with 05Ah WDTPW in the upper byte Period...

Page 415: ... in Table 12 1 Table 12 1 Watchdog Timer Registers Register Short Form Register Type Address Initial State Watchdog timer control register WDTCTL Read write 0120h 06900h with PUC SFR interrupt enable register 1 IE1 Read write 0000h Reset with PUC SFR interrupt flag register 1 IFG1 Read write 0002h Reset with PUC WDTIFG is reset with POR ...

Page 416: ... the NMI interrupt when WDTNMI 1 Modifying this bit can trigger an NMI Modify this bit when WDTNMI 0 to avoid triggering an accidental NMI 0 NMI on rising edge 1 NMI on falling edge WDTNMI Bit 5 Watchdog timer NMI select This bit selects the function for the RST NMI pin 0 Reset function 1 NMI function WDTTMSEL Bit 4 Watchdog timer mode select 0 Watchdog mode 1 Interval timer mode WDTCNTCL Bit 3 Wa...

Page 417: ...t using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled Bits 3 1 These bits may be used by other modules See device specific datasheet WDTIE Bit 0 Watchdog timer interrupt enable This bit enables the WDTIFG interrupt for interval timer mode It is not necessary to set this bit for watchdog mode Because other bits in IE1 may be used for...

Page 418: ... instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending Bits 3 1 These bits may be used by other modules See device specific datasheet WDTIFG Bit 0 Watchdog timer interrupt flag In watchdog mode WDTIFG remains set until reset by software In interval mode WDTIFG is reset automatically by servicing the interrupt or can be reset by software Because other bits ...

Page 419: ... two independent cascadable 8 bit timers This chapter describes the Basic Timer1 Basic Timer1 is implemented in all MSP430x4xx devices Topic Page 13 1 Basic Timer1 Introduction 13 2 13 2 Basic Timer1 Operation 13 4 13 3 Basic Timer1 Registers 13 6 Chapter 13 ...

Page 420: ...ion Some uses for the Basic Timer1 include Real time clock RTC function Software time increments Basic Timer1 features include Selectable clock source Two independent cascadable 8 bit timers Interrupt capability LCD control signal generation The Basic Timer1 block diagram is shown in Figure 13 1 Note Basic Timer1 Initialization The Basic Timer1 module registers have no initial condition These regi...

Page 421: ...Timer1 Figure 13 1 Basic Timer1 Block Diagram BTCNT2 Set_BTIFG BTCNT1 EN1 CLK1 Q4 Q5 Q6 Q7 BTDIV BTHOLD ACLK EN2 CLK2 Q4 Q5 Q6 Q7 Q3 Q2 Q1 Q0 BTSSEL SMCLK BTIPx BTFRFQx ACLK 256 fLCD 00 01 10 11 11 10 01 00 111 110 101 100 001 011 010 000 ...

Page 422: ...wo The Basic Timer1 counter two BTCNT2 is an 8 bit timer counter directly accessible by software BTCNT2 can be sourced from ACLK or SMCLK or ACLK 256 when cascaded with BTCNT1 The BTCNT2 clock source is selected with the BTSSEL and BTDIV bits BTCNT2 can be stopped to reduce power consumption by setting the HOLD bit BTCNT2 sources the Basic Timer1 interrupt BTIFG The interrupt interval is selected ...

Page 423: ...ith a frame frequency of 30 Hz to 100 Hz fFrame from LCD datasheet 30 Hz to 100 Hz fLCD 2 3 fFrame fLCD min 180 Hz fLCD max 600 Hz select fLCD 32768 128 256 Hz or 32768 64 512 Hz The LCD_A controller does not use the Basic Timer1 for fLCD generation See the LCD Controller and LCD_A Controller chapters for more details on the LCD controllers 13 2 5 Basic Timer1 Interrupts The Basic Timer1 uses two ...

Page 424: ...tate Basic Timer1 Control BTCTL Read write 040h Unchanged Basic Timer1 Counter 1 BTCNT1 Read write 046h Unchanged Basic Timer1 Counter 2 BTCNT2 Read write 047h Unchanged SFR interrupt enable register 2 IE2 Read write 001h Reset with PUC SFR interrupt flag register 2 IFG2 Read write 003h Reset with PUC Note The Basic Timer1 registers should be configured at power up There is no initial state for BT...

Page 425: ...d BTCNT2 are operational 1 BTCNT1 is held if BTDIV 1 BTCNT2 is held BTDIV Bit 5 Basic Timer1 clock divide This bit together with the BTSSEL bit selects the clock source for BTCNT2 BTSSEL BTDIV BTCNT2 Clock Source 0 0 ACLK 0 1 ACLK 256 1 0 SMCLK 1 1 ACLK 256 BTFRFQx Bits 4 3 fLCD frequency These bits control the LCD update frequency 00 fACLK 32 01 fACLK 64 10 fACLK 128 11 fACLK 256 BTIPx Bits 2 0 B...

Page 426: ... 6 5 4 3 2 1 0 BTCNT1x rw rw rw rw rw rw rw rw BTCNT1x Bits 7 0 BTCNT1 register The BTCNT1 register is the count of BTCNT1 BTCNT2 Basic Timer1 Counter 2 7 6 5 4 3 2 1 0 BTCNT2x rw rw rw rw rw rw rw rw BTCNT2x Bits 7 0 BTCNT2 register The BTCNT2 register is the count of BTCNT2 ...

Page 427: ... 0 Interrupt not enabled 1 Interrupt enabled Bits 6 1 These bits may be used by other modules See device specific datasheet IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 BTIFG rw 0 BTIFG Bit 7 Basic Timer1 interrupt flag Because other bits in IFG2 may be used for other modules it is recommended to clear BTIFG automatically by servicing the interrupt or by using BIS B or BIC B instructions rather ...

Page 428: ...13 10 Basic Timer1 ...

Page 429: ...it counter module with calendar function This chapter describes the Real Time Clock RTC module The RTC is implemented in MSP430FG461x devices Topic Page 14 1 Real Time Clock Introduction 14 2 14 2 Real Time Clock Operation 14 4 14 3 Real Time Clock Registers 14 7 Chapter 14 ...

Page 430: ...nd clock mode 32 bit counter mode with selectable clock sources Automatic counting of seconds minutes hours day of week day of month month and year in calender mode Interrupt capability Selectable BCD format The RTC block diagram is shown in Figure 14 1 Note Real Time Clock Initialization Most RTC module registers have no initial condition These registers must be configured by user software before...

Page 431: ...G RTCNT3 RTCHOUR 00 01 10 11 RTCBCD RTCNT1 RTCSEC RTCNT2 RTCMIN RTCNT4 RTCDOW 16 23 24 31 Calendar RTCMON RTCYEARL RTCYEARH BCD BCD RTCDAY RTCTEVx EN Mode RTCHOLD Set_BTIFG RTCIE 0 1 Set_BTIFG from Basic Timer Midnight 8 bit overflow minute changed 16 bit overflow hour changed 24 bit overflow RTCHOUR Midnight 32 bit overflow RTCHOUR Noon ...

Page 432: ...he Basic Timer1 module selected by the RTCMODEx bits The counter can be stopped by setting the RTCHOLD bit Four individual 8 bit counters are cascaded to provide the 32 bit counter This provides interrupt triggers at 8 bit 16 bit 24 bit and 32 bit overflows Each counter RTCNT1 RTCNT4 is individually accessible and may be read or written to Note Accessing the RTCNTx registers When the counter clock...

Page 433: ...r clock is asynchronous to the CPU clock any read from any counting register should occur while the counter is not operating Otherwise the results may be unpredictable Alternatively the counter may be read multiple times while operating and a majority vote taken in software to determine the correct reading Any write to any counting register takes effect immediately However the clock is stopped dur...

Page 434: ...The RTCFG flag must be cleared with software when RTCIE 0 When RTCIE 1 the RTC controls interrupt generation and the Basic Timer1 BTIPx bits are ignored In this case the RTCFG and BTIFG flags are set at the interval selected with the RTCEVx bits and an interrupt request is generated if the GIE bit is set Both the RTCFG and BTIFG flags are reset automatically when the interrupt is serviced or can b...

Page 435: ... Unchanged Real Time Clock day of month RTCDAY Read write 04Ch Unchanged Real Time Clock month RTCMON Read write 04Dh Unchanged Real Time Clock year low byte RTCYEARL Read write 04Eh Unchanged Real Time Clock year high byte RTCYEARH Read write 04Fh Unchanged SFR interrupt enable register 2 IE2 Read write 001h Reset with PUC SFR interrupt flag register 2 IFG2 Read write 003h Reset with PUC Note Mod...

Page 436: ... Bits 5 4 Real Time Clock mode and clock source select RTCMODEx Counter Mode Clock Source 00 32 bit counter ACLK 01 32 bit counter BTCNT2 Q6 10 32 bit counter SMCLK 11 Calendar mode BTCNT2 Q6 RTCTEVx Bits 3 2 Real Time Clock interrupt event These bits select the event for setting RTCFG RTC Mode RTCTEVx Interrupt Interval Counter Mode 00 8 bit overflow 01 16 bit overflow 10 24 bit overflow 11 32 bi...

Page 437: ... 7 6 5 4 3 2 1 0 RTCNT2x rw rw rw rw rw rw rw rw RTCNT2x Bits 7 0 RTCNT2 register The RTCNT2 register is the count of RTCNT2 RTCNT3 RTC Counter 3 Counter Mode 7 6 5 4 3 2 1 0 RTCNT3x rw rw rw rw rw rw rw rw RTCNT3x Bits 7 0 RTCNT3 register The RTCNT3 register is the count of RTCNT3 RTCNT4 RTC Counter 4 Counter Mode 7 6 5 4 3 2 1 0 RTCNT4x rw rw rw rw rw rw rw rw RTCNT4x Bits 7 0 RTCNT4 register Th...

Page 438: ...gister Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 Seconds high digit 0 5 Seconds low digit 0 9 r 0 rw rw rw rw rw rw rw RTCMIN RTC Minutes Register Calendar Mode with Hexadecimal Format 7 6 5 4 3 2 1 0 0 0 Minutes 0 59 r 0 r 0 rw rw rw rw rw rw RTCMIN RTC Minutes Register Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 Minutes high digit 0 5 Minutes low digit 0 9 r 0 rw rw rw rw rw rw rw ...

Page 439: ... 5 4 3 2 1 0 0 0 0 Hours 0 24 r 0 r 0 r 0 rw rw rw rw rw RTCHOUR RTC Hours Register Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 0 Hours high digit 0 2 Hours low digit 0 9 r 0 r 0 rw rw rw rw rw rw RTCDOW RTC Day of Week Register Calendar Mode 7 6 5 4 3 2 1 0 0 0 0 0 0 Day of Week 0 6 r 0 r 0 r 0 r 0 r 0 rw rw rw ...

Page 440: ...nth Register Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 0 Day of Month high digit 0 3 Day of Month low digit 0 9 r 0 r 0 rw rw rw rw rw rw RTCMON RTC Month Register Calendar Mode with Hexadecimal Format 7 6 5 4 3 2 1 0 0 0 0 0 Month 1 12 r 0 r 0 r 0 r 0 rw rw rw rw RTCMON RTC Month Register Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 0 0 Month high digit 0 3 Month low digit 0 9 r 0 r 0 r ...

Page 441: ...gister Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 Decade 0 9 Year lowest digit 0 9 rw rw rw rw rw rw rw rw RTCYEARH RTC Year High Byte Register Calendar Mode with Hexadecimal Format 7 6 5 4 3 2 1 0 0 0 0 0 Year High Byte of 0 4095 r 0 r 0 r 0 r 0 rw rw rw rw RTCYEARH RTC Year High Byte Register Calendar Mode with BCD Format 7 6 5 4 3 2 1 0 0 Century high digit 0 4 Century low digit 0 9 r 0 rw r...

Page 442: ...s 0 Interrupt not enabled 1 Interrupt enabled Bits 6 1 These bits may be used by other modules See device specific data sheet IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 BTIFG rw 0 BTIFG Bit 7 Basic Timer1 interrupt flag Because other bits in IFG2 may be used for other modules it is recommended to clear BTIFG automatically by servicing the interrupt or by using BIS B or BIC B instructions rathe...

Page 443: ... multiple capture compare registers This chapter describes Timer_A This chapter describes the operation of the Timer_A of the MSP430x4xx device family Topic Page 15 1 Timer_A Introduction 15 2 15 2 Timer_A Operation 15 4 15 3 Timer_A Registers 15 19 Chapter 15 ...

Page 444: ...ure compare registers Configurable outputs with PWM capability Asynchronous input and output latching Interrupt vector register for fast decoding of all Timer_A interrupts The block diagram of Timer_A is shown in Figure 15 1 Note Use of the Word Count Count is used throughout this chapter It means the counter must be in the process of counting for the action to take place If a particular value is ...

Page 445: ...COV logic Output Unit4 D Set Q EQU0 OUT OUT4 Signal Reset GND VCC CCI4A CCI4B EQU4 Divider 1 2 4 8 Count Mode 16 bit Timer TAR RC Set TAIFG 15 0 TASSELx MCx IDx 00 01 10 11 Clear Timer Clock EQU0 Timer Clock Timer Clock TACCR4 SCCI Y A EN CCR1 POR TACLR CCR0 Timer Block 00 01 10 11 Set TA1CCR4 CCIFG CAP 1 0 1 0 CCR2 CCR3 ACLK SMCLK TACLK ...

Page 446: ...is recommended to stop the timer before modifying its operation with exception of the interrupt enable interrupt flag and TACLR to avoid errant operating conditions When the timer clock is asynchronous to the CPU clock any read from TAR should occur while the timer is not operating or the results may be unpredictable Alternatively the timer may be read multiple times while operating and a majority...

Page 447: ...this scenario the timer starts incrementing in the up direction from zero 15 2 3 Timer Mode Control The timer has four modes of operation as described in Table 15 1 stop up continuous and up down The operating mode is selected with the MCx bits Table 15 1 Timer Modes MCx Mode Description 00 Stop The timer is halted 01 Up The timer repeatedly counts from zero to the value of TACCR0 10 Continuous Th...

Page 448: ...ode 0h 0FFFFh TACCR0 The TACCR0 CCIFG interrupt flag is set when the timer counts to the TACCR0 value The TAIFG interrupt flag is set when the timer counts from TACCR0 to zero Figure 15 3 shows the flag set cycle Figure 15 3 Up Mode Flag Setting CCR0 1 CCR0 0h Timer Clock Timer Set TAIFG Set TACCR0 CCIFG 1h CCR0 1 CCR0 0h Changing the Period Register TACCR0 When changing TACCR0 while the timer is ...

Page 449: ...re 15 4 The capture compare register TACCR0 works the same way as the other capture compare registers Figure 15 4 Continuous Mode 0h 0FFFFh The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero Figure 15 5 shows the flag set cycle Figure 15 5 Continuous Mode Flag Setting FFFEh FFFFh 0h Timer Clock Timer Set TAIFG 1h FFFEh FFFFh 0h ...

Page 450: ...e without impact from interrupt latency Up to three Timer_A3 or five Timer_A5 independent time intervals or output frequencies can be generated using capture compare registers Figure 15 6 Continuous Mode Time Intervals 0FFFFh TACCR0a TACCR0b TACCR0c TACCR0d t1 t0 t0 TACCR1a TACCR1b TACCR1c TACCR1d t1 t1 t0 Time intervals can be produced with other modes as well where TACCR0 is used as the period r...

Page 451: ...in the same direction it was counting before it was stopped If this is not desired the TACLR bit must be set to clear the direction The TACLR bit also clears the TAR value and the clock divider In up down mode the TACCR0 CCIFG interrupt flag and the TAIFG interrupt flag are set only once during a period separated by 1 2 the timer period The TACCR0 CCIFG interrupt flag is set when the timer counts ...

Page 452: ...l count may occur before the counter begins counting down Use of the Up Down Mode The up down mode supports applications that require dead times between output signals See section Timer_A Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the example shown in Figure 15 9 the tdead is tdead ttimer TACCR1 TACCR2 With t...

Page 453: ...TACCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit MSP430x4xx family devices may have different signals connected to CCIxA and CCIxB See the device specific data sheet for the connections of these signals The capture signal can be asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capture w...

Page 454: ...edges Software then sets CCIS1 1 and toggles bit CCIS0 to switch the capture signal between VCC and GND initiating a capture each time CCIS0 changes state MOV CAP SCS CCIS1 CM_3 TACCTLx Setup TACCTLx XOR CCIS0 TACCTLx TACCTLx TAR Compare Mode The compare mode is selected when CAP 0 The compare mode is used to generate PWM output signals or interrupts at specific time intervals When TAR counts to t...

Page 455: ...n the timer counts to the TACCRx value It remains set until a reset of the timer or until another output mode is selected and affects the output 010 Toggle Reset The output is toggled when the timer counts to the TACCRx value It is reset when the timer counts to the TACCR0 value 011 Set Reset The output is set when the timer counts to the TACCRx value It is reset when the timer counts to the TACCR...

Page 456: ...nding on the output mode An example is shown in Figure 15 12 using TACCR0 and TACCR1 Figure 15 12 Output Example Timer in Up Mode 0h 0FFFFh EQU0 TAIFG Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TACCR0 TACCR1 EQU1 EQU0 TAIFG EQU1 EQU0 TAIFG Interrupt Events ...

Page 457: ...on the output mode An example is shown in Figure 15 13 using TACCR0 and TACCR1 Figure 15 13 Output Example Timer in Continuous Mode 0h 0FFFFh TAIFG Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TACCR0 TACCR1 EQU1 TAIFG EQU1 EQU0 Interrupt Events EQU0 ...

Page 458: ... Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TACCR0 TACCR2 EQU2 TAIFG Interrupt Events EQU2 EQU0 EQU2 EQU2 EQU0 Note Switching Between Output Modes When switching between output modes one of the OUTMODx bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decode...

Page 459: ...set Timer Clock POR CAP EQU0 Capture IRACC Interrupt Request Accepted CCIE TAIV Interrupt Vector Generator The TACCR1 CCIFG TACCR2 CCIFG and TAIFG flags are prioritized and combined to source a single interrupt vector The interrupt vector register TAIV is used to determine which flag requested an interrupt The highest priority enabled interrupt generates a number in the TAIV register see register ...

Page 460: ...apture compare block TACCR0 11 cycles Capture compare blocks TACCR1 TACCR2 16 cycles Timer overflow TAIFG 14 cycles Interrupt handler for TACCR0 CCIFG Cycles CCIFG_0_HND Start of handler Interrupt latency 6 RETI 5 Interrupt handler for TAIFG TACCR1 and TACCR2 CCIFG TA_HND Interrupt latency 6 ADD TAIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP CCIFG_1_HND Vector 2 TACCR1 2 JMP C...

Page 461: ...A3 capture compare 2 TACCR2 TA0CCR2 Read write 0176h Reset with POR Timer_A interrupt vector Timer0_A3 interrupt vector TAIV TA0IV Read only 012Eh Reset with POR Table 15 4 Timer1_A5 Registers Register Short Form Register Type Address Initial State Timer1_A5 control TA1CTL Read write 0180h Reset with POR Timer1_A5 counter TA1R Read write 0190h Reset with POR Timer1_A5 capture compare control 0 TA1...

Page 462: ...ts 5 4 Mode control Setting MCx 00h when Timer_A is not in use conserves power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TACCR0 10 Continuous mode the timer counts up to 0FFFFh 11 Up down mode the timer counts up to TACCR0 then down to 0000h Unused Bit 3 Unused TACLR Bit 2 Timer_A clear Setting this bit resets TAR the clock divider and the count direction The TACLR bit is ...

Page 463: ...unt of Timer_A TACCRx Timer_A Capture Compare Register x 15 14 13 12 11 10 9 8 TACCRx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 TACCRx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TACCRx Bits 15 0 Timer_A capture compare register Compare mode TACCRx holds the data for the comparison to the timer value in the Timer_A Register TAR Capture mode The Timer_A Register TAR is copied into the TAC...

Page 464: ...ce specific data sheet for specific signal connections 00 CCIxA 01 CCIxB 10 GND 11 VCC SCS Bit 11 Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture SCCI Bit 10 Synchronized capture compare input The selected CCI input signal is latched with the EQUx signal and can be read via this bit Unused Bit 9 U...

Page 465: ...with software 0 No capture overflow occurred 1 Capture overflow occurred CCIFG Bit 0 Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending TAIV Timer_A Interrupt Vector Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 0 0 0 0 TAIVx 0 r0 r0 r0 r0 r 0 r 0 r 0 r0 TAIVx Bits 15 0 Timer_A Interrupt Vector value TAIV Contents Interrupt Source Int...

Page 466: ...15 24 Timer_A ...

Page 467: ...mer counter with multiple capture compare registers This chapter describes the operation of the Timer_B of the MSP430x4xx device family Topic Page 16 1 Timer_B Introduction 16 2 16 2 Timer_B Operation 16 4 16 3 Timer_B Registers 16 20 Chapter 16 ...

Page 468: ...tputs with PWM capability Double buffered compare latches with synchronized loading Interrupt vector register for fast decoding of all Timer_B interrupts The block diagram of Timer_B is shown in Figure 16 1 Note Use of the Word Count Count is used throughout this chapter It means the counter must be in the process of counting for the action to take place If a particular value is directly written t...

Page 469: ...unt Mode 16 bit Timer TBR Set TBIFG 15 0 MCx IDx Clear TBCLR Timer Clock CCR0 EQU0 Timer Clock Timer Clock VCC TBR 0 UP DOWN EQU0 CLLDx CNTLx Load CCR1 CCR2 CCR3 CCR4 CCR5 Timer Block TBCCR6 RC 10 12 16 8 TBCLGRPx CCR5 CCR4 CCR1 Group Load Logic Group Load Logic TBSSELx 00 01 10 11 GND VCC CCI6A CCI6B 00 01 10 11 CCISx 00 01 10 11 00 01 10 11 CAP 1 0 SCS 1 0 Set TBCCR6 CCIFG Compare Latch TBCL6 AC...

Page 470: ...rating conditions When the timer clock is asynchronous to the CPU clock any read from TBR should occur while the timer is not operating or the results may be unpredictable Alternatively the timer may be read multiple times while operating and a majority vote taken in software to determine the correct reading Any write to TBR will take effect immediately TBR Length Timer_B is configurable to operat...

Page 471: ...arts incrementing in the up direction from zero 16 2 3 Timer Mode Control The timer has four modes of operation as described in Table 16 1 stop up continuous and up down The operating mode is selected with the MCx bits Table 16 1 Timer Modes MCx Mode Description 00 Stop The timer is halted 01 Up The timer repeatedly counts from zero to the value of compare register TBCL0 10 Continuous The timer re...

Page 472: ...R0 CCIFG interrupt flag is set when the timer counts to the TBCL0 value The TBIFG interrupt flag is set when the timer counts from TBCL0 to zero Figure 15 3 shows the flag set cycle Figure 16 3 Up Mode Flag Setting TBCL0 1 TBCL0 0h Timer Clock Timer Set TBIFG Set TBCCR0 CCIFG 1h TBCL0 1 TBCL0 0h Changing the Period Register TBCL0 When changing TBCL0 while the timer is running and when the TBCL0 lo...

Page 473: ...16 4 The compare latch TBCL0 works the same way as the other capture compare registers Figure 16 4 Continuous Mode 0h TBR max The TBIFG interrupt flag is set when the timer counts from TBR max to zero Figure 16 5 shows the flag set cycle Figure 16 5 Continuous Mode Flag Setting TBR max 1 TBR max 0h Timer Clock Timer Set TBIFG 1h TBR max 0h TBR max 1 ...

Page 474: ...om interrupt latency Up to three Timer_B3 or 7 Timer_B7 independent time intervals or output frequencies can be generated using capture compare registers Figure 16 6 Continuous Mode Time Intervals 0h EQU0 Interrupt TBCL0a TBCL0b TBCL0c TBCL0d t1 t0 t0 TBCL1a TBCL1b TBCL1c TBCL1d t1 t1 t0 EQU1 Interrupt TBR max Time intervals can be produced with other modes as well where TBCL0 is used as the perio...

Page 475: ... latched This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped If this is not desired the TBCLR bit must be used to clear the direction The TBCLR bit also clears the TBR value and the clock divider In up down mode the TBCCR0 CCIFG interrupt flag and the TBIFG interrupt flag are set only once during the period separated by 1 2 the timer p...

Page 476: ...the current count value when TBCL0 is loaded the timer begins counting down However one additional count may occur before the counter begins counting down Use of the Up Down Mode The up down mode supports applications that require dead times between output signals see section Timer_B Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state ...

Page 477: ... TBCCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit MSP430x4xx family devices may have different signals connected to CCIxA and CCIxB Refer to the device specific datasheet for the connections of these signals The capture signal can be asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capt...

Page 478: ...t for capture on both edges Software then sets bit CCIS1 1 and toggles bit CCIS0 to switch the capture signal between VCC and GND initiating a capture each time CCIS0 changes state MOV CAP SCS CCIS1 CM_3 TBCCTLx Setup TBCCTLx XOR CCIS0 TBCCTLx TBCCTLx TBR Compare Mode The compare mode is selected when CAP 0 Compare mode is used to generate PWM output signals or interrupts at specific time interval...

Page 479: ... mode 11 New data is transferred from TBCCRx to TBCLx when TBR counts to the old TBCLx value Grouping Compare Latches Multiple compare latches may be grouped together for simultaneous updates with the TBCLGRPx bits When using groups the CLLDx bits of the lowest numbered TBCCRx in the group determine the load event for each compare latch of the group except when TBCLGRP 3 as shown in Table 16 3 The...

Page 480: ...OUTx is defined by the OUTx bit The OUTx signal updates immediately when OUTx is updated 001 Set The output is set when the timer counts to the TBCLx value It remains set until a reset of the timer or until another output mode is selected and affects the output 010 Toggle Reset The output is toggled when the timer counts to the TBCLx value It is reset when the timer counts to the TBCL0 value 011 S...

Page 481: ...nding on the output mode An example is shown in Figure 16 12 using TBCL0 and TBCL1 Figure 16 12 Output Example Timer in Up Mode 0h TBR max EQU0 TBIFG Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TBCL0 TBCL1 EQU1 EQU0 TBIFG EQU1 EQU0 TBIFG Interrupt Events ...

Page 482: ...on the output mode An example is shown in Figure 16 13 using TBCL0 and TBCL1 Figure 16 13 Output Example Timer in Continuous Mode 0h TBR max TBIFG Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TBCL0 TBCL1 EQU1 TBIFG EQU1 EQU0 Interrupt Events EQU0 ...

Page 483: ...Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set TBCL0 TBCL3 EQU3 TBIFG Interrupt Events EQU3 EQU0 EQU3 EQU3 EQU0 Note Switching Between Output Modes When switching between output modes one of the OUTMODx bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decodes o...

Page 484: ... POR CAP EQU0 Capture IRACC Interrupt Request Accepted CCIE TBIV Interrupt Vector Generator The TBIFG flag and TBCCRx CCIFG flags excluding TBCCR0 CCIFG are prioritized and combined to source a single interrupt vector The interrupt vector register TBIV is used to determine which flag requested an interrupt The highest priority enabled interrupt excluding TBCCR0 CCIFG generates a number in the TBIV...

Page 485: ...owing software example shows the recommended use of TBIV for Timer_B3 Interrupt handler for TBCCR0 CCIFG Cycles CCIFG_0_HND Start of handler Interrupt latency 6 RETI 5 Interrupt handler for TBIFG TBCCR1 and TBCCR2 CCIFG TB_HND Interrupt latency 6 ADD TBIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP CCIFG_1_HND Vector 2 Module 1 2 JMP CCIFG_2_HND Vector 4 Module 2 2 RETI Vector 6...

Page 486: ...with POR Timer_B capture compare control 2 TBCCTL2 Read write 0186h Reset with POR Timer_B capture compare 2 TBCCR2 Read write 0196h Reset with POR Timer_B capture compare control 3 TBCCTL3 Read write 0188h Reset with POR Timer_B capture compare 3 TBCCR3 Read write 0198h Reset with POR Timer_B capture compare control 4 TBCCTL4 Read write 018Ah Reset with POR Timer_B capture compare 4 TBCCR4 Read w...

Page 487: ...4 TBCL5 TBCL6 TBCCR4 CLLDx bits control the update TBCL0 independent 11 TBCL0 TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 TBCCR1 CLLDx bits control the update CNTLx Bits 12 11 Counter Length 00 16 bit TBR max 0FFFFh 01 12 bit TBR max 0FFFh 10 10 bit TBR max 03FFh 11 8 bit TBR max 0FFh Unused Bit 10 Unused TBSSELx Bits 9 8 Timer_B clock source select 00 TBCLK 01 ACLK 10 SMCLK 11 Inverted TBCLK IDx Bits 7 6...

Page 488: ... Bit 1 Timer_B interrupt enable This bit enables the TBIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TBIFG Bit 0 Timer_B interrupt flag 0 No interrupt pending 1 Interrupt pending TBR Timer_B Register 15 14 13 12 11 10 9 8 TBRx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 TBRx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TBRx Bits 15 0 Timer_B register The TBR register is the...

Page 489: ...rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TBCCRx Bits 15 0 Timer_B capture compare register Compare mode Compare data is written to each TBCCRx and automatically transferred to TBCLx TBCLx holds the data for the comparison to the timer value in the Timer_B Register TBR Capture mode The Timer_B Register TBR is copied into the TBCCRx register when a capture is performed ...

Page 490: ...A 01 CCIxB 10 GND 11 VCC SCS Bit 11 Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture CLLDx Bit 10 9 Compare latch load These bits select the compare latch load event 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBCLx loads when TBR counts to 0 up or continuous mode TBCLx...

Page 491: ...put The selected input signal can be read by this bit OUT Bit 2 Output For output mode 0 this bit directly controls the state of the output 0 Output low 1 Output high COV Bit 1 Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred CCIFG Bit 0 Capture compare interrupt flag 0 No interrupt pending 1 ...

Page 492: ...ts 15 0 Timer_B interrupt vector value TBIV Contents Interrupt Source Interrupt Flag Interrupt Priority 00h No interrupt pending 02h Capture compare 1 TBCCR1 CCIFG Highest 04h Capture compare 2 TBCCR2 CCIFG 06h Capture compare 3 TBCCR3 CCIFG 08h Capture compare 4 TBCCR4 CCIFG 0Ah Capture compare 5 TBCCR5 CCIFG 0Ch Capture compare 6 TBCCR6 CCIFG 0Eh Timer overflow TBIFG Lowest MSP430x4xx devices on...

Page 493: ...le This chapter discusses the operation of the asynchronous UART mode USART0 is implemented on the MSP430x42x and MSP430x43x devices In addition to USART0 the MSP430x44x devices implement a second identical USART module USART1 USART1 is also implemented in MSP430FG461x devices Topic Page 17 1 USART Introduction UART Mode 17 2 17 2 USART Operation UART Mode 17 4 17 3 USART Registers UART Mode 17 21...

Page 494: ...ndependent transmit and receive shift registers Separate transmit and receive buffer registers LSB first data transmit and receive Built in idle line and address bit communication protocols for multiprocessor systems Receiver start edge detection for auto wake up from LPMx modes Programmable baud rate with modulation for fractional baud rate support Status flags for error detection and suppression...

Page 495: ...larity Receive Status SYNC CKPH CKPL SSEL1 SSEL0 UCLKI ACLK SMCLK SMCLK 00 01 10 11 OE PE BRK TXWAKE UCLKS UCLKI Receive Control RXERR FE SWRST URXEx URXEIE URXWIE Transmit Control SWRST UTXEx TXEPT RXWAKE SPB CHAR PENA PEV SPB CHAR PENA PEV WUT UTXD URXD SOMI STE Prescaler Divider UxBRx Modulator UxMCTL Baud Rate Generator UTXIFGx Refer to the device specific datasheet for SFR locations SYNC URXI...

Page 496: ... chapter USART Module I2C mode for USART0 when reconfiguring from I2C mode to UART mode Note Initializing or Re Configuring the USART Module The required USART initialization re configuration process is 1 Set SWRST BIS B SWRST UxCTL 2 Initialize all USART registers with SWRST 1 including UxCTL 3 Enable USART module via the MEx SFRs URXEx and or UTXEx 4 Clear SWRST via software BIC B SWRST UxCTL 5 ...

Page 497: ...ous ones marks are received after the first stop bit of a character When two stop bits are used for the idle line the second stop bit is counted as the first mark bit of the idle period The first character received after an idle period is an address character The RXWAKE bit is used as an address tag for each block of characters In the idle line multiprocessor format this bit is set when a received...

Page 498: ...flag double buffered with the user accessible TXWAKE bit When the transmitter is loaded from UxTXBUF WUT is also loaded from TXWAKE resetting the TXWAKE bit The following procedure sends out an idle frame to indicate an address character will follow 1 Set TXWAKE then write any character to UxTXBUF UxTXBUF must be ready for new data UTXIFGx 1 The TXWAKE value is shifted to WUT and the contents of U...

Page 499: ...cter to UxRXBUF and set URXIFGx All applicable error status flags are also set If an address is received user software must reset URXWIE to continue receiving data If URXWIE remains set only address characters address bit 1 will be received The URXWIE bit is not modified by the USART hardware automatically Figure 17 4 Address Bit Multiprocessor Format ST Address SP ST Data SP ST Data SP Blocks of ...

Page 500: ...Framing error A framing error occurs when a low stop bit is detected When two stop bits are used only the first stop bit is checked for framing error When a framing error is detected the FE bit is set Parity error A parity error is a mismatch between the number of 1s in a character and the value of the parity bit When an address bit is included in the character it is included in the parity calcula...

Page 501: ...he RX shift register after the character is received Figure 17 5 State Diagram of Receiver Enable Idle State Receiver Enabled Receive Disable Receiver Collects Character URXEx 0 No Valid Start Bit Not Completed URXEx 1 URXEx 0 URXEx 1 Valid Start Bit Handle Interrupt Conditions Character Received URXEx 1 URXEx 0 Note Re Enabling the Receiver Setting URXEx UART Mode When the receiver is disabled UR...

Page 502: ... 0 No Data Written to Transmit Buffer Not Completed UTXEx 1 UTXEx 0 UTXEx 1 Data Written to Transmit Buffer Handle Interrupt Conditions Character Transmitted UTXEx 1 UTXEx 0 And Last Buffer Entry Is Transmitted When the transmitter is enabled UTXEx 1 data should not be written to UxTXBUF unless it is ready for new data indicated by UTXIFGx 1 Violation can result in an erroneous transmission if dat...

Page 503: ...CLK 8 8 UCLKI ACLK SMCLK SMCLK 11 BITCLK 10 01 00 20 27 28 215 Compare 0 or 1 Modulation Data Shift Register LSB first 16 Bit Counter Q0 Q15 m0 m7 8 UxBR1 UxBR0 Toggle FF N R R R UxMCTL 0 or 1 SSEL1 SSEL0 Timing for each bit is shown in Figure 17 8 For each bit received a majority vote is taken to determine the bit value These samples occur at the N 2 1 N 2 and N 2 1 BRCLK periods where N is the n...

Page 504: ...CLK can be adjusted from bit to bit with the modulator to meet timing requirements when a non integer divisor is needed Timing of each bit is expanded by one BRCLK clock cycle if the modulator bit mi is set Each time a bit is received or transmitted the next bit in the modulation control register determines the timing for that bit A set modulation bit increases the division factor by one while a c...

Page 505: ...ce the ideal division factor is 13 65 UxMCTL 6Bh m7 0 m6 1 m5 1 m4 0 m3 1 m2 0 m1 1 and m0 1 The LSB of UxMCTL is used first Start bit Error ǒbaud rate BRCLK 0 1 UxBR 1 1Ǔ 100 2 54 Data bit D0 Error ǒbaud rate BRCLK 1 1 UxBR 2 2Ǔ 100 5 08 Data bit D1 Error ǒbaud rate BRCLK 2 1 UxBR 2 3Ǔ 100 0 29 Data bit D2 Error ǒbaud rate BRCLK 3 1 UxBR 3 4Ǔ 100 2 83 Data bit D3 Error ǒbaud rate BRCLK 4 1 UxBR 3...

Page 506: ...tion Error 0 5x BRCLK Int UxBR 2 m0 Int 13 2 1 6 1 7 Majority Vote Taken Majority Vote Taken UxBR m1 13 1 14 UxBR m2 13 0 13 Majority Vote Taken BRCLK URXDx URXDS tactual Sample URXDS The ideal start bit timing tideal 0 is half the baud rate timing tbaud rate because the bit is tested in the middle of its period The ideal baud rate timing tideal i for the remaining character bits is the baud rate ...

Page 507: ... bit D3 Error ǒbaud rate BRCLK 2x 1 6 4 UxBR 2 1 4Ǔ 100 1 95 Data bit D4 Error ǒbaud rate BRCLK 2x 1 6 5 UxBR 3 1 5Ǔ 100 0 59 Data bit D5 Error ǒbaud rate BRCLK 2x 1 6 6 UxBR 4 1 6Ǔ 100 3 13 Data bit D6 Error ǒbaud rate BRCLK 2x 1 6 7 UxBR 4 1 7Ǔ 100 1 66 Data bit D7 Error ǒbaud rate BRCLK 2x 1 6 8 UxBR 5 1 8Ǔ 100 0 88 Parity bit Error ǒbaud rate BRCLK 2x 1 6 9 UxBR 6 1 9Ǔ 100 3 42 Stop bit 1 Erro...

Page 508: ...r versus the ideal time of the bit period Table 17 2 Commonly Used Baud Rates Baud Rate Data and Errors Divide by A BRCLK 32 768 Hz B BRCLK 1 048 576 Hz Baud Rate A B UxBR1 UxBR0 UxMCTL Max TX Error Max RX Error Synchr RX Error UxBR1 UxBR0 UxMCTL Max TX Error Max RX Error 1200 27 31 873 81 0 1B 03 4 3 4 3 2 03 69 FF 0 0 3 2 2400 13 65 436 91 0 0D 6B 6 3 6 3 4 01 B4 FF 0 0 3 2 4800 6 83 218 45 0 06...

Page 509: ...other character An interrupt request is generated if UTXIEx and GIE are also set UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF UTXIFGx is set after a PUC or when SWRST 1 UTXIEx is reset after a PUC or when SWRST 1 The operation is shown is Figure 17 10 Figure 17 10 Transmit Interrupt Operation Clear UTXIEx Clear D Character Moved From B...

Page 510: ...t Operation Clear URXS Clear τ S SYNC Valid Start Bit Receiver Collects Character URXSE From URXD PE FE BRK URXEIE URXWIE RXWAKE Erroneous Character Rejection Non Address Character Rejection Character Received or Break Detected URXIFGx URXIEx Interrupt Service Requested SWRST PUC UxRXBUF Read URXSE IRQA S URXEIE is used to enable or disable erroneous characters from setting URXIFGx When using mult...

Page 511: ...e mode or to a low power mode where the source is active If the ISR returns to a low power mode where the BRCLK source is inactive the character will not be received Toggling URXSE clears the URXS signal and re enables the start edge detect feature for future characters See chapter System Resets Interrupts and Operating Modes for information on entering and exiting low power modes The now active B...

Page 512: ... Suppression USART Receive Not Started URXDx URXS tτ When a glitch is longer than tτ or a valid start bit occurs on URXDx the USART receive operation is started and a majority vote is taken as shown in Figure 17 13 If the majority vote fails to detect a start bit the USART halts character reception If character reception is halted an active BRCLK is not necessary A time out period longer than the ...

Page 513: ...rupt enable register 1 IE1 Read write 000h 000h with PUC SFR interrupt flag register 1 IFG1 Read write 002h 082h with PUC Table 17 4 USART1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h with PUC Transmit control register U1TCTL Read write 079h 001h with PUC Receive control register U1RCTL Read write 07Ah 000h ...

Page 514: ...rity 1 Even parity SPB Bit 5 Stop bit select Number of stop bits transmitted The receiver always checks for one stop bit 0 One stop bit 1 Two stop bits CHAR Bit 4 Character length Selects 7 bit or 8 bit character length 0 7 bit data 1 8 bit data LISTEN Bit 3 Listen enable The LISTEN bit selects loopback mode 0 Disabled 1 Enabled UTXDx is internally fed back to the receiver SYNC Bit 2 Synchronous m...

Page 515: ...K SSELx Bits 5 4 Source select These bits select the BRCLK source clock 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK URXSE Bit 3 UART receive start edge The bit enables the UART receive start edge feature 0 Disabled 1 Enabled TXWAKE Bit 2 Transmitter wake 0 Next frame transmitted is data 1 Next frame transmitted is an address Unused Bit 1 Unused TXEPT Bit 0 Transmitter empty flag 0 UART is transmitting data...

Page 516: ...condition occurred URXEIE Bit 3 Receive erroneous character interrupt enable 0 Erroneous characters rejected and URXIFGx is not set 1 Erroneous characters received will set URXIFGx URXWIE Bit 2 Receive wake up interrupt enable This bit enables URXIFGx to be set when an address character is received When URXEIE 0 an address character will not set URXIFGx if it is received with errors 0 All received...

Page 517: ...ol Register 1 7 6 5 4 3 2 1 0 215 214 213 212 211 210 29 28 rw rw rw rw rw rw rw rw UxBRx The valid baud rate control range is 3 UxBR 0FFFFh where UxBR UxBR1 UxBR0 Unpredictable receive and transmit timing occurs if UxBR 3 UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0 m7 m6 m5 m4 m3 m2 m1 m0 rw rw rw rw rw rw rw rw UxMCTLx Bits 7 0 Modulation bits These bits select the modulation for BR...

Page 518: ...xRXBUF resets the receive error bits the RXWAKE bit and URXIFGx In 7 bit data mode UxRXBUF is LSB justified and the MSB is always reset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw UxTXBUFx Bits 7 0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted on UTXDx Wr...

Page 519: ... Module enabled Bits 5 0 These bits may be used by other modules See device specific data sheet ME2 Module Enable Register 2 7 6 5 4 3 2 1 0 UTXE1 URXE1 rw 0 rw 0 Bits 7 6 These bits may be used by other modules See device specific data sheet UTXE1 Bit 5 USART1 transmit enable This bit enables the transmitter for USART1 0 Module not enabled 1 Module enabled URXE1 Bit 4 USART1 receive enable This b...

Page 520: ...terrupt enabled Bits 5 0 These bits may be used by other modules See device specific data sheet IE2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 UTXIE1 URXIE1 rw 0 rw 0 Bits 7 6 These bits may be used by other modules See device specific data sheet UTXIE1 Bit 5 USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIE1 Bit 4 USART1 rec...

Page 521: ...nterrupt pending Bits 5 0 These bits may be used by other modules See device specific data sheet IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UTXIFG1 URXIFG1 rw 1 rw 0 Bits 7 6 These bits may be used by other modules See device specific data sheet UTXIFG1 Bit 5 USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF empty 0 No interrupt pending 1 Interrupt pending URXIFG1 Bit 4 USART1 receive...

Page 522: ...17 30 USART Peripheral Interface UART Mode ...

Page 523: ...apter discusses the operation of the synchronous peripheral interface or SPI mode USART0 is implemented on the MSP430x42x and MSP430x43x devices In addition to USART0 the MSP430x44x devices implement a second identical USART module USART1 USART1 is also implemented in MSP430FG461x devices Topic Page 18 1 USART Introduction SPI Mode 18 2 18 2 USART Operation SPI Mode 18 4 18 3 USART Registers SPI M...

Page 524: ...n the SYNC bit is set and the I2C bit is cleared SPI mode features include 7 or 8 bit data length 3 pin and 4 pin SPI operation Master or slave modes Independent transmit and receive shift registers Separate transmit and receive buffer registers Selectable UCLK polarity and phase control Programmable UCLK frequency in master mode Independent interrupt capability for receive and transmit Figure 18 ...

Page 525: ...rity Receive Status SYNC CKPH CKPL SSEL1 SSEL0 UCLKI ACLK SMCLK SMCLK 00 01 10 11 OE PE BRK TXWAKE UCLKS UCLKI Receive Control RXERR FE SWRST USPIEx URXEIE URXWIE Transmit Control SWRST USPIEx TXEPT RXWAKE SPB CHAR PENA PEV SPB CHAR PENA PEV WUT SIMO UTXD URXD SOMI STE Prescaler Divider UxBRx Modulator UxMCTL Baud Rate Generator UTXIFGx Refer to the device specific datasheet for SFR locations SYNC...

Page 526: ...ow SIMO and UCLK are set to the input direction 4 pin slave mode When STE is high RX TX operation of the slave is disabled and SOMI is forced to the input direction When STE is low RX TX operation of the slave is enabled and SOMI operates normally 18 2 1 USART Initialization and Reset The USART is reset by a PUC or by the SWRST bit After a PUC the SWRST bit is automatically set keeping the USART i...

Page 527: ...aracter is received the receive data is moved from the RX shift register to the received data buffer UxRXBUF and the receive interrupt flag URXIFGx is set indicating the RX TX operation is complete A set transmit interrupt flag UTXIFGx indicates that data has moved from UxTXBUF to the TX shift register and UxTXBUF is ready for new data It does not indicate RX TX completion In master mode the compl...

Page 528: ...to the TX shift register before the start of UCLK is transmitted on SOMI Data on SIMO is shifted into the receive shift register on the opposite edge of UCLK and moved to UxRXBUF when the set number of bits are received When data is moved from the RX shift register to UxRXBUF the URXIFGx interrupt flag is set indicating that data has been received The overrun error bit OE is set when the previousl...

Page 529: ...e BRCLK source is active Figure 18 4 and Figure 18 5 show the transmit enable state diagrams Figure 18 4 Master Mode Transmit Enable Idle State Transmitter Enabled Transmit Disable Transmission Active USPIEx 0 No Data Written to Transfer Buffer Not Completed USPIEx 1 USPIEx 0 USPIEx 1 Data Written to Transmit Buffer Handle Interrupt Conditions Character Transmitted USPIEx 1 USPIEx 0 And Last Buffe...

Page 530: ...abled Receive Disable Receiver Collects Character USPIEx 0 No Data Written to UxTXBUF Not Completed USPIEx 1 USPIEx 0 USPIEx 1 Handle Interrupt Conditions Character Received USPIEx 1 USPIEx 0 SWRST PUC Data Written to UxTXBUF Figure 18 7 SPI Slave Receive Enable State Diagram Idle State Receive Enabled Receive Disable Receiver Collects Character USPIEx 0 No Clock at UCLK Not Completed USPIEx 1 USP...

Page 531: ...r data transfer Figure 18 8 SPI Baud Rate Generator Bit Start mX BRCLK 8 8 UCLKI ACLK SMCLK SMCLK 11 BITCLK 10 01 00 20 27 28 215 Compare 0 or 1 Modulation Data Shift Register LSB first 16 Bit Counter Q0 Q15 m0 m7 8 UxBR1 UxBR0 Toggle FF N R R R UxMCTL SSEL1 SSEL0 The 16 bit value of UxBR0 UxBR1 is the division factor of the USART clock source BRCLK The maximum baud rate that can be generated in m...

Page 532: ... UCLK are independently configured via the CKPL and CKPH control bits of the USART Timing for each case is shown in Figure 18 9 Figure 18 9 USART SPI Timing CKPH CKPL Cycle UCLK UCLK UCLK UCLK SIMO SOMI SIMO SOMI Move to UxTXBUF RX Sample Points 0 1 0 0 0 1 1 1 0 X 1 X MSB MSB 1 2 3 4 5 6 7 8 LSB LSB TX Data Shifted Out STE ...

Page 533: ...e also set UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF UTXIFGx is set after a PUC or when SWRST 1 UTXIEx is reset after a PUC or when SWRST 1 The operation is shown is Figure 18 10 Figure 18 10 Transmit Interrupt Operation Clear UTXIEx Clear D Character Moved From Buffer to Shift Register Interrupt Service Requested SWRST Data moved t...

Page 534: ...nding interrupt is served or when UxRXBUF is read Figure 18 11 Receive Interrupt Operation URXS Clear τ S SYNC Valid Start Bit Receiver Collects Character URXSE From URXD PE FE BRK URXEIE URXWIE RXWAKE Character Received URXIFGx URXIEx Interrupt Service Requested SWRST PUC UxRXBUF Read URXSE IRQA SYNC 1 Clear Figure 18 12 Receive Interrupt State Diagram Receive Character Completed Interrupt Servic...

Page 535: ... enable register 1 IE1 Read write 000h 000h with PUC SFR interrupt flag register 1 IFG1 Read write 002h 082h with PUC Table 18 2 USART1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h with PUC Transmit control register U1TCTL Read write 079h 001h with PUC Receive control register U1RCTL Read write 07Ah 000h with...

Page 536: ... 1 0 SPI mode 1 I2C mode CHAR Bit 4 Character length 0 7 bit data 1 8 bit data LISTEN Bit 3 Listen enable The LISTEN bit selects the loopback mode 0 Disabled 1 Enabled The transmit signal is internally fed back to the receiver SYNC Bit 2 Synchronous mode enable 0 UART mode 1 SPI mode MM Bit 1 Master mode 0 USART is slave 1 USART is master SWRST Bit 0 Software reset enable 0 Disabled USART reset re...

Page 537: ...ock polarity select 0 The inactive state is low 1 The inactive state is high SSELx Bits 5 4 Source select These bits select the BRCLK source clock 00 External UCLK valid for slave mode only 01 ACLK valid for master mode only 10 SMCLK valid for master mode only 11 SMCLK valid for master mode only Unused Bit 3 Unused Unused Bit 2 Unused STC Bit 1 Slave transmit control 0 4 pin SPI mode STE enabled 1...

Page 538: ...TC 0 FE is unused in slave mode 0 No conflict detected 1 A negative edge occurred on STE indicating bus conflict Undefined Bit 6 Unused OE Bit 5 Overrun error flag This bit is set when a character is transferred into UxRXBUF before the previous character was read OE is automatically reset when UxRXBUF is read when SWRST 1 or can be reset by software 0 No error 1 Overrun error occurred Unused Bit 4...

Page 539: ...ter 1 7 6 5 4 3 2 1 0 215 214 213 212 211 210 29 28 rw rw rw rw rw rw rw rw UxBRx The baud rate generator uses the content of UxBR1 UxBR0 to set the baud rate Unpredictable SPI operation occurs if UxBR 2 UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0 m7 m6 m5 m4 m3 m2 m1 m0 rw rw rw rw rw rw rw rw UxMCTLx Bits 7 0 The modulation control register is not used for SPI mode and should be set...

Page 540: ...ading UxRXBUF resets the OE bit and URXIFGx flag In 7 bit data mode UxRXBUF is LSB justified and the MSB is always reset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw UxTXBUFx Bits 7 0 The transmit data buffer is user accessible and contains current data to be transmitted When seven bit character length is used the data should be MSB justifi...

Page 541: ...de for USART0 0 Module not enabled 1 Module enabled Bits 5 0 These bits may be used by other modules See device specific data sheet ME2 Module Enable Register 2 7 6 5 4 3 2 1 0 USPIE1 rw 0 Bits 7 5 These bits may be used by other modules See device specific data sheet USPIE1 Bit 4 USART1 SPI enable This bit enables the SPI mode for USART1 0 Module not enabled 1 Module enabled Bits 3 0 These bits m...

Page 542: ...errupt enabled Bits 5 0 These bits may be used by other modules See device specific data sheet IE2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 UTXIE1 URXIE1 rw 0 rw 0 Bits 7 6 These bits may be used by other modules See device specific data sheet UTXIE1 Bit 5 USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIE1 Bit 4 USART1 rece...

Page 543: ...errupt pending Bits 5 0 These bits may be used by other modules See device specific data sheet IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UTXIFG1 URXIFG1 rw 1 rw 0 Bits 7 6 These bits may be used by other modules See device specific data sheet UTXIFG1 Bit 5 USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF is empty 0 No interrupt pending 1 Interrupt pending URXIFG1 Bit 4 USART1 receiv...

Page 544: ...18 22 USART Peripheral Interface SPI Mode ...

Page 545: ...rial communication interface USCI supports multiple serial communication modes with one hardware module This chapter discusses the operation of the asynchronous UART mode Topic Page 19 1 USCI Overview 19 2 19 2 USCI Introduction UART Mode 19 3 19 3 USCI Operation UART Mode 19 5 19 4 USCI Registers UART Mode 19 27 Chapter 19 ...

Page 546: ...s different from USCI_B etc If more than one identical USCI module is implemented on one device those modules are named with incrementing numbers For example if one device has two USCI_A modules they are named USCI_A0 and USCI_A1 See the device specific data sheet to determine which USCI modules if any are implemented on which devices The USCI_Ax modules support UART mode Pulse shaping for IrDA co...

Page 547: ...Independent transmit and receive shift registers Separate transmit and receive buffer registers LSB first or MSB first data transmit and receive Built in idle line and address bit communication protocols for multiprocessor systems Receiver start edge detection for auto wake up from LPMx modes Programmable baud rate with modulation for fractional baud rate support Status flags for error detection a...

Page 548: ...CPE UCFE UCOE UCABEN Receive Shift Register Receive Buffer UC0RXBUF Receive State Machine 1 0 UCIREN UCPEN UCPAR UCMSB UC7BIT UCDORM UCMODEx 2 UCSPB Set UCBRK Set UCADDR UCIDLE 0 1 UCLISTEN UC0RX 1 0 UCIRRXPL IrDA Decoder UCIRRXFE UCIRRXFLx 6 Transmit Buffer UC0TXBUF Transmit State Machine UCTXADDR UCTXBRK Transmit Shift Register UCPEN UCPAR UCMSB UC7BIT UCIREN UCIRTXPLx 6 0 1 IrDA Encoder UC0TX T...

Page 549: ...ST releases the USCI for operation Note Initializing or Re Configuring the USCI Module The recommended USCI initialization re configuration process is 1 Set UCSWRST BIS B UCSWRST UCAxCTL1 2 Initialize all USCI registers with UCSWRST 1 including UCAxCTL1 3 Configure ports 4 Clear UCSWRST via software BIC B UCSWRST UCAxCTL1 5 Enable interrupts optional via UCAxRXIE and or UCAxTXIE 19 3 2 Character F...

Page 550: ...ntinuous ones marks are received after the one or two stop bits of a character The baud rate generator is switched off after reception of an idle line until the next start edge is detected When an idle line is detected the UCIDLE bit is set The first character received after an idle period is an address character The UCIDLE bit is used as an address tag for each block of characters In idle line mu...

Page 551: ...ss transmission in idle line multiprocessor format a precise idle period can be generated by the USCI to generate address character identifiers on UCAxTXD The double buffered UCTXADDR flag indicates if the next character loaded into UCAxTXBUF is preceded by an idle line of 11 bits UCTXADDR is automatically cleared when the start bit is generated Transmitting an Idle Frame The following procedure s...

Page 552: ...CAxRXIFG is set and any applicable error flag is set when UCRXEIE 1 When UCRXEIE 0 and a character containing a set address bit is received but has a framing error or parity error the character is not transferred into UCAxRXBUF and UCAxRXIFG is not set If an address is received user software can validate the address and must reset UCDORM to continue receiving data If UCDORM remains set only addres...

Page 553: ...nd Generation When UCMODEx 00 01 or 10 the receiver detects a break when all data parity and stop bits are low regardless of the parity address mode or other character settings When a break is detected the UCBRK bit is set If the break interrupt enable bit UCBRKIE is set the receive interrupt flag UCAxRXIFG will also be set In this case the value in UCAxRXBUF is 0h since all data bits were zero To...

Page 554: ...n the first falling edge and the last falling edge of the pattern The transmit baud rate generator is used for the measurement if automatic baud rate detection is enabled by setting UCABDEN Otherwise the pattern is received but not measured The result of the measurement is transferred into the baud rate control registers UCAxBR0 UCAxBR1 and UCAxMCTL If the length of the synch field exceeds the mea...

Page 555: ... a full duplex communication system with some restrictions The USCI can not transmit data while receiving the break sync field and if a 0h byte with framing error is received any data transmitted during this time gets corrupted The latter case can be discovered by checking the received data and the UCFE bit Transmitting a Break Synch Field The following procedure transmits a break synch field 1 Se...

Page 556: ... selected with UCIRTXCLK 1 and the pulse length is set to 6 half clock cycles with UCIRTXPLx 6 1 5 When UCIRTXCLK 0 the pulse length tPULSE is based on BRCLK and is calculated as follows UCIRTXPLx tPULSE 2 fBRCLK 1 When the pulse length is based on BRCLK the prescaler UCBRx must to be set to a value greater or equal to 5 IrDA Decoding The decoder detects high pulses when UCIRRXPL 0 Otherwise it de...

Page 557: ...ming error is detected the UCFE bit is set Parity error UCPE A parity error is a mismatch between the number of 1s in a character and the value of the parity bit When an address bit is included in the character it is included in the parity calculation When a parity error is detected the UCPE bit is set Receive overrun UCOE An overrun error occurs when a character is loaded into UCAxRXBUF before th...

Page 558: ...etected a character will be received When the idle line multiprocessor mode is selected with UCMODEx 01 the UART state machine checks for an idle line after receiving a character If a start bit is detected another character is received Otherwise the UCIDLE flag is set after 10 ones are received and the UART state machine returns to its idle state and the baud rate generator is turned off Receive D...

Page 559: ...ud Rate Generation The USCI baud rate generator is capable of producing standard baud rates from non standard source frequencies It provides two modes of operation selected by the UCOS16 bit Low Frequency Baud Rate Generation The low frequency mode is selected when UCOS16 0 This mode allows generation of baud rates from low frequency clock sources e g 9600 baud from a 32768Hz crystal By using a lo...

Page 560: ...2 division Majority Vote m 0 m 1 Modulation is based on the UCBRSx setting as shown in Table 19 2 A 1 in the table indicates that m 1 and the corresponding BITCLK period is one BRCLK period longer than a BITCLK period with m 0 The modulation wraps around after 8 bits but restarts with each new start bit Table 19 2 BITCLK Modulation Pattern UCBRSx Bit 0 Start Bit Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6...

Page 561: ...and BRCLK is equal to BITCLK16 Modulation for BITCLK16 is based on the UCBRFx setting as shown in Table 19 3 A 1 in the table indicates that the corresponding BITCLK16 period is one BRCLK period longer than the periods m 0 The modulation restarts with each new bit timing Modulation for BITCLK is based on the UCBRSx setting as shown in Table 19 2 as previously described Table 19 3 BITCLK16 Modulati...

Page 562: ...s realized by the modulator with the following nominal formula UCBRSx round N INT N 8 Incrementing or decrementing the UCBRSx setting by one count may give a lower maximum bit error for any given bit To determine if this is the case a detailed error calculation must be performed for each bit for each UCBRSx setting Oversampling Baud Rate Mode Setting In the oversampling mode the prescaler is set t...

Page 563: ...bit i from Table 19 2 Oversampling Baud Rate Mode Bit Timing In oversampling baud rate mode calculate the length of bit i Tbit TX i based on the baud rate generator UCBRx UCBRFx and UCBRSx settings Tbit TX i 1 fBRCLK ǒǒ16 mUCBRSx i Ǔ UCBRx ȍ 15 j 0 mUCBRFx j Ǔ where ȍ 15 j 0 mUCBRFx j Sum of ones from the corresponding row in Table 19 3 mUCBRSx i Modulation of bit i from Table 19 2 This results in...

Page 564: ...9 11 Receive Error 1 2 3 4 5 6 0 i t0 tideal 7 8 1 t1 2 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 t0 t1 t2 ST D0 D1 D0 D1 ST Synchronization Error 0 5x BRCLK Majority Vote Taken Majority Vote Taken Majority Vote Taken BRCLK UCAxRXD RXD synch tactual Sample RXD synch The ideal sampling time tbit ideal RX i is in the middle of a bit period tbit ideal RX i 1 Baudrate i 0 5 The r...

Page 565: ...t RX i tbit ideal RX i Ǔ Baudrate 100 19 3 13 Typical Baud Rates and Errors Standard baud rate data for UCBRx UCBRSx and UCBRFx are listed in Table 19 4 and Table 19 5 for a 32 768 Hz crystal sourcing ACLK and typical SMCLK frequencies Please ensure that the selected BRCLK frequency does not exceed the device specific maximum USCI input frequency Please refer to the device specific data sheet The ...

Page 566: ... 56000 17 7 0 4 8 0 8 8 0 3 2 1 000 000 115200 8 6 0 7 8 6 4 9 7 16 1 1 000 000 128000 7 7 0 10 4 6 4 18 0 11 6 1 000 000 256000 3 7 0 29 6 0 43 6 5 2 4 000 000 9600 416 6 0 0 2 0 2 0 2 0 4 4 000 000 19200 208 3 0 0 2 0 5 0 3 0 8 4 000 000 38400 104 1 0 0 5 0 6 0 9 1 2 4 000 000 56000 71 4 0 0 6 1 0 1 7 1 3 4 000 000 115200 34 6 0 2 1 0 6 2 5 3 1 4 000 000 128000 31 2 0 0 8 1 6 3 6 2 0 4 000 000 2...

Page 567: ...CLK Frequency Hz Baud Rate Baud UCBRx UCBRSx UCBRFx Max TX Error Max RX Error 16 000 000 9600 1666 6 0 0 05 0 05 0 05 0 1 16 000 000 19200 833 2 0 0 1 0 05 0 2 0 1 16 000 000 38400 416 6 0 0 2 0 2 0 2 0 4 16 000 000 56000 285 6 0 0 3 0 1 0 5 0 2 16 000 000 115200 138 7 0 0 7 0 0 8 0 6 16 000 000 128000 125 0 0 0 0 0 8 0 16 000 000 256000 62 4 0 0 8 0 1 2 1 2 ...

Page 568: ... 7 3 4 000 000 230400 1 7 0 34 4 0 33 4 0 8 000 000 9600 52 0 1 0 4 0 0 4 0 1 8 000 000 19200 26 0 1 0 0 9 0 1 1 8 000 000 38400 13 0 0 1 8 0 1 9 0 2 8 000 000 57600 8 0 11 0 0 88 0 1 6 8 000 000 115200 4 5 3 3 5 3 2 1 8 6 4 8 000 000 230400 2 3 2 2 1 4 8 2 5 7 3 8 000 000 460800 1 7 0 34 4 0 33 4 0 12 000 000 9600 78 0 2 0 0 0 05 0 05 12 000 000 19200 39 0 1 0 0 0 0 2 12 000 000 38400 19 0 8 1 8 ...

Page 569: ...active 19 3 15 USCI Interrupts The USCI has one interrupt vector for transmission and one interrupt vector for reception USCI Transmit Interrupt Operation The UCAxTXIFG interrupt flag is set by the transmitter to indicate that UCAxTXBUF is ready to accept another character An interrupt request is generated if UCAxTXIE and GIE are also set UCAxTXIFG is automatically reset if a character is written ...

Page 570: ...ndle data receive interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode USCIA0_RX_USCIB0_RX_ISR BIT B UCA0RXIFG IFG2 USCI_A0 Receive Interrupt JNZ USCIA0_RX_ISR USCIB0_RX_ISR Read UCB0RXBUF clears UCB0RXIFG RETI USCIA0_RX_ISR Read UCA0RXBUF clears UCA0RXIFG RETI The following software example shows an extract of an interrupt service routine to handle data transmit interrupts f...

Page 571: ...rite 001h Reset with PUC SFR interrupt flag register 2 IFG2 Read write 003h 00Ah with PUC Note Modifying SFR bits To avoid modifying control bits of other modules it is recommended to set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B or CLR B instructions Table 19 7 USCI_A1 Control and Status Registers Register Short Form Register Type Address Initial State USC...

Page 572: ...CPAR is not used when parity is disabled 0 Odd parity 1 Even parity UCMSB Bit 5 MSB first select Controls the direction of the receive and transmit shift register 0 LSB first 1 MSB first UC7BIT Bit 4 Character length Selects 7 bit or 8 bit character length 0 8 bit data 1 7 bit data UCSPB Bit 3 Stop bit select Number of stop bits 0 One stop bit 1 Two stop bits UCMODEx Bits 2 1 USCI mode The UCMODEx...

Page 573: ...aracters will set UCAxRXIFG 1 Dormant Only characters that are preceded by an idle line or with address bit set will set UCAxRXIFG In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG UCTXADDR Bit 2 Transmit address Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode 0 Next frame transmit...

Page 574: ...xBR0 UCAxBR1 256 forms the prescaler value UCAxMCTL USCI_Ax Modulation Control Register 7 6 5 4 3 2 1 0 UCBRFx UCBRSx UCOS16 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 UCBRFx Bits 7 4 First modulation stage select These bits determine the modulation pattern for BITCLK16 when UCOS16 1 Ignored with UCOS16 0 Table 19 3 shows the modulation pattern UCBRSx Bits 3 1 Second modulation stage select These bit...

Page 575: ...t will not function correctly 0 No error 1 Overrun error occurred UCPE Bit 4 Parity error flag When UCPEN 0 UCPE is read as 0 0 No error 1 Character received with parity error UCBRK Bit 3 Break detect flag 0 No break condition 1 Break condition occurred UCRXERR Bit 2 Receive error flag This bit indicates a character was received with error s When UCRXERR 1 on or more error flags UCFE UCPE UCOE is ...

Page 576: ...XBUF resets the receive error bits the UCADDR or UCIDLE bit and UCAxRXIFG In 7 bit data mode UCAxRXBUF is LSB justified and the MSB is always reset UCAxTXBUF USCI_Ax Transmit Buffer Register 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw UCTXBUFx Bits 7 0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted on UCAxTXD...

Page 577: ... encoder decoder enable 0 IrDA encoder decoder disabled 1 IrDA encoder decoder enabled UCAxIRRCTL USCI_Ax IrDA Receive Control Register 7 6 5 4 3 2 1 0 UCIRRXFLx UCIRRXPL UCIRRXFE rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 UCIRRXFLx Bits 7 2 Receive filter length The minimum pulse length for receive is given by tMIN UCIRRXFLx 4 2 fIRTXCLK UCIRRXPL Bit 1 IrDA receive input UCAxRXD polarity 0 IrDA tran...

Page 578: ...it time 01 2 bit times 10 3 bit times 11 4 bit times UCSTOE Bit 3 Synch field time out error 0 No error 1 Length of synch field exceeded measurable time UCBTOE Bit 2 Break time out error 0 No error 1 Length of break field exceeded 22 bit times Reserved Bit 1 Reserved UCABDEN Bit 0 Automatic baud rate detect enable 0 Baud rate detection disabled Length of break and synch field is not measured 1 Bau...

Page 579: ...IE Bit 0 USCI_A0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UCA0 TXIFG UCA0 RXIFG rw 1 rw 0 Bits 7 2 These bits may be used by other modules see the device specific data sheet UCA0 TXIFG Bit 1 USCI_A0 transmit interrupt flag UCA0TXIFG is set when UCA0TXBUF is empty 0 No interrupt pending 1 Interrupt pending UCA0 RXIFG Bit 0 USCI...

Page 580: ...RXIE Bit 0 USCI_A1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled UC1IFG USCI_A1 Interrupt Flag Register 7 6 5 4 3 2 1 0 Unused Unused Unused Unused UCA1 TXIFG UCA1 RXIFG rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 Unused Bits 7 4 Unused Bits 3 2 These bits may be used by other USCI modules see the device specific data sheet UCA1 TXIFG Bit 1 USCI_A1 transmit interrupt flag UCA1TXIFG is set wh...

Page 581: ...ication interface USCI supports multiple serial communication modes with one hardware module This chapter discusses the operation of the synchronous peripheral interface or SPI mode Topic Page 20 1 USCI Overview 20 2 20 2 USCI Introduction SPI Mode 20 3 20 3 USCI Operation SPI Mode 20 5 20 4 USCI Registers SPI Mode 20 14 Chapter 20 ...

Page 582: ... different from USCI_B etc If more than one identical USCI module is implemented on one device those modules are named with incrementing numbers For example if one device has two USCI_A modules they are named USCI_A0 and USCI_A1 See the device specific data sheet to determine which USCI modules if any are implemented on which devices The USCI_Ax modules support UART mode Pulse shaping for IrDA com...

Page 583: ...th the UCMODEx bits SPI mode features include 7 or 8 bit data length LSB first or MSB first data transmit and receive 3 pin and 4 pin SPI operation Master or slave modes Independent transmit and receive shift registers Separate transmit and receive buffer registers Continuous transmit and receive operation Selectable clock polarity and phase control Programmable clock frequency in master mode Inde...

Page 584: ...Bit Clock Generator UCxBRx 16 Receive Shift Register Receive Buffer UCxRXBUF Receive State Machine UCMSB UC7BIT 1 0 UCMST UCxSOMI Transmit Buffer UCxTXBUF Transmit State Machine Transmit Shift Register UCMSB UC7BIT BRCLK Set UCxRXIFG Set UCxTXIFG 0 1 UCLISTEN Clock Direction Phase and Polarity UCCKPH UCCKPL UCxSIMO UCxCLK Set UCOE Transmit Enable Control 2 UCMODEx UCxSTE Set UCFE ...

Page 585: ...out Master mode UCxSIMO is the data output line Slave mode UCxSIMO is the data input line UCxSOMI Slave out master in Master mode UCxSOMI is the data input line Slave mode UCxSOMI is the data output line UCxCLK USCI SPI clock Master mode UCxCLK is an output Slave mode UCxCLK is an input UCxSTE Slave transmit enable Used in 4 pin mode to allow multiple masters on a single bus Not used in 3 pin mode...

Page 586: ...RST BIS B UCSWRST UCxCTL1 2 Initialize all USCI registers with UCSWRST 1 including UCxCTL1 3 Configure ports 4 Clear UCSWRST via software BIC B UCSWRST UCxCTL1 5 Enable interrupts optional via UCxRXIE and or UCxTXIE 20 3 2 Character Format The USCI module in SPI mode supports 7 and 8 bit character lengths selected by the UC7BIT bit In 7 bit data mode UCxRXBUF is LSB justified and the MSB is always...

Page 587: ...egister when the TX shift register is empty initiating data transfer on UCxSIMO starting with either the most significant or least significant bit depending on the UCMSB setting Data on UCxSOMI is shifted into the receive shift register on the opposite clock edge When the character is received the receive data is moved from the RX shift register to the received data buffer UCxRXBUF and the receive...

Page 588: ... set indicating a communication integrity violation to be handled by the user The internal state machines are reset and the shift operation is aborted If data is written into UCxTXBUF while the master is held inactive by UCxSTE it will be transmit as soon as UCxSTE transitions to the master active state If an active transfer is aborted by UCxSTE transitioning to the master inactive state the data ...

Page 589: ...ed on UCxSOMI Data on UCxSIMO is shifted into the receive shift register on the opposite edge of UCxCLK and moved to UCxRXBUF when the set number of bits are received When data is moved from the RX shift register to UCxRXBUF the UCxRXIFG interrupt flag is set indicating that data has been received The overrun error bit UCOE is set when the previously received data is not read from UCxRXBUF before ...

Page 590: ...ock is provided by the master A transmit or receive operation is indicated by UCBUSY 1 A PUC or set UCSWRST bit disables the USCI immediately and any active transfer is terminated Transmit Enable In master mode writing to UCxTXBUF activates the bit clock generator and the data will begin to transmit In slave mode transmission begins when a master provides a clock and in 4 pin mode when the UCxSTE ...

Page 591: ...lue of UCBRx in the bit rate control registers UCxxBR1 and UCxxBR0 is the division factor of the USCI clock source BRCLK The maximum bit clock that can be generated in master mode is BRCLK Modulation is not used in SPI mode and UCAxMCTL should be cleared when using SPI mode for USCI_A The UCAxCLK UCBxCLK frequency is given by fBitClock fBRCLK UCBRx Serial Clock Polarity and Phase The polarity and ...

Page 592: ...is required because the clock is provided by the external master It is possible to operate the USCI in SPI slave mode while the device is in LPM4 and all clock sources are disabled The receive or transmit interrupt can wake up the CPU from any low power mode 20 3 8 SPI Interrupts The USCI has one interrupt vector for transmission and one interrupt vector for reception SPI Transmit Interrupt Operat...

Page 593: ...dle data receive interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode USCIA0_RX_USCIB0_RX_ISR BIT B UCA0RXIFG IFG2 USCI_A0 Receive Interrupt JNZ USCIA0_RX_ISR USCIB0_RX_ISR Read UCB0RXBUF clears UCB0RXIFG RETI USCIA0_RX_ISR Read UCA0RXBUF clears UCA0RXIFG RETI The following software example shows an extract of an interrupt service routine to handle data transmit interrupts fr...

Page 594: ...Read write 065h Reset with PUC USCI_A0 Receive buffer register UCA0RXBUF Read 066h Reset with PUC USCI_A0 Transmit buffer register UCA0TXBUF Read write 067h Reset with PUC USCI_B0 control register 0 UCB0CTL0 Read write 068h 001h with PUC USCI_B0 control register 1 UCB0CTL1 Read write 069h 001h with PUC USCI_B0 Bit rate control register 0 UCB0BR0 Read write 06Ah Reset with PUC USCI_B0 Bit rate cont...

Page 595: ...rite 0D5h Reset with PUC USCI_A1 Receive buffer register UCA1RXBUF Read 0D6h Reset with PUC USCI_A1 Transmit buffer register UCA1TXBUF Read write 0D7h Reset with PUC USCI_B1 control register 0 UCB1CTL0 Read write 0D8h 001h with PUC USCI_B1 control register 1 UCB1CTL1 Read write 0D9h 001h with PUC USCI_B1 Bit rate control register 0 UCB1BR0 Read write 0DAh Reset with PUC USCI_B1 Bit rate control re...

Page 596: ... polarity select 0 The inactive state is low 1 The inactive state is high UCMSB Bit 5 MSB first select Controls the direction of the receive and transmit shift register 0 LSB first 1 MSB first UC7BIT Bit 4 Character length Selects 7 bit or 8 bit character length 0 8 bit data 1 7 bit data UCMST Bit 3 Master mode select 0 Slave mode 1 Master mode UCMODEx Bits 2 1 USCI Mode The UCMODEx bits select th...

Page 597: ... 0 r0 rw 0 rw 0 rw 0 rw 0 rw 1 UCAxCTL1 USCI_Ax UCBxCTL1 USCI_Bx UCSSELx Bits 7 6 USCI clock source select These bits select the BRCLK source clock in master mode UCxCLK is always used in slave mode 00 NA 01 ACLK 10 SMCLK 11 SMCLK Unused Bits 5 1 Unused in synchronous mode UCSYNC 1 UCSWRST Bit 0 Software reset enable 0 Disabled USCI reset released for operation 1 Enabled USCI logic held in reset s...

Page 598: ...USCI_Bx Bit Rate Control Register 0 7 6 5 4 3 2 1 0 UCBRx low byte rw rw rw rw rw rw rw rw UCAxBR1 USCI_Ax Bit Rate Control Register 1 UCBxBR1 USCI_Bx Bit Rate Control Register 1 7 6 5 4 3 2 1 0 UCBRx high byte rw rw rw rw rw rw rw rw UCBRx Bit clock prescaler setting The 16 bit value of UCxxBR0 UCxxBR1 256 form the prescaler value ...

Page 599: ... 6 Framing error flag This bit indicates a bus conflict in 4 wire master mode UCFE is not used in 3 wire master or any slave mode 0 No error 1 Bus conflict occurred UCOE Bit 5 Overrun error flag This bit is set when a character is transferred into UCxRXBUF before the previous character was read UCOE is cleared automatically when UCxRXBUF is read and must not be cleared by software Otherwise it wil...

Page 600: ...ister Reading UCxRXBUF resets the receive error bits and UCxRXIFG In 7 bit data mode UCxRXBUF is LSB justified and the MSB is always reset UCAxTXBUF USCI_Ax Transmit Buffer Register UCBxTXBUF USCI_Bx Transmit Buffer Register 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw UCTXBUFx Bits 7 0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift r...

Page 601: ... used by other modules See device specific data sheet UCB0TXIE Bit 3 USCI_B0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCB0RXIE Bit 2 USCI_B0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCA0TXIE Bit 1 USCI_A0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCA0RXIE Bit 0 USCI_A0 receive interrupt enable 0 Interrupt disabled 1 Interr...

Page 602: ...0TXIFG is set when UCB0TXBUF is empty 0 No interrupt pending 1 Interrupt pending UCB0 RXIFG Bit 2 USCI_B0 receive interrupt flag UCB0RXIFG is set when UCB0RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending UCA0 TXIFG Bit 1 USCI_A0 transmit interrupt flag UCA0TXIFG is set when UCA0TXBUF empty 0 No interrupt pending 1 Interrupt pending UCA0 RXIFG Bit 0 USCI_A0 receive...

Page 603: ...rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Bits 7 4 Unused UCB1TXIE Bit 3 USCI_B1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCB1RXIE Bit 2 USCI_B1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCA1TXIE Bit 1 USCI_A1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCA1RXIE Bit 0 USCI_A1 receive interrupt enable 0 Interrupt disabled 1 In...

Page 604: ... UCB1TXIFG is set when UCB1TXBUF is empty 0 No interrupt pending 1 Interrupt pending UCB1 RXIFG Bit 2 USCI_B1 receive interrupt flag UCB1RXIFG is set when UCB1RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending UCA1 TXIFG Bit 1 USCI_A1 transmit interrupt flag UCA1TXIFG is set when UCA1TXBUF empty 0 No interrupt pending 1 Interrupt pending UCA1 RXIFG Bit 0 USCI_A1 rec...

Page 605: ...rsal serial communication interface USCI supports multiple serial communication modes with one hardware module This chapter discusses the operation of the I2C mode Topic Page 21 1 USCI Overview 21 2 21 2 USCI Introduction I2C Mode 21 3 21 3 USCI Operation I2C Mode 21 5 21 4 USCI Registers I2C Mode 21 25 Chapter 21 ...

Page 606: ... different from USCI_B etc If more than one identical USCI module is implemented on one device those modules are named with incrementing numbers For example if one device has two USCI_A modules they are named USCI_A0 and USCI_A1 See the device specific data sheet to determine which USCI modules if any are implemented on which devices The USCI_Ax modules support UART mode Pulse shaping for IrDA com...

Page 607: ...module through the 2 wire I2C interface The I2C mode features include Compliance to the Philips Semiconductor I2C specification v2 1 J 7 bit and 10 bit device addressing modes J General call J START RESTART STOP J Multi master transmitter receiver mode J Slave receiver transmitter mode J Standard mode up to 100 kbps and fast mode up to 400 kbps support Programmable UCxCLK frequency in master mode ...

Page 608: ...Diagram I2C Mode ACLK SMCLK SMCLK 00 01 10 11 UCSSELx UC1CLK Prescaler Divider Bit Clock Generator UCxBRx 16 BRCLK Slave Address UC1SA Transmit Shift Register UCMST Transmit Buffer UC1TXBUF I2C State Machine Own Address UC1OA Receive Shift Register UCA10 Receive Buffer UC1RXBUF UCGCEN UCxSDA UCxSCL UCSLA10 ...

Page 609: ...master or the slave when performing data transfers A master initiates a data transfer and generates the clock signal SCL Any device addressed by a master is considered a slave I2C data is communicated using the serial data pin SDA and the serial clock pin SCL Both SDA and SCL are bidirectional and must be connected to a positive supply voltage using a pullup resistor Figure 21 2 I2C Bus Connection...

Page 610: ...USCI module should be done when UCSWRST is set to avoid unpredictable behavior Setting UCSWRST in I2C mode has the following effects I2C communication stops SDA and SCL are high impedance UCBxI2CSTAT bits 6 0 are cleared UCBxTXIE and UCBxRXIE are cleared UCBxTXIFG and UCBxRXIFG are cleared All other bits and registers remain unchanged Note Initializing or Reconfiguring the USCI Module The recommen...

Page 611: ...dule Data Transfer SDA SCL MSB Acknowledgement Signal From Receiver Acknowledgement Signal From Receiver 1 2 7 8 9 1 2 8 9 ACK ACK START Condition S STOP Condition P R W START and STOP conditions are generated by the master and are shown in Figure 21 3 A START condition is a high to low transition on the SDA line while SCL is high A STOP condition is a low to high transition on the SDA line while ...

Page 612: ... sent from the receiver after each byte The next byte is the remaining 8 bits of the 10 bit slave address followed by the ACK bit and the 8 bit data Figure 21 6 I2C Module 10 Bit Addressing Format S 1 Slave Address 1st byte 7 Slave Address 2nd byte ACK R W 1 1 8 ACK 1 Data 8 ACK 1 P 1 1 1 1 1 0 X X Repeated Start Conditions The direction of data flow on SDA can be changed by the master without fir...

Page 613: ...sented by grey rectangles data transmitted by the slave by white rectangles Data transmitted by the USCI module either as master or slave is shown by rectangles that are taller than the others Actions taken by the USCI module are shown in grey rectangles with an arrow indicating where in the the data stream the action occurs Actions that must be handled with software are indicated with white recta...

Page 614: ...er is identical to its own address with a set R W bit The slave transmitter shifts the serial data out on SDA with the clock pulses that are generated by the master device The slave device does not generate the clock but it will hold SCL low while intervention of the CPU is required after a byte has been transmitted If the master requests data from the slave the USCI module is automatically config...

Page 615: ...d low until data available DATA DATA A UCSTPIFG 1 UCSTTIFG 0 A A DATA A S SLA R UCTR 1 Transmitter UCSTTIFG 1 UCBxTXIFG 1 UCBxTXBUF discarded DATA A S SLA W UCTR 0 Receiver UCSTTIFG 1 Arbitration lost as master and addressed as slave UCALIFG 1 UCMST 0 UCTR 1 Transmitter UCSTTIFG 1 UCBxTXIFG 1 UCSTPIFG 0 UCBxTXIFG 0 Repeated start continue as slave transmitter Repeated start continue as slave recei...

Page 616: ...next data byte If the previous data was not read from the receive buffer UCBxRXBUF at the end of a reception the bus is stalled by holding SCL low As soon as UCBxRXBUF is read the new data is transferred into UCBxRXBUF an acknowledge is sent to the master and the next data can be received Setting the UCTXNACK bit causes a NACK to be transmitted to the master during the next acknowledgment cycle A ...

Page 617: ...iagram Bus not stalled even if UCBxRXBUF not read P or S DATA A A Arbitration lost as master and addressed as slave UCALIFG 1 UCMST 0 UCTR 0 Receiver UCSTTIFG 1 UCGC 1if general call UCBxTXIFG 0 UCSTPIFG 0 Last byte is not acknowledged UCTR 0 Receiver UCSTTIFG 1 UCSTPIFG 0 Gen Call A UCTR 0 Receiver UCSTTIFG 1 UCGC 1 Reception of the general call address UCTXNACK 0 Bus stalled SCL held low if UCBx...

Page 618: ...ith the R W bit set This will set the UCSTTIFG flag if it was previously cleared by software and the USCI modules switches to transmitter mode with UCTR 1 Figure 21 11 I2C Slave 10 bit Addressing Mode S S 11110 xx W A SLA 2 A P or S Reception of own address and data bytes All are acknowledged UCBxRXIFG 1 DATA DATA A A UCTR 0 Receiver UCSTTIFG 1 UCSTPIFG 0 Gen Call A UCTR 0 Receiver UCSTTIFG 1 UCGC...

Page 619: ...CBxTXBUF before the acknowledge cycle the bus is held during the acknowledge cycle with SCL low until data is written into UCBxTXBUF Data is transmitted or the bus is held as long as the UCTXSTP bit or UCTXSTT bit is not set Setting UCTXSTP will generate a STOP condition after the next acknowledge from the slave If UCTXSTP is set during the transmission of the slave s address or while the USCI mod...

Page 620: ...SLA R UCTXSTP 1 1 UCTR 1 Transmitter 2 UCTXSTT 1 1 UCTR 0 Receiver 2 UCTXSTT 1 Arbitration lost in slave address or data byte A A Other master continues Arbitration lost and addressed as slave Other master continues A UCALIFG 1 UCMST 0 UCTR 0 Receiver UCSTTIFG 1 UCGC 1if general call UCBxTXIFG 0 UCSTPIFG 0 USCI continues as Slave Receiver Not acknowledge received after a data byte UCTXSTT 0 UCTXST...

Page 621: ...ng the UCTXSTP bit will generate a STOP condition After setting UCTXSTP a NACK followed by a STOP condition is generated after reception of the data from the slave or immediately if the USCI module is currently waiting for UCBxRXBUF to be read If a master wants to receive a single byte only the UCTXSTP bit must be set while the byte is being received For this case the UCTXSTT may be polled to dete...

Page 622: ... UCTXSTT 1 DATA S SLA R 1 UCTR 0 Receiver 2 UCTXSTT 1 Not acknowledge received after slave address UCTXSTT 0 UCNACKIFG 1 P S SLA W S SLA R 1 UCTR 1 Transmitter 2 UCTXSTT 1 1 UCTR 0 Receiver 2 UCTXSTT 1 Arbitration lost in slave address or data byte A Other master continues UCALIFG 1 UCMST 0 UCSTTIFG 0 Arbitration lost and addressed as slave Other master continues A UCALIFG 1 UCMST 0 UCTR 1 Transmi...

Page 623: ... I2C Master 10 bit Addressing Mode Master Transmitter S A A P 1 UCTR 1 Transmitter 2 UCTXSTT 1 Successful transmission to a slave receiver UCBxTXIFG 1 UCBxTXIFG 1 DATA DATA A A UCTXSTP 1 UCTXSTT 0 UCTXSTP 0 11110 xx W SLA 2 S A P 1 UCTR 0 Receiver 2 UCTXSTT 1 Successful reception from a slave transmitter DATA DATA A UCTXSTP 1 A UCTXSTT 0 UCTXSTP 0 A A 11110 xx W SLA 2 11110 xx R Master Receiver S ...

Page 624: ...mitter that lost arbitration switches to the slave receiver mode and sets the arbitration lost flag UCALIFG If two or more devices send identical first bytes arbitration continues on the subsequent bytes Figure 21 15 Arbitration Procedure Between Two Master Transmitters 1 0 0 0 1 0 0 0 1 1 1 1 1 n Device 1 Lost Arbitration and Switches Off Bus Line SCL Data From Device 1 Data From Device 2 Bus Lin...

Page 625: ...ow periods of the generated SCL are tLOW MIN tHIGH MIN UCBRxń2 fBRCLK when UCBRx is even and tLOW MIN tHIGH MIN UCBRx 1 ń2 fBRCLK when UCBRx is odd The USCI clock source frequency and the prescaler setting UCBRx must to be chosen such that the minimum low and high period times of the I2C specifi cation are met During the arbitration procedure the clocks from the different masters must be synchroni...

Page 626: ...SCI module provides automatic clock activation for SMCLK for use with low power modes When SMCLK is the USCI clock source and is inactive because the device is in a low power mode the USCI module automatically activates it when needed regardless of the control bit settings for the clock source The clock remains active until the USCI module returns to its idle condition After the USCI module return...

Page 627: ...errupt request is generated if UCBxRXIE and GIE are also set UCBxRXIFG and UCBxRXIE are reset after a PUC signal or when UCSWRST 1 UCxRXIFG is automatically reset when UCxRXBUF is read I2C State Change Interrupt Operation Table 21 1 Describes the I2C state change interrupt flags Table 21 1 I2C State Change Interrupt Flags Interrupt Flag Interrupt Condition UCALIFG Arbitration lost Arbitration can ...

Page 628: ...in either UART or SPI mode and state change interrupts from USCI_B0 in I2C mode USCIA0_RX_USCIB0_I2C_STATE_ISR BIT B UCA0RXIFG IFG2 USCI_A0 Receive Interrupt JNZ USCIA0_RX_ISR USCIB0_I2C_STATE_ISR Decode I2C state changes Decode I2C state changes RETI USCIA0_RX_ISR Read UCA0RXBUF clears UCA0RXIFG RETI The following software example shows an extract of the interrupt service routine that handles dat...

Page 629: ...IE2 Read write 001h Reset with PUC SFR interrupt flag register 2 IFG2 Read write 003h 00Ah with PUC Note Modifying SFR bits To avoid modifying control bits of other modules it is recommended to set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B or CLR B instructions Table 21 3 USCI_B1 Control and Status Registers Register Short Form Register Type Address Initial...

Page 630: ...5 Multi master environment select 0 Single master environment There is no other master in the system The address compare unit is disabled 1 Multi master environment Unused Bit 4 Unused UCMST Bit 3 Master mode select When a master looses arbitration in a multi master environment UCMM 1 the UCMST bit is automatically cleared and the module acts as slave 0 Slave mode 1 Master mode UCMODEx Bits 2 1 US...

Page 631: ...cknowledge normally 1 Generate NACK UCTXSTP Bit 2 Transmit STOP condition in master mode Ignored in slave mode In master receiver mode the STOP condition is preceded by a NACK UCTXSTP is automatically cleared after STOP is generated 0 No STOP generated 1 Generate STOP UCTXSTT Bit 1 Transmit START condition in master mode Ignored in slave mode In master receiver mode a repeated START condition is p...

Page 632: ...SCI_Bx Baud Rate Control Register 0 7 6 5 4 3 2 1 0 UCBRx low byte rw rw rw rw rw rw rw rw UCBxBR1 USCI_Bx Baud Rate Control Register 1 7 6 5 4 3 2 1 0 UCBRx high byte rw rw rw rw rw rw rw rw UCBRx Bit clock prescaler setting The 16 bit value of UCBxBR0 UCBxBR1 256 forms the prescaler value ...

Page 633: ...ived 1 General call address received UCBBUSY Bit 4 Bus busy 0 Bus inactive 1 Bus busy UCNACK IFG Bit 3 Not acknowledge received interrupt flag UCNACKIFG is automatically cleared when a START condition is received 0 No interrupt pending 1 Interrupt pending UCSTPIFG Bit 2 Stop condition interrupt flag UCSTPIFG is automatically cleared when a START condition is received 0 No interrupt pending 1 Inter...

Page 634: ... accessible and contains the last received character from the receive shift register Reading UCBxRXBUF resets UCBxRXIFG UCBxTXBUF USCI_Bx Transmit Buffer Register 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw UCTXBUFx Bits 7 0 The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted Writing to the transmit data buffer cl...

Page 635: ...CI_Bx I2C controller The address is right justified In 7 bit addressing mode Bit 6 is the MSB Bits 9 7 are ignored In 10 bit addressing mode Bit 9 is the MSB UCBxI2CSA USCI_Bx I2C Slave Address Register 15 14 13 12 11 10 9 8 0 0 0 0 0 0 I2CSAx r0 r0 r0 r0 r0 r0 rw 0 rw 0 7 6 5 4 3 2 1 0 I2CSAx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CSAx Bits 9 0 I2C slave address The I2CSAx bits contain the sla...

Page 636: ...w 0 rw 0 rw 0 rw 0 rw 0 Reserved Bits 7 4 Reserved UCNACKIE Bit 3 Not acknowledge interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCSTPIE Bit 2 Stop condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCSTTIE Bit 1 Start condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCALIE Bit 0 Arbitration lost interrupt enable 0 Interrupt disabled 1 Interrupt enabl...

Page 637: ...Bits 1 0 These bits may be used by other modules see the device specific data sheet IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UCB0 TXIFG UCB0 RXIFG rw 1 rw 0 Bits 7 4 These bits may be used by other modules see the device specific data sheet UCB0 TXIFG Bit 3 USCI_B0 transmit interrupt flag UCB0TXIFG is set when UCB0TXBUF is empty 0 No interrupt pending 1 Interrupt pending UCB0 RXIFG Bit 2 USC...

Page 638: ...ts 1 0 These bits may be used by other USCI modules see the device specific data sheet UC1IFG USCI_B1 Interrupt Flag Register 7 6 5 4 3 2 1 0 Unused Unused Unused Unused UCB1 TXIFG UCB1 RXIFG rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 Unused Bits 7 4 Unused UCB1 TXIFG Bit 3 USCI_B1 transmit interrupt flag UCB1TXIFG is set when UCB1TXBUF is empty 0 No interrupt pending 1 Interrupt pending UCB1 RXIFG Bit 2 USCI_...

Page 639: ...odules are implemented in the MSP430FG43x and MSP430xG461x devices Two OA modules are implemented in the MSP430FG42x0 devices Topic Page 22 1 OA Introduction 22 2 22 2 OA Operation 22 4 22 3 OA Modules in FG42x0 Devices 22 11 22 4 OA Registers 22 16 22 5 OA Registers in FG42x0 Devices 22 19 Chapter 22 ...

Page 640: ...tware selectable feedback resistor ladder for PGA implementations Note Multiple OA Modules Some devices may integrate more than one OA module In the case where more than one OA is present on a device the multiple OA modules operate identically Throughout this chapter nomenclature appears such as OAxCTL0 to describe register names When this occurs the x is used to indicate which OA module is being ...

Page 641: ... 3 NA 000 001 100 011 010 111 110 101 000 001 100 011 010 111 110 101 3 OAPx 3 1 OAFCx 2 4 5 6 1 1 OAFCx 0 1 3 OAFCx 7 reserved AVCC reserved OANx 00 01 10 11 OANx 00 01 10 11 OAxI0 OAxI1 unused OAxOUT unused OANx 0 A1 int ext OA0O OA0 A3 int ext OA1O OA1 A5 int ext OA2O OA2 A12 int OA0 A13 int OA1 A14 int OA2 Int DAC12_1OUT OAxI0 OAxI1 Int DAC12_0OUT Int DAC12_1OUT OA1RBOTTOM OA0 OA2RBOTTOM OA1 O...

Page 642: ...als or internal signals from one of the DAC12 modules One of the non inverting inputs is tied together internally for all OA modules The OA input signal swing is software selectable with the OARRIP bit When OARRIP 0 rail to rail input mode is selected and the OA uses higher quiescent current See the device data sheet for parameters 22 2 3 OA Output The OA has configurable output selection The OA o...

Page 643: ... RBOTTOM and the inverting input of the OAx providing a unity gain buffer The non inverting input is selected by the OAPx bits The external connection for the inverting input is disabled and the OANx bits are don t care The OAx output is internally connected to the ADC12 input channel as selected by the OAxCTL0 bits Comparator Mode In this mode the output of the OAx is isolated from the resistor l...

Page 644: ...s the OAxI0 OAxI1 or the output of one of the remaining OAs selected with the OANx bits The OAxTAP signal is connected to the inverting input of the OAx providing an inverting amplifier with a gain of OAxTAP ratio The OAxTAP ratio is selected by the OAFBRx bits The non inverting input is selected by the OAPx bits The OAx output is internally connected to the ADC12 input channel as selected by the ...

Page 645: ... 22 3 The OAx interconnections are shown in Figure 22 3 Table 22 2 Two Opamp Differential Amplifier Control Register Settings Register Settings binary OA0CTL0 00 xx xx 0 0 OA0CTL1 000 111 0 x OA1CTL0 10 xx xx x x OA1CTL1 xxx 110 0 x Table 22 3 Two Opamp Differential Amplifier Gain Settings OA1 OAFBRx Gain 000 0 001 1 3 010 1 011 1 2 3 100 3 101 4 1 3 110 7 111 15 Figure 22 2 Two Opamp Differential...

Page 646: ... 10 11 OAPMx 0 1 1 OAFBRx A13 ext OAADC0 4R 4R 2R 2R R R R R OA1 OAADC1 0 1 00 01 10 11 000 001 100 011 010 111 110 101 000 001 100 011 010 111 110 101 3 00 01 10 11 A3 int ext OA1O A13 int 0 1 OAADC1 OAPMx OAPx OA0OUT OA0 00 01 10 11 0 1 00 01 10 11 000 001 100 011 010 111 110 101 OA1RBOTTOM V2 V1 ...

Page 647: ... in Table 22 5 The OAx interconnections are shown in Figure 22 5 Table 22 4 Three Opamp Differential Amplifier Control Register Settings Register Settings binary OA0CTL0 00 xx xx 0 0 OA0CTL1 xxx 001 0 x OA1CTL0 00 xx xx 0 0 OA1CTL1 000 111 0 x OA2CTL0 11 11 xx x x OA2CTL1 xxx 110 0 x Table 22 5 Three Opamp Differential Amplifier Gain Settings OA0 OA2 OAFBRx Gain 000 0 001 1 3 010 1 011 1 2 3 100 3...

Page 648: ...0 01 10 11 000 001 100 011 010 111 110 101 000 001 100 011 010 111 110 101 3 OAPMx 0 1 1 OAFBRx A14 ext OAADC0 4R 4R 2R 2R R R R R OA2 OAADC1 0 1 00 01 10 11 000 001 100 011 010 111 110 101 000 001 100 011 010 111 110 101 3 00 01 10 11 A5 int ext OA2O A14 int OA0TAP 0 1 OAADC1 OA1OUT OAPMx OAPx OA1 00 01 10 11 0 1 00 01 10 11 000 001 100 011 010 111 110 101 OA2RBOTTOM V2 V1 ...

Page 649: ...diagram of the operational amplifier is shown in Figure 22 6 Figure 22 6 FG42x0 Operational Amplifiers Block Diagram OAPMx OAPx OAx OAFCx 001 OAxI0 OA0I0 Int DAC12 00 01 10 11 0 1 0 1 OAFCx OANx 00 01 10 11 OA0OUT A0 OA0 OA1OUT A1 OA1 OAxI1 OAxI2 Int DAC12 3 000 001 101 111 110 reserved unused unused reserved unused OAN0 OA0FB A0 OA0 OA1FB A1 OA1 1 SWCTL3 OA0 SWCTL7 OA1 1 0 OACAL Int SD16_A A0 OA0...

Page 650: ...fro more details 22 3 3 OA Outputs The OA outputs are routed to the respective output pin OAxOUT and the positive SD16_A inputs A0 OA0 or A1 OA1 22 3 4 OA Configurations The OA can be configured for different amplifier functions with the OAFCx bits as listed in Table 22 6 The SWCTL0 SWCTL1 SWCTL4 and SWCTL5 bits force settings of the OAFCx bits See section Switch Control for more details Table 22 ...

Page 651: ...own in Figure 22 7 mimics a low resistive multiplexer between the inputs OAxI1 and OAxI2 Since the current into the negative terminal of operational amplifier is very low the voltage drop over the negative input multiplexer can be neglected The multiplexer connecting the input OAxI1 or OAxI2 to the feedback path is included in the feedback loop thus compensating for the voltage drop across this mu...

Page 652: ...he operational amplifier as transimpedance amplifier SWCTL2 closes the switch SW0C to ground and SWCTL6 closes the switch SW1C SWCTL3 shorts the external feedback resistor for OA0 and SWCTL7 shorts the external feedback resistor for OA1 SWCTL0 and SWCTL1 select the negative analog input to the transimpedance amplifier OA0 SWCTL4 and SWCTL5 select them for OA1 as shown in Table 22 7 Table 22 7 Inpu...

Page 653: ...o be connected to the negative input of the sigma delta ADC by setting the calibration bit OACAL The voltage that can be measured between the negative and the positive SD16_A input represents the offset voltage of the operational amplifier The measurement result can be incorporated into the later measurement results to compensate for the offset of the amplifier Figure 22 9 Offset Calibration OAx A...

Page 654: ...control register 0 OA0CTL0 Read write 0C0h Reset with PUC OA0 control register 1 OA0CTL1 Read write 0C1h Reset with PUC OA1 control register 0 OA1CTL0 Read write 0C2h Reset with PUC OA1 control register 1 OA1CTL1 Read write 0C3h Reset with PUC OA2 control register 0 OA2CTL0 Read write 0C4h Reset with PUC OA2 control register 1 OA2CTL1 Read write 0C5h Reset with PUC ...

Page 655: ...OAPMx Bits 3 2 Slew rate select These bits select the slew rate vs current consumption for the OA 00 Off output high Z 01 Slow 10 Medium 11 Fast OAADC1 Bit 1 OA output select This bit connects the OAx output to ADC12 input Ax and output pin OAxO when OAFCx 0 0 OAx output not connected to internal external A1 OA0 A3 OA1 or A5 OA2 signals 1 OAx output connected to internal external A1 OA0 A3 OA1 or ...

Page 656: ... 5 110 Tap 6 111 Tap 7 OAFCx Bits 4 2 OAx function control This bit selects the function of OAx 000 General purpose 001 Unity gain buffer 010 Reserved 011 Comparing amplifier 100 Non inverting PGA 101 Reserved 110 Inverting PGA 111 Differential amplifier Reserved Bit 1 Reserved OARRIP Bit 0 OA rail to rail input off 0 OAx input signal range is rail to rail 1 OAx input signal range is limited See t...

Page 657: ...hort Form Register Type Address Initial State OA0 control register 0 OA0CTL0 Read write 0C0h Reset with PUC OA0 control register 1 OA0CTL1 Read write 0C1h Reset with PUC OA1 control register 0 OA1CTL0 Read write 0C2h Reset with PUC OA1 control register 1 OA1CTL1 Read write 0C3h Reset with PUC Switch control register SWCTL Read write 0CFh Reset with PUC ...

Page 658: ...select the input signal for the OAx inverting input 00 OAxI1 01 OAxI2 10 DAC internal 11 VSS OAPx Bits 5 4 Non inverting input select These bits select the input signal for the OAx non inverting input 00 OAxI0 01 OA0I0 10 DAC internal 11 VSS OAPMx Bits 3 2 Slew rate select These bits select the slew rate vs current consumption of the OAx 00 Off output high Z 01 Slow 10 Medium 11 Fast Reserved Bits...

Page 659: ...s 7 5 Reserved OAFCx Bit 4 2 OAx function control These bits select the function of OAx 000 General purpose 001 Unity gain buffer 010 Reserved 011 Reserved 100 Reserved 101 Reserved 110 Inverting amplifier 111 Reserved OACAL Bit 1 Offset calibration This bit enables the offset calibration 0 Offset calibration disabled 1 Offset calibration enabled Reserved Bit 0 Reserved ...

Page 660: ...VSS SWCTL5 SWCTL4 Bits 5 4 OANx and OAFCx forced settings for OA1 00 No forced settings 01 OANx forced to 00 OAFCx forced to 110 10 OANx forced to 01 OAFCx forced to 110 11 No forced settings SWCTL3 Bit 3 Shunt switch for OA0 0 Switch open 1 OA0OUT and OA0FB shorted together SWCTL2 Bit 2 SW0C control 0 Switch open 1 SW0C shorted to VSS SWCTL1 SWCTL0 Bits 1 0 OANx and OAFCx forced settings for OA0 ...

Page 661: ...is an analog voltage comparator This chapter describes Comparator_A Comparator_A is implemented in all MSP430x4xx devices Topic Page 23 1 Comparator_A Introduction 23 2 23 2 Comparator_A Operation 23 4 23 3 Comparator_A Registers 23 9 Chapter 23 ...

Page 662: ...nalog signals Features of Comparator_A include Inverting and non inverting terminal input multiplexer Software selectable RC filter for the comparator output Output provided to Timer_A capture input Software control of the port input buffer Interrupt capability Selectable reference voltage generator Comparator and reference generator can be powered down The Comparator_A block diagram is shown in F...

Page 663: ...Comparator_A Figure 23 1 Comparator_A Block Diagram CAOUT CAEX 0 5x 0 25x Set_CAIFG CA1 CCI1B 0V G D S P2CA0 P2CA1 CAF CARSEL CAON CAREFx 1 0 00 01 10 11 00 01 10 11 1 0 1 0 1 0 1 0 1 0 0V 1 0 VCAREF CA0 0 1 0 1 VCC VCC VCC Tau 2 0 s ...

Page 664: ...ssociated port pins using the P2CAx bits Both comparator terminal inputs can be controlled individually The P2CAx bits allow Application of an external signal to the and terminals of the comparator Routing of an internal reference voltage to an associated output port pin Internally the input switch is constructed as a T switch to suppress distortion in the signal path Note Comparator Input Connect...

Page 665: ...he output filter can reduce errors associated with comparator oscillation Figure 23 2 RC Filter Response at the Output of the Comparator Terminal Terminal Comparator Inputs Comparator Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT 23 2 4 Voltage Reference Generator The voltage reference generator is used to generate VCAREF which can be applied to either comparator input terminal Th...

Page 666: ...s critical any P1 pin connected to analog signals should be disabled with their associated CAPDx bit Figure 23 3 Transfer Characteristic and Power Dissipation in a CMOS Inverter Buffer VCC VSS ICC VO VI 0 VCC VI VCC ICC CAPD x 1 23 2 6 Comparator_A Interrupts One interrupt flag and one interrupt vector are associated with the Comparator_A as shown in Figure 23 4 The interrupt flag CAIFG is set on ...

Page 667: ...s used to calculate the temperature sensed by Rmeas are Two digital I O pins to charge and discharge the capacitor I O set to output high VCC to charge capacitor reset to discharge I O switched to high impedance input with CAPDx set when not in use One output charges and discharges the capacitor via Rref One output discharges capacitor via Rmeas The terminal is connected to the positive terminal o...

Page 668: ... Figure 23 6 Timing for Temperature Measurement Systems VC VCC 0 25 VCC Phase I Charge Phase II Discharge Phase III Charge tref Phase IV Discharge tmeas t Rmeas Rref The VCC voltage and the capacitor value should remain constant during the conversion but are not critical since they cancel in the ratio Nmeas Nref Rmeas C ln Vref VCC Rref C ln Vref VCC Nmeas Nref Rmeas Rref Rmeas Rref Nmeas Nref ...

Page 669: ...d in Table 23 1 Table 23 1 Comparator_A Registers Register Short Form Register Type Address Initial State Comparator_A control register 1 CACTL1 Read write 059h Reset with POR Comparator_A control register 2 CACTL2 Read write 05Ah Reset with POR Comparator_A port disable CAPD Read write 05Bh Reset with POR ...

Page 670: ... 0 VCAREF is applied to the terminal 1 VCAREF is applied to the terminal CAREF Bits 5 4 Comparator_A reference These bits select the reference voltage VCAREF 00 Internal reference off An external reference can be applied 01 0 25 VCC 10 0 50 VCC 11 Diode reference is selected CAON Bit 3 Comparator_A on This bit turns on the comparator When the comparator is off it consumes no current The reference ...

Page 671: ... 0 Comparator_A output is not filtered 1 Comparator_A output is filtered CAOUT Bit 0 Comparator_A output This bit reflects the value of the comparator output Writing this bit has no effect CAPD Comparator_A Port Disable Register 7 6 5 4 3 2 1 0 CAPD7 CAPD6 CAPD5 CAPD4 CAPD3 CAPD2 CAPD1 CAPD0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 CAPDx Bits 7 0 Comparator_A port disable These bits individually di...

Page 672: ...23 12 Comparator_A ...

Page 673: ... mux LCDs This chapter describes LCD controller The LCD controller is implemented on all MSP430x4xx devices except the MSP430x42x0 and MSP430FG461x devices Topic Page 24 1 LCD Controller Introduction 24 2 24 2 LCD Controller Operation 24 4 24 3 LCD Controller Registers 24 18 Chapter 24 ...

Page 674: ...tic 2 mux 3 mux and 4 mux LCDs The LCD controller features are Display memory Automatic signal generation Configurable frame frequency Blinking capability Support for 4 types of LCDs J Static J 2 mux 1 2 bias J 3 mux 1 3 bias J 4 mux 1 3 bias The LCD controller block diagram is shown in Figure 24 1 Note Max LCD Segment Control The maximum number of segment lines available differs with device See t...

Page 675: ...Voltage Multiplexer Timing Generator R23 R13 R03 COM0 COM2 COM1 R33 COM3 S0 S1 Common Output Control S39 S38 SEG0 SEG1 SEG38 SEG39 Mux Mux Mux LCDP2 LCDP1 LCDP0 LCDMX1 LCDMX0 LCDSON LCDON fLCD from Basic Timer OSCOFF from SR V1 V2 V3 V4 V5 VD VC VB VA Static 2Mux 3Mux 4Mux R R Rx Rx Rx R R R External Resistors 091h 0A4h Rx Optional Contrast Control ...

Page 676: ... 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 0 Associated Segment Pins Sn 1 Sn 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 n 092h 093h 094h 095h 096h 31 30 33 32 35 34 37 36 39 38 30 32 34 36 38 091h 24 2 2 Blinking the LCD The LCD controller supports blinking The LCDSON bit is ANDed with each segment s memory bit When LCDSON 1 each segment is on or off according to its bit valu...

Page 677: ...ally an additional resistor Rx to GND Increasing the voltage at R03 reduces the total applied segment voltage decreasing the LCD contrast 24 2 5 LCD Outputs Some LCD segment common and Rxx functions are multiplexed with digital I O functions These pins can function either as digital I O or as LCD functions The pin functions for COMx and Rxx when multiplexed with digital I O are selected using the ...

Page 678: ...one common line COM0 is used Figure 24 3 shows some example static waveforms Figure 24 3 Example Static Waveforms fframe COM0 SP1 SP2 Resulting Voltage for Segment a COM0 SP1 Segment Is On COM0 SP1 SP6 SP2 SP7 SP3 SP8 SP4 SP5 V1 V5 V1 V5 V1 V5 V1 0 V V1 0 V SP Segment Pin Resulting Voltage for Segment b COM0 SP2 Segment Is Off a b ...

Page 679: ...3h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 24 22 20 18 16 14 12 10 8 6 4 2 0 Digit 4 Digit 3 Digit 2 Digit 1 a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ...

Page 680: ...nts the on segments according to the content of Rx MOV B Table Rx RY Load segment information into temporary memory Ry 0000 0000 hfdb geca MOV B Ry LCDn Note All bits of an LCD memory byte are written RRA Ry Ry 0000 0000 0hfd bgec MOV B Ry LCDn 1 Note All bits of an LCD memory byte are written RRA Ry Ry 0000 0000 00hf dbge MOV B Ry LCDn 2 Note All bits of an LCD memory byte are written RRA Ry Ry 0...

Page 681: ...COM0 and COM1 are used Figure 24 5 shows some example 2 mux waveforms Figure 24 5 Example 2 Mux Waveforms COM1 COM0 COM0 COM1 SP1 SP2 SP1 SP2 SP3 SP4 V1 V3 V5 V1 V5 V1 V5 V1 V3 0 V V3 V1 V1 V3 0 V V3 V5 fframe Resulting Voltage for Segment h COM0 SP2 Segment Is On Resulting Voltage for Segment b COM1 SP2 Segment Is Off SP Segment Pin b h V1 V3 V5 ...

Page 682: ...10 8 6 4 2 0 Digit 7 Digit 6 Digit 4 Digit 2 3 2 1 1 2 Digit 8 Digit 5 Digit 3 Digit 1 a b c d e f g h a b c d e f g h S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1f 1h 1d 1e 2f 2h 2d 2e 3f 3h 3d 3e 4f 4h 4d 4e 5f...

Page 683: ...QU 010h The register content of Rx should be displayed The Table represents the on segments according to the content of Rx MOV B Table Rx Ry Load segment information into temporary memory MOV B Ry LCDn Ry 0000 0000 gebh cdaf Note All bits of an LCD memory byte are written RRA Ry Ry 0000 0000 0geb hcda RRA Ry Ry 0000 0000 00ge bhcd MOV B Ry LCDn 1 Note All bits of an LCD memory byte are written Tab...

Page 684: ...2 are used Figure 24 7 shows some example 3 mux waveforms Figure 24 7 Example 3 Mux Waveforms COM0 COM1 COM2 COM0 COM2 SP1 SP2 SP3 SP3 SP2 SP1 fframe V1 V2 V4 V5 V1 V5 V1 0 V V1 V1 0 V V1 COM1 Resulting Voltage for Segment e COM0 SP1 Segment Is Off Resulting Voltage for Segment d COM0 SP2 Segment Is On SP Segment Pin d e V1 V2 V4 V5 V1 V2 V4 V5 V1 V2 V4 V5 V1 V2 V4 V5 ...

Page 685: ...14 12 10 8 6 4 2 0 Digit 9 Digit 7 Digit 4 Digit 2 3 2 1 y y Digit 5 Digit 3 Digit 1 Digit 6 Digit 8 Digit 10 DIGIT10 DIGIT1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 1e 1d 1h 2e 2d 2h 3e 3d 3h 4e 4d 4h 5e 5d 5h 6e 6d 6h 7...

Page 686: ...ed characters MOV Table Rx Ry Load segment information to temporary mem Ry 0000 0bch 0agd 0yfe MOV B Ry LCDn write a g d y f e of Digit n LowByte SWPB Ry Ry 0agd 0yfe 0000 0bch BIC B 07h LCDn 1 write b c h of Digit n HighByte BIS B Ry LCDn 1 EVNDIG RLA Rx LCD in 3mux has 9 segments per digit word table required for displayed characters MOV Table Rx Ry Load segment information to temporary mem Ry 0...

Page 687: ... are used Figure 24 9 shows some example 4 mux waveforms Figure 24 9 Example 4 Mux Waveforms fframe V1 V2 V4 V5 V1 0 V V1 V1 0 V V1 COM0 COM1 COM2 COM3 SP1 SP2 COM3 COM2 COM1 COM0 SP2 SP1 Resulting Voltage for Segment e COM1 SP1 Segment Is Off Resulting Voltage for Segment c COM1 SP2 Segment Is On SP Segment Pin c e V1 V2 V4 V5 V1 V2 V4 V5 V1 V2 V4 V5 V1 V2 V4 V5 V1 V2 V4 V5 ...

Page 688: ...Digit 11 Digit 13 Digit 15 a b c d e f g h a b c d e f g h DIGIT15 DIGIT1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1d 1h 2d 2h 3d 3h 4d 4h 5d 5h 6d 6h 7d 7h 8d 8h 9d 9h 10d 10h 11d 11h 12d 12h 13d 13h 14d 14h 15d 15h C...

Page 689: ...e a EQU 080h b EQU 040h c EQU 020h d EQU 001h e EQU 002h f EQU 008h g EQU 004h h EQU 010h The LSDigit of register Rx should be displayed The Table represents the on segments according to the content of Rx MOV B Table Rx LCDn n 1 15 all eight segments are written to the display memory Table DB a b c d e f displays 0 DB b c displays 1 DB b c d e g displays d DB a d e f g displays E DB a e f g displa...

Page 690: ...anged LCD memory 6 LCDM6 Read write 096h Unchanged LCD memory 7 LCDM7 Read write 097h Unchanged LCD memory 8 LCDM8 Read write 098h Unchanged LCD memory 9 LCDM9 Read write 099h Unchanged LCD memory 10 LCDM10 Read write 09Ah Unchanged LCD memory 11 LCDM11 Read write 09Bh Unchanged LCD memory 12 LCDM12 Read write 09Ch Unchanged LCD memory 13 LCDM13 Read write 09Dh Unchanged LCD memory 14 LCDM14 Read ...

Page 691: ...011 S0 S23 are LCD function 100 S0 S27 are LCD function 101 S0 S31 are LCD function 110 S0 S35 are LCD function 111 S0 S39 are LCD function LCDMXx Bits 4 3 LCD mux rate These bits select the LCD mode 00 Static 01 2 mux 10 3 mux 11 4 mux LCDSON Bit 2 LCD segments on This bit supports flashing LCD applications by turning off all segment lines while leaving the LCD timing generator and R33 enabled 0 ...

Page 692: ...24 20 LCD Controller ...

Page 693: ...mux 3 mux or 4 mux LCDs This chapter describes the LCD_A controller The LCD_A controller is implemented on the MSP430x42x0 and MSP430FG46xx devices Topic Page 25 1 LCD Controller Introduction 25 2 25 2 LCD Controller Operation 25 4 25 3 LCD Controller Registers 25 21 Chapter 25 ...

Page 694: ...features are Display memory Automatic signal generation Configurable frame frequency Blinking capability Regulated charge pump Contrast control by software Support for 4 types of LCDs J Static J 2 mux 1 2 bias or 1 3 bias J 3 mux 1 2 bias or 1 3 bias J 4 mux 1 2 bias or 1 3 bias The LCD controller block diagram is shown in Figure 25 1 Note Maximum LCD Segment Control The maximum number of segment ...

Page 695: ...ing Generator COM0 COM2 COM1 COM3 S0 S1 Common Output Control S39 S38 SEG0 SEG1 SEG38 SEG39 Mux Mux Mux LCDSx LCDMXx LCDSON LCDON fLCD OSCOFF from SR V1 V2 V3 V4 VD VC VB VA 091h 0A4h ACLK 32768 Hz LCDFREQx Regulated Charge Pump Contrast Control VLCDx VLCD LCDCAP R33 LCD Bias Generator V1 VLCD LCD2B LCDMXx V2 V3 V4 LCDCPEN V5 V5 Divider 32 512 4 REXT R23 LCDREF R13 R03 R03EXT 10 LCDREF ...

Page 696: ... memory bit is set Figure 25 2 LCD memory 3 2 1 0 3 2 1 0 Associated Common Pins 097h Address 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h 0A1h 0A2h 0A3h 0A4h 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 0 Associated Segment Pins Sn 1 Sn 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 n 092h 093h 094h 095h 096h 31 30 33 32 35 34 37 36 39 38 30 32 34 36 38 091h 25 2 2 B...

Page 697: ...cal occur on DVCC However the charge pump duty cycle is approximately 1 1000 resulting in a 2 μA average current The charge pump may be temporarily disabled by setting LCDCPEN 0 with VLCDx 0 to reduce system noise In this case the voltage present at the external capacitor is used for the LCD voltages until the charge pump is re enabled Note Capacitor Required For Internal Charge Pump A 4 7 μF or l...

Page 698: ...XT is set When using an external resistor divider R33 may serve as a switched VLCD output when VLCDEXT 0 This allows the power to the resistor ladder to be turned off eliminating current consumption when the LCD is not used When VLCDEXT 1 R33 serves as a VLCD input Figure 25 3 Bias Generation 0 1 VLCDEXT 0 0 LCD Off Internal VLCD LCDREF R13 R23 R03 LCDCAP R33 REXT 1 0 1 0 1 0 1 0 V5 V2 int V3 int ...

Page 699: ... turned off VRMS OFF as functions of VLCD It also shows the resulting contrast ratios between the on and off states Table 25 1 LCD Voltage and Biasing Characteristics Mode Bias Config LCDMx LCD2B COM Lines Voltage Levels VRMS OFF VLCD VRMS ON VLCD Contrast Ratio VRMS ON VRMS OFF Static Static 00 X 1 V1 V5 0 1 1 0 2 mux 1 2 01 1 2 V1 V3 V5 0 354 0 791 2 236 2 mux 1 3 01 0 2 V1 V2 V4 V5 0 333 0 745 ...

Page 700: ...has the lowest current consumption The highest frequency has the least flicker 25 2 5 LCD Outputs Some LCD segment common and Rxx functions are multiplexed with digital I O functions These pins can function either as digital I O or as LCD functions The pin functions for COMx and Rxx when multiplexed with digital I O are selected using the applicable PxSELx bits as described in the Digital I O chap...

Page 701: ...d one common line COM0 is used Figure 25 4 shows some example static waveforms Figure 25 4 Example Static Waveforms fframe COM0 SP1 SP2 Resulting Voltage for Segment a COM0 SP1 Segment Is On COM0 SP1 SP6 SP2 SP7 SP3 SP8 SP4 SP5 V1 V5 V1 V5 V1 V5 V1 0 V V1 0 V SP Segment Pin Resulting Voltage for Segment b COM0 SP2 Segment Is Off a b ...

Page 702: ...h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 24 22 20 18 16 14 12 10 8 6 4 2 0 Digit 4 Digit 3 Digit 2 Digit 1 a b c d e f g h a b c d e f g h a b c d e f g h a b c d e f g h S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ...

Page 703: ...esents the on segments according to the content of Rx MOV B Table Rx RY Load segment information into temporary memory Ry 0000 0000 hfdb geca MOV B Ry LCDn Note All bits of an LCD memory byte are written RRA Ry Ry 0000 0000 0hfd bgec MOV B Ry LCDn 1 Note All bits of an LCD memory byte are written RRA Ry Ry 0000 0000 00hf dbge MOV B Ry LCDn 2 Note All bits of an LCD memory byte are written RRA Ry R...

Page 704: ...M0 and COM1 are used Figure 25 6 shows some example 2 mux 1 2 bias waveforms Figure 25 6 Example 2 Mux Waveforms COM1 COM0 COM0 COM1 SP1 SP2 SP1 SP2 SP3 SP4 V1 V3 V5 V1 V5 V1 V5 V1 V3 0 V V3 V1 V1 V3 0 V V3 V5 fframe Resulting Voltage for Segment h COM0 SP2 Segment Is On Resulting Voltage for Segment b COM1 SP2 Segment Is Off SP Segment Pin b h V1 V3 V5 ...

Page 705: ... 10 8 6 4 2 0 Digit 7 Digit 6 Digit 4 Digit 2 3 2 1 1 2 Digit 8 Digit 5 Digit 3 Digit 1 a b c d e f g h a b c d e f g h S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1f 1h 1d 1e 2f 2h 2d 2e 3f 3h 3d 3e 4f 4h 4d 4e 5...

Page 706: ... EQU 010h The register content of Rx should be displayed The Table represents the on segments according to the content of Rx MOV B Table Rx Ry Load segment information into temporary memory MOV B Ry LCDn Ry 0000 0000 gebh cdaf Note All bits of an LCD memory byte are written RRA Ry Ry 0000 0000 0geb hcda RRA Ry Ry 0000 0000 00ge bhcd MOV B Ry LCDn 1 Note All bits of an LCD memory byte are written T...

Page 707: ...2 are used Figure 25 8 shows some example 3 mux 1 3 bias waveforms Figure 25 8 Example 3 Mux Waveforms COM0 COM1 COM2 COM0 COM2 SP1 SP2 SP3 SP3 SP2 SP1 fframe V1 V2 V4 V5 V1 V5 V1 V5 V1 0 V V1 V1 0 V V1 COM1 Resulting Voltage for Segment e COM0 SP1 Segment Is Off Resulting Voltage for Segment d COM0 SP2 Segment Is On SP Segment Pin d e V1 V2 V4 V5 V1 V2 V4 V5 V1 V2 V4 V5 ...

Page 708: ... 14 12 10 8 6 4 2 0 Digit 9 Digit 7 Digit 4 Digit 2 3 2 1 y y Digit 5 Digit 3 Digit 1 Digit 6 Digit 8 Digit 10 DIGIT10 DIGIT1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 1e 1d 1h 2e 2d 2h 3e 3d 3h 4e 4d 4h 5e 5d 5h 6e 6d 6h ...

Page 709: ...ayed characters MOV Table Rx Ry Load segment information to temporary mem Ry 0000 0bch 0agd 0yfe MOV B Ry LCDn write a g d y f e of Digit n LowByte SWPB Ry Ry 0agd 0yfe 0000 0bch BIC B 07h LCDn 1 write b c h of Digit n HighByte BIS B Ry LCDn 1 EVNDIG RLA Rx LCD in 3mux has 9 segments per digit word table required for displayed characters MOV Table Rx Ry Load segment information to temporary mem Ry...

Page 710: ...e used Figure 25 10 shows some example 4 mux 1 3 bias waveforms Figure 25 10 Example 4 Mux Waveforms fframe V1 V2 V4 V5 V1 0 V V1 V1 0 V V1 COM0 COM1 COM2 COM3 SP1 SP2 COM3 COM2 COM1 COM0 SP2 SP1 Resulting Voltage for Segment e COM1 SP1 Segment Is Off Resulting Voltage for Segment c COM1 SP2 Segment Is On SP Segment Pin c e V1 V2 V4 V5 V1 V2 V4 V5 V1 V2 V4 V5 V1 V2 V4 V5 V1 V2 V4 V5 ...

Page 711: ... Digit 11 Digit 13 Digit 15 a b c d e f g h a b c d e f g h DIGIT15 DIGIT1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1d 1h 2d 2h 3d 3h 4d 4h 5d 5h 6d 6h 7d 7h 8d 8h 9d 9h 10d 10h 11d 11h 12d 12h 13d 13h 14d 14h 15d 15h ...

Page 712: ...yte a EQU 080h b EQU 040h c EQU 020h d EQU 001h e EQU 002h f EQU 008h g EQU 004h h EQU 010h The LSDigit of register Rx should be displayed The Table represents the on segments according to the content of Rx MOV B Table Rx LCDn n 1 15 all eight segments are written to the display memory Table DB a b c d e f displays 0 DB b c displays 1 DB b c d e g displays d DB a d e f g displays E DB a e f g disp...

Page 713: ...e 098h Unchanged LCD memory 9 LCDM9 Read write 099h Unchanged LCD memory 10 LCDM10 Read write 09Ah Unchanged LCD memory 11 LCDM11 Read write 09Bh Unchanged LCD memory 12 LCDM12 Read write 09Ch Unchanged LCD memory 13 LCDM13 Read write 09Dh Unchanged LCD memory 14 LCDM14 Read write 09Eh Unchanged LCD memory 15 LCDM15 Read write 09Fh Unchanged LCD memory 16 LCDM16 Read write 0A0h Unchanged LCD memor...

Page 714: ...by 192 101 Divide by 256 110 Divide by 384 111 Divide by 512 LCDMXx Bits 4 3 LCD mux rate These bits select the LCD mode 00 Static 01 2 mux 10 3 mux 11 4 mux LCDSON Bit 2 LCD segments on This bit supports flashing LCD applications by turning off all segment lines while leaving the LCD timing generator and R33 enabled 0 All LCD segments are off 1 All LCD segments are enabled and on or off according...

Page 715: ...ons LCDS16 Bit 4 LCD Segment 16 to 19 Enable This bit only affects pins with multiplexed functions Dedicated LCD pins are always LCD function 0 Multiplexed pins are port functions 1 Pins are LCD functions LCDS12 Bit 3 LCD Segment 12 to 15 Enable This bit only affects pins with multiplexed functions Dedicated LCD pins are always LCD function 0 Multiplexed pins are port functions 1 Pins are LCD func...

Page 716: ...6 Bit 1 LCD Segment 36 to 39 Enable This bit only affects pins with multiplexed functions Dedicated LCD pins are always LCD function 0 Multiplexed pins are port functions 1 Pins are LCD functions LCDS32 Bit 0 LCD Segment 32 to 35 Enable This bit only affects pins with multiplexed functions Dedicated LCD pins are always LCD function 0 Multiplexed pins are port functions 1 Pins are LCD functions ...

Page 717: ...REXT Bit 5 V2 V4 voltage select This bit selects the external connections for voltages V2 V4 0 V2 V4 are generated internally 1 V2 V4 are sourced externally and the internal bias generator is switched off VLCDEXT Bit 4 VLCD source select 0 VLCD is generated internally 1 VLCD is sourced externally LCDCPEN Bit 3 Charge pump enable 0 Charge pump disabled 1 Charge pump enabled when VLCD is generated i...

Page 718: ...e select LCDCPEN must be 1 for the charge pump to be enabled AVCC is used for VLCD when VLCDx 0000 and VREFx 00 and VLCDEXT 0 0000 Charge pump disabled 0001 VLCD 2 60 V 0010 VLCD 2 66 V 0011 VLCD 2 72 V 0100 VLCD 2 78 V 0101 VLCD 2 84 V 0110 VLCD 2 90 V 0111 VLCD 2 96 V 1000 VLCD 3 02 V 1001 VLCD 3 08 V 1010 VLCD 3 14 V 1011 VLCD 3 20 V 1100 VLCD 3 26 V 1101 VLCD 3 32 V 1110 VLCD 3 38 V 1111 VLCD ...

Page 719: ...e 12 bit analog to digital converter ADC This chapter describes the ADC12 The ADC12 is implemented in the MSP430x43x MSP430x44x and MSP430FG461x devices Topic Page 26 1 ADC12 Introduction 26 2 26 2 ADC12 Operation 26 4 26 3 ADC12 Registers 26 20 Chapter 26 ...

Page 720: ...nversion initiation by software Timer_A or Timer_B Software selectable on chip reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference Eight individually configurable external input channels twelve on MSP430FG43x and MSP430FG461x devices Conversion channels for internal temperature sensor AVCC and external references Independent channel selectable reference s...

Page 721: ...0 A1 A2 A3 A4 A5 A6 A7 ADC12MEM0 ADC12MEM15 ADC12MCTL0 ADC12MCTL15 CSTARTADDx 4 4 SHT1x CONSEQx ACLK MCLK SMCLK ADC12SSELx ADC12OSC 00 01 10 11 00 01 10 11 SHSx 00 01 10 11 00 01 10 11 ISSH 1 0 0 1 SREF2 0 1 SREF1 00 01 SREF0 10 ADC12ON BUSY REFON INCHx 0Ah 1 5 V or 2 5 V Reference on Ref_x Ref_x INCHx 0Bh 11 R R 0000 1001 1000 0010 0001 0011 0100 0101 0110 0111 1011 1010 0001 1111 1110 1101 1100 ...

Page 722: ...ol registers ADC12CTL0 and ADC12CTL1 The core is enabled with the ADC12ON bit The ADC12 can be turned off when not in use to save power With few exceptions the ADC12 control bits can only be modified when ENC 0 ENC must be set to 1 before any conversion can take place Conversion Clock Selection The ADC12CLK is used both as the conversion clock and to generate the sampling period when the pulse sam...

Page 723: ...ution method When the inputs are internally switched the switching action may cause transients on the input signal These transients decay and settle before causing errant conversion Figure 26 2 Analog Multiplexer R 100 Ohm ESD Protection ADC12MCTLx 0 3 Input Ax Analog Port Selection The ADC12 inputs are multiplexed with the port P6 pins which are digital CMOS gates When analog signals are applied ...

Page 724: ... to bias the recommended storage capacitors If the internal reference generator is not used for the conversion the storage capacitors are not required Note Reference Decoupling Approximately 200 μA is required from any reference used by the ADC12 while the two LSBs are being resolved during a conversion A parallel combination of 10 μF and 0 1 μF capacitors is recommended for any reference used as ...

Page 725: ...mpling is active The high to low SAMPCON transition starts the analog to digital conversion which requires 13 ADC12CLK cycles Two different sample timing methods are defined by control bit SHP extended sample mode and pulse mode Extended Sample Mode The extended sample mode is selected when SHP 0 The SHI signal directly controls SAMPCON and defines the length of the sample period tsample When SAMP...

Page 726: ...timer keeps SAMPCON high after synchronization with AD12CLK for a programmed interval tsample The total sampling time is tsample plus tsync See Figure 26 4 The SHTx bits select the sampling time in 4x multiples of ADC12CLK SHT0x selects the sampling time for ADC12MCTL0 to 7 and SHT1x selects the sampling time for ADC12MCTL8 to 15 Figure 26 4 Pulse Sample Mode Start Sampling Stop Sampling Conversio...

Page 727: ...ge VS for an accurate 12 bit conversion Figure 26 5 Analog Input Equivalent Circuit RS RI VS VC MSP430 CI VI VI Input voltage at pin Ax VS External source voltage RS External source resistance RI Internal MUX on input resistance CI Input capacitance VC Capacitance charging voltage The resistance of the source RS and RI affect tsample The following equation can be used to calculate the minimum samp...

Page 728: ...annels or repeat sequence of channels CSTARTADDx points to the first ADC12MCTLx location to be used in a sequence A pointer not visible to software is incremented automatically to the next ADC12MCTLx in a sequence when each conversion completes The sequence continues until an EOS bit in ADC12MCTLx is processed this is the last control byte processed When conversion results are written to a selecte...

Page 729: ...iggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each conversion Figure 26 6 Single Channel Single Conversion Mode ADC12 off x CSTARTADDx Wait for Enable ENC Wait for Trigger Sample Input Channel Defined in ADC12MCTLx ENC ENC SHSx 0 and ENC 1 or and ADC12SC SAMPCON SAMPCON 1 Convert SAMPCON ENC 0 ENC 0 12 x ADC12CLK Conversion Completed Result Stored Int...

Page 730: ...ces can be triggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each sequence Figure 26 7 Sequence of Channels Mode ADC12 off x CSTARTADDx Wait for Enable ENC Wait for Trigger Sample Input Channel Defined in ADC12MCTLx ENC ENC SHSx 0 and ENC 1 or and ADC12SC SAMPCON SAMPCON 1 Convert SAMPCON 12 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMx A...

Page 731: ...d is overwritten by the next conversion Figure 26 8 shows repeat single channel mode Figure 26 8 Repeat Single Channel Mode ADC12 off x CSTARTADDx Wait for Enable ENC Wait for Trigger Sample Input Channel Defined in ADC12MCTLx ENC ENC SHSx 0 and ENC 1 or and ADC12SC SAMPCON SAMPCON 1 Convert SAMPCON 12 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMx ADC12IFG x is Set 1 x ADC12CLK ADC1...

Page 732: ...ce of channels mode Figure 26 9 Repeat Sequence of Channels Mode ADC12 off x CSTARTADDx Wait for Enable ENC Wait for Trigger Sample Input Channel Defined in ADC12MCTLx ENC ENC SHSx 0 and ENC 1 or and ADC12SC SAMPCON SAMPCON 1 SAMPCON 12 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMx ADC12IFG x is Set 1 x ADC12CLK ADC12ON 1 CONSEQx 11 MSC 1 and SHP 1 and ENC 1 or EOS x 0 ENC 0 and EOS...

Page 733: ...t Stopping Conversions Stopping ADC12 activity depends on the mode of operation The recommended ways to stop an active conversion or conversion sequence are Resetting ENC in single channel single conversion mode stops a conversion immediately and the results are unpredictable For correct results poll the busy bit until reset before clearing ENC Resetting ENC during repeat single channel operation ...

Page 734: ... than 30 μs The temperature sensor offset error can be large and may need to be calibrated for most applications See device specific data sheet for parameters Selecting the temperature sensor automatically turns on the on chip reference generator as a voltage source for the temperature sensor However it does not enable the VREF output or affect the reference selections for the conversion The refer...

Page 735: ...t voltages of the A D converter The connections shown in Figure 26 11 help avoid this In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result A noise free design using separate analog and digital ground planes with a single point connection is recommend to achieve high accuracy Figure 26 11 AD...

Page 736: ...mine which enabled ADC12 interrupt source requested an interrupt The highest priority enabled ADC12 interrupt generates a number in the ADC12IV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled ADC12 interrupts do not affect the ADC12IV value Any access read or write of the ADC12IV registe...

Page 737: ...check immediately if a higher prioritized interrupt occurred during the processing of ADC12IFG15 This saves nine cycles if another ADC12 interrupt is pending Interrupt handler for ADC12 INT_ADC12 Enter Interrupt Service Routine 6 ADD ADC12IV PC Add offset to PC 3 RETI Vector 0 No interrupt 5 JMP ADOV Vector 2 ADC overflow 2 JMP ADTOV Vector 4 ADC timing overflow 2 JMP ADM0 Vector 6 ADC12IFG0 2 Vec...

Page 738: ... ADC12MEM11 Read write 0156h Unchanged ADC12 memory 12 ADC12MEM12 Read write 0158h Unchanged ADC12 memory 13 ADC12MEM13 Read write 015Ah Unchanged ADC12 memory 14 ADC12MEM14 Read write 015Ch Unchanged ADC12 memory 15 ADC12MEM15 Read write 015Eh Unchanged ADC12 memory control 0 ADC12MCTL0 Read write 080h Reset with POR ADC12 memory control 1 ADC12MCTL1 Read write 081h Reset with POR ADC12 memory co...

Page 739: ... when ENC 0 SHT1x Bits 15 12 Sample and hold time These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM8 to ADC12MEM15 SHT0x Bits 11 8 Sample and hold time These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM0 to ADC12MEM7 SHTx Bits ADC12CLK cycles 0000 4 0001 8 0010 16 0011 32 0100 64 0101 96 0110 128 0111 192 1000 2...

Page 740: ... Reference on ADC12ON Bit 4 ADC12 on 0 ADC12 off 1 ADC12 on ADC12OVIE Bit 3 ADC12MEMx overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Overflow interrupt disabled 1 Overflow interrupt enabled ADC12 TOVIE Bit 2 ADC12 conversion time overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Conversion time overflow interrupt disabled 1 Conversio...

Page 741: ...RTADDx is 0 to 0Fh corresponding to ADC12MEM0 to ADC12MEM15 SHSx Bits 11 10 Sample and hold source select 00 ADC12SC bit 01 Timer_A OUT1 10 Timer_B OUT0 11 Timer_B OUT1 SHP Bit 9 Sample and hold pulse mode select This bit selects the source of the sampling signal SAMPCON to be either the output of the sampling timer or the sample input signal directly 0 SAMPCON signal is sourced from the sample in...

Page 742: ...2 busy This bit indicates an active sample or conversion operation 0 No operation is active 1 A sequence sample or conversion is active ADC12MEMx ADC12 Conversion Memory Registers 15 14 13 12 11 10 9 8 0 0 0 0 Conversion Results r0 r0 r0 r0 rw rw rw rw 7 6 5 4 3 2 1 0 Conversion Results rw rw rw rw rw rw rw rw Conversion Results Bits 15 0 The 12 bit conversion results are right justified Bit 11 is...

Page 743: ... VREF and VR AVSS 010 VR VeREF and VR AVSS 011 VR VeREF and VR AVSS 100 VR AVCC and VR VREF VeREF 101 VR VREF and VR VREF VeREF 110 VR VeREF and VR VREF VeREF 111 VR VeREF and VR VREF VeREF INCHx Bits 3 0 Input channel select 0000 A0 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 VeREF 1001 VREF VeREF 1010 Temperature sensor 1011 AVCC AVSS 2 1100 AVCC AVSS 2 A12 on FG43x and FG461x d...

Page 744: ...Interrupt disabled 1 Interrupt enabled ADC12IFG ADC12 Interrupt Flag Register 15 14 13 12 11 10 9 8 ADC12 IFG15 ADC12 IFG14 ADC12 IFG13 ADC12 IFG12 ADC12 IFG11 ADC12 IFG10 ADC12 IFG9 ADC12 IFG8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 ADC12 IFG7 ADC12 IFG6 ADC12 IFG5 ADC12 IFG4 ADC12 IFG3 ADC12 IFG2 ADC12 IFG1 ADC12 IFG0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IFGx Bits 15 0 AD...

Page 745: ...DC12IFG0 008h ADC12MEM1 interrupt flag ADC12IFG1 00Ah ADC12MEM2 interrupt flag ADC12IFG2 00Ch ADC12MEM3 interrupt flag ADC12IFG3 00Eh ADC12MEM4 interrupt flag ADC12IFG4 010h ADC12MEM5 interrupt flag ADC12IFG5 012h ADC12MEM6 interrupt flag ADC12IFG6 014h ADC12MEM7 interrupt flag ADC12IFG7 016h ADC12MEM8 interrupt flag ADC12IFG8 018h ADC12MEM9 interrupt flag ADC12IFG9 01Ah ADC12MEM10 interrupt flag ...

Page 746: ...26 28 ADC12 ...

Page 747: ...6 bit sigma delta analog to digital converter This chapter describes the SD16 The SD16 module is implemented in the MSP430FE42x and MSP430F42x devices Topic Page 27 1 SD16 Introduction 27 2 27 2 SD16 Operation 27 4 27 3 SD16 Registers 27 19 Chapter 27 ...

Page 748: ...256 Additional filtering can be done in software Features of the SD16 include 16 bit sigma delta architecture Up to 3 independent simultaneously sampling ADC channels The number of channels is device dependent see the device specific data sheet Up to 8 multiplexed differential analog inputs per channel The number of inputs is device dependent refer to device specific data sheet Software selectable...

Page 749: ...NCHx 001 010 011 100 101 110 111 PGA 1 32 2nd Order ΣΔ Modulator SD16GAINx SD16DF SD16LP SD16PRE1 7 0 SD16SC Conversion Control to prior channel SD16OSRx SD16SNGL SD16MEM1 Reference Reference Conversion Control from next channel Channel 2 SD16VMIDON SD16REFON Temperature sensor Temperature sensor fM Reference 1 2V SD16GRP Group Start Conversion Logic AVSS A1 1 A1 0 A1 2 A1 3 A1 4 A1 5 A1 6 A1 7 Re...

Page 750: ...cific data sheet for full scale input specifications 27 2 3 Voltage Reference Generator The SD16 module has a built in 1 2V reference that can be used for each SD16 channel and is enabled by the SD16REFON bit When using the internal reference an external 100nF capacitor connected from VREF to AVSS is recommended to reduce noise The internal reference voltage can be used off chip when SD16VMIDON 1 ...

Page 751: ...t one of eight differential input pairs of the analog multiplexer The gain for each PGA is selected by the SD16GAINx bits A total of six gain settings are available During conversion any modification to the SD16INCHx and SD16GAINx bits will become effective with the next decimation step of the digital filter After these bits are modified the next three conversions may be invalid due to the settlin...

Page 752: ...e voltage RS External source resistance CS Sampling capacitance RS 1 k VS CS AVCC 2 The maximum sampling frequency fS may be calculated from the minimum settling time tSettling of the sampling circuit given by tSettling w RS 1kW CS lnǒGAIN 217 VAx VREF Ǔ where fS 1 2 tSettling and VAx maxǒŤAVCC 2 VS Ť ŤAVCC 2 VS ŤǓ with VS and VS referenced to AVSS CS varies with the gain setting as shown in Table...

Page 753: ...e modulator frequency fM to the sample frequency fS Figure 27 3 shows the filter s frequency response for an OSR of 32 The first filter notch is at fS fM OSR The notch frequency can be adjusted by changing the modulator frequency fM using SD16SSELx and SD16DIVx and the oversampling rate using SD16OSRx The digital filter for each enabled ADC channel completes the decimation of the digital bit strea...

Page 754: ...ficient filter settling time for a full scale change at the ADC input If the step occurs synchronously to the decimation of the digital filter the valid data will be available on the third conversion An asynchronous step will require one additional conversion before valid data is available Figure 27 4 Digital Filter Step Response and Conversion Points 1 2 3 4 1 0 0 2 0 4 0 6 0 8 1 0 0 2 0 4 0 6 0 ...

Page 755: ... bits of the digital filter output When SD16LSBTOG 1 the SD16LSBACC bit is automatically toggled each time the corresponding channel s SD16MEMx register is read This allows the complete digital filter output result to be read with two read accesses of SD16MEMx Setting or clearing SD16LSBTOG does not change SD16LSBACC until the next SD16MEMx access Figure 27 5 Used Bits of Digital Filter Output 0 4...

Page 756: ...hown in Table 27 2 The data format is selected by the SD16DF bit Table 27 2 Data Format SD16DF Format Analog Input SD16MEMx Digital Filter Output OSR 256 Unipolar FSR FFFF FFFFFF 0 Unipolar Offset ZERO 8000 800000 0 Offset Binary FSR 0000 000000 Bipolar FSR 7FFF 7FFFFF 1 Bipolar Two s ZERO 0000 000000 1 Two s complement FSR 8000 800000 Independent of SD16OSRx setting SD16LSBACC 0 Figure 27 6 shows...

Page 757: ...utomatically be cleared after conversion completion Clearing SD16SC before the conversion is completed immediately stops conversion of the selected channel the channel is powered down and the corresponding digital filter is turned off The value in SD16MEMx can change when SD16SC is cleared It is recommended that the conversion data in SD16MEMx be read prior to clearing SD16SC to avoid reading an i...

Page 758: ...g conversion of all channels in the group with its SD16SC bit The SD16GRP bit of the master channel is always 0 The SD16GRP bit of last channel in SD16 has no function and is always 0 When SD16SNGL 1 for a channel in a group single conversion mode is selected A single conversion of that channel will occur synchronously when the master channel SD16SC bit is set The SD16SC bit of all channels in the...

Page 759: ...ing digital filters are turned off Values in SD16MEMx can change when SD16SC is cleared It is recommended that the conversion data in SD16MEMx be read prior to clearing SD16SC to avoid reading an invalid result Figure 27 8 shows grouped channel operation for three SD16 channels Channel 0 is configured for single conversion mode SD16SNGL 1 and channels 1 and 2 are in continuous conversion mode SD16...

Page 760: ...on cycle following each write to SD16PREx Following conversions are not delayed After modifying SD16PREx the next write to SD16PREx should not occur until the next conversion cycle is completed otherwise the conversion results may be incorrect The accuracy of the result for the delayed conversion cycle using SD16PREx is dependent on the length of the delay and the frequency of the analog signal be...

Page 761: ...he preload delay for that channel will be reintroduced Figure 27 11 shows the re synchronization and preload delays for channels in a group It is recommended that SD16PREx 0 for the master channel to maintain a consistent delay between the master and remaining channels in the group when they are re enabled Figure 27 11 Preload and Channel Synchronization Channel 0 SD16SNGL 0 SD16GRP 1 Time Convers...

Page 762: ...ny used external reference In this case the SD16VMIDON bit may be set to minimize the affects of the contention on the conversion The typical temperature sensor transfer function is shown in Figure 27 12 When switching inputs of an SD16 channel to the temperature sensor adequate delay must be provided using SD16INTDLYx to allow the digital filter to settle and assure that conversion results are va...

Page 763: ...ags The SD16IFG flags are reset by reading the associated SD16MEMx register or by clearing the flags in software SD16OVIFG bits can only be reset with software If another interrupt is pending after servicing of an interrupt another interrupt is generated For example if the SD16OVIFG and one or more SD16IFG interrupts are pending when the interrupt service routine accesses the SD16IV register the S...

Page 764: ...nel 2 SD16IFG shows a way to check immediately if a higher prioritized interrupt occurred during the processing of the ISR This saves nine cycles if another SD16 interrupt is pending Interrupt handler for SD16 INT_SD16 Enter Interrupt Service Routine 6 ADD SD16IV PC Add offset to PC 3 RETI Vector 0 No interrupt 5 JMP ADOV Vector 2 ADC overflow 2 JMP ADM0 Vector 4 CH_0 SD16IFG 2 JMP ADM1 Vector 6 C...

Page 765: ...ol SD16INCTL0 Read write 0B0h Reset with PUC SD16 Channel 0 Preload SD16PRE0 Read write 0B8h Reset with PUC SD16 Channel 1 Control SD16CCTL1 Read write 0104h Reset with PUC SD16 Channel 1 Conversion Memory SD16MEM1 Read write 0114h Reset with PUC SD16 Channel 1 Input Control SD16INCTL1 Read write 0B1h Reset with PUC SD16 Channel 1 Preload SD16PRE1 Read write 0B9h Reset with PUC SD16 Channel 2 Cont...

Page 766: ...D16 0 Low power mode is disabled 1 Low power mode is enabled The maximum clock frequency for the SD16 is reduced SD16DIVx Bits 7 6 SD16 clock divider 00 1 01 2 10 4 11 8 SD16SSELx Bits 5 4 SD16 clock source select 00 MCLK 01 SMCLK 10 ACLK 11 External TACLK SD16 VMIDON Bit 3 VMID buffer on 0 Off 1 On SD16 REFON Bit 2 Reference generator on 0 Reference off 1 Reference on SD16OVIE Bit 1 SD16 overflow...

Page 767: ...BTOG Bit 7 LSB toggle This bit when set causes SD16LSBACC to toggle each time the SD16MEMx register is read 0 SD16LSBACC does not toggle with each SD16MEMx read 1 SD16LSBACC toggles with each SD16MEMx read SD16 LSBACC Bit 6 LSB access This bit allows access to the upper or lower 16 bits of the SD16 conversion result 0 SD16MEMx contains the most significant 16 bits of the conversion 1 SD16MEMx cont...

Page 768: ...annel x Input Control Register 7 6 5 4 3 2 1 0 SD16INTDLYx SD16GAINx SD16INCHx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 SD16 INTDLYx Bits 7 6 Interrupt delay generation after conversion start These bits select the delay for the first interrupt after conversion start 00 Fourth sample causes interrupt 01 Third sample causes interrupt 10 Second sample causes interrupt 11 First sample causes interrupt ...

Page 769: ...n Results r r r r r r r r Conversion Result Bits 15 0 Conversion Results The SD16MEMx register holds the upper or lower 16 bits of the digital filter output depending on the SD16LSBACC bit SD16PREx SD16 Channel x Preload Register 7 6 5 4 3 2 1 0 Preload Value rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 SD16 Preload Value Bits 7 0 SD16 digital filter preload value ...

Page 770: ...V Contents Interrupt Source Interrupt Flag Interrupt Priority 000h No interrupt pending 002h SD16MEMx overflow SD16CCTLx SD16OVIFG Highest 004h SD16_0 Interrupt SD16CCTL0 SD16IFG 006h SD16_1 Interrupt SD16CCTL1 SD16IFG 008h SD16_2 Interrupt SD16CCTL1 SD16IFG 00Ah Reserved 00Ch Reserved 00Eh Reserved 010h Reserved Lowest When an SD16 overflow occurs the user must check all SD16CCTLx SD16OVIFG flags...

Page 771: ...a delta analog to digital converter ADC This chapter describes the SD16_A The SD16_A module is implemented in the MSP430F42x0 MSP430FG42x0 and MSP430F47x devices Topic Page 28 1 SD16_A Introduction 28 2 28 2 SD16_A Operation 28 5 28 3 SD16_A Registers 28 22 Chapter 28 ...

Page 772: ...ude 16 bit sigma delta architecture Up to seven independent simultaneously sampling ADC channels The number of channels is device dependent see the device specific data sheet Up to eight multiplexed differential analog inputs per channel The number of inputs is device dependent see the device specific data sheet Software selectable on chip reference voltage generation 1 2 V Software selectable int...

Page 773: ... fM Reference 1 2V AVSS SD16XDIVx Divider 1 3 16 48 SD16XOSR 1 0 SD16UNI 1 AVCC SD16INCHx 101 Temp sensor PGA 1 32 5R R 5R Reference SD16_A Control Block SD16SC Conversion Control to prior channel SD16SGNL Conversion Control from next channel SD16GRP Group Start Conversion Logic SD16PRE1 Channel 1 Temperature and Vcc Sense ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Channel 0 ÌÌÌÌÌ...

Page 774: ...CC VREF Divider 1 2 4 8 A0 000 SD16INCHx 001 010 011 100 101 110 111 A1 A2 A3 A4 A5 A6 2ndOrder ΣΔ Modulator SD16GAINx SD16DF SD16LP SD16SC SD16OSRx SD16SNGL SD16MEM0 Reference A7 SD16VMIDON SD16REFON fM Reference 1 2V Start Conversion Logic AVSS SD16XDIVx Divider 1 3 16 48 SD16XOSR BUF SD16BUFx 1 0 SD16UNI 1 AVCC SD16INCHx 101 Temp sensor PGA 1 32 5R R 5R Reference ...

Page 775: ...fic data sheet for full scale input specifications 28 2 3 Voltage Reference Generator The SD16_A module has a built in 1 2V reference It can be used for each SD16_A channel and is enabled by the SD16REFON bit When using the internal reference an external 100nF capacitor connected from VREF to AVSS is recommended to reduce noise The internal reference voltage can be used off chip when SD16VMIDON 1 ...

Page 776: ...uitry for the associated pin See the device specific data sheet for pin diagrams During conversion any modification to the SD16INCHx and SD16GAINx bits will become effective with the next decimation step of the digital filter After these bits are modified the next three conversions may be invalid due to the settling time of the digital filter This can be handled automatically with the SD16INTDLYx ...

Page 777: ...n all devices see the device specific data sheet When the buffers are used RS does not affect the sampling frequency fS However when the buffers are not used or are not present on the device the maximum sampling frequency fS may be calculated from the minimum settling time tSettling of the sampling circuit given by tSettling w RS 1kW CS lnǒGAIN 217 VAx VREF Ǔ where fS 1 2 tSettling and VAx maxǒŤAV...

Page 778: ... frequency fM to the sample frequency fS Figure 28 4 shows the filter s frequency response for an OSR of 32 The first filter notch is at fS fM OSR The notch s frequency can be adjusted by changing the modulator s frequency fM using SD16SSELx and SD16DIVx and the oversampling rate using the SD16OSRx and SD16XOSR bits The digital filter for each enabled ADC channel completes the decimation of the di...

Page 779: ...ufficient filter settling time for a full scale change at the ADC input If the step occurs synchronously to the decimation of the digital filter the valid data will be available on the third conversion An asynchronous step will require one additional conversion before valid data is available Figure 28 5 Digital Filter Step Response and Conversion Points 1 2 3 4 1 0 0 2 0 4 0 6 0 8 1 0 0 2 0 4 0 6 ...

Page 780: ... time SD16MEMx is read This allows the complete digital filter output result to be read with two reads of SD16MEMx Setting or clearing SD16LSBTOG does not change SD16LSBACC until the next SD16MEMx access Figure 28 6 Used Bits of Digital Filter Output 0 4 8 12 16 20 24 1 5 3 2 6 9 7 23 22 21 19 18 17 15 14 13 11 10 28 27 26 25 29 OSR 512 LSBACC 0 SD16UNI 0 0 4 8 12 16 20 24 1 5 3 2 6 9 7 23 22 21 1...

Page 781: ...UNI 1 0 4 8 12 16 20 24 1 5 3 2 6 9 7 23 22 21 19 18 17 15 14 13 11 10 28 27 26 25 29 OSR 128 LSBACC 0 SD16UNI 0 0 4 8 12 16 20 24 1 5 3 2 6 9 7 23 22 21 19 18 17 15 14 13 11 10 28 27 26 25 29 OSR 128 LSBACC 1 SD16UNI 0 0 4 8 12 16 20 24 1 5 3 2 6 9 7 23 22 21 19 18 17 15 14 13 11 10 28 27 26 25 29 OSR 128 LSBACC 0 SD16UNI 1 0 4 8 12 16 20 24 1 5 3 2 6 9 7 23 22 21 19 18 17 15 14 13 11 10 28 27 26...

Page 782: ... shown in Table 28 3 The data format is selected by the SD16DF and SD16UNI bits Table 28 3 Data Format SD16UNI SD16DF Format Analog Input SD16MEMx Digital Filter Output OSR 256 Bipolar FSR FFFF FFFFFF 0 0 Bipolar Offset ZERO 8000 800000 0 0 Offset Binary FSR 0000 000000 Bipolar FSR 7FFF 7FFFFF 0 1 Bipolar Two s ZERO 0000 000000 0 1 Two s Compliment FSR 8000 800000 FSR FFFF FFFFFF 1 0 Unipolar ZERO...

Page 783: ...and the conversion result The data formats are illustrated Figure 28 7 Input Voltage vs Digital Output Input Voltage SD16MEMx VFSR V FSR 7FFFh 8000h Bipolar Output 2 s complement Input Voltage SD16MEMx VFSR V FSR FFFFh 8000h Bipolar Output Offset Binary 0000h 0000h Input Voltage SD16MEMx VFSR V FSR FFFFh Unipolar Output 0000h ...

Page 784: ... any other channels The SD16SC bit will automatically be cleared after conversion completion Clearing SD16SC before the conversion is completed immediately stops conversion of the selected channel the channel is powered down and the corresponding digital filter is turned off The value in SD16MEMx can change when SD16SC is cleared It is recommended that the conversion data in SD16MEMx be read prior...

Page 785: ...ing conversion of all channels in the group with its SD16SC bit The SD16GRP bit of the master channel is always 0 The SD16GRP bit of last channel in SD16_A has no function and is always 0 When SD16SNGL 1 for a channel in a group single conversion mode is selected A single conversion of that channel will occur synchronously when the master channel SD16SC bit is set The SD16SC bit of all channels in...

Page 786: ...ding digital filters are turned off Values in SD16MEMx can change when SD16SC is cleared It is recommended that the conversion data in SD16MEMx be read prior to clearing SD16SC to avoid reading an invalid result Figure 28 9 shows grouped channel operation for three SD16_A channels Channel 0 is configured for single conversion mode SD16SNGL 1 and channels 1 and 2 are in continuous conversion mode S...

Page 787: ...rsion cycle following each write to SD16PREx Following conversions are not delayed After modifying SD16PREx the next write to SD16PREx should not occur until the next conversion cycle is completed otherwise the conversion results may be incorrect The accuracy of the result for the delayed conversion cycle using SD16PREx is dependent on the length of the delay and the frequency of the analog signal...

Page 788: ...l the preload delay for that channel will be reintroduced Figure 28 12 shows the re synchronization and preload delays for channels in a group It is recommended that SD16PREx 0 for the master channel to maintain a consistent delay between the master and remaining channels in the group when they are re enabled Figure 28 12 Preload and Channel Synchronization Channel 0 SD16SNGL 0 SD16GRP 1 Time Conv...

Page 789: ...any used external reference In this case the SD16VMIDON bit may be set to minimize the affects of the contention on the conversion The typical temperature sensor transfer function is shown in Figure 28 13 When switching inputs of an SD16_A channel to the temperature sensor adequate delay must be provided using SD16INTDLYx to allow the digital filter to settle and assure that conversion results are...

Page 790: ...16IFG flags The SD16IFG flags are reset by reading the associated SD16MEMx register or by clearing the flags in software SD16OVIFG bits can only be reset with software If another interrupt is pending after servicing of an interrupt another interrupt is generated For example if the SD16OVIFG and one or more SD16IFG interrupts are pending when the interrupt service routine accesses the SD16IV regist...

Page 791: ...nnel 2 SD16IFG shows a way to check immediately if a higher prioritized interrupt occurred during the processing of the ISR This saves nine cycles if another SD16_A interrupt is pending Interrupt handler for SD16_A INT_SD16 Enter Interrupt Service Routine 6 ADD SD16IV PC Add offset to PC 3 RETI Vector 0 No interrupt 5 JMP ADOV Vector 2 ADC overflow 2 JMP ADM0 Vector 4 CH_0 SD16IFG 2 JMP ADM1 Vecto...

Page 792: ...eset with PUC SD16_A Channel 2 Input Control SD16INCTL2 Read write 0B2h Reset with PUC SD16_A Channel 2 Preload SD16PRE2 Read write 0BAh Reset with PUC SD16_A Channel 3 Control SD16CCTL3 Read write 0108h Reset with PUC SD16_A Channel 3 Conversion Memory SD16MEM3 Read write 0118h Reset with PUC SD16_A Channel 3 Input Control SD16INCTL3 Read write 0B3h Reset with PUC SD16_A Channel 3 Preload SD16PRE...

Page 793: ...t selects a reduced speed reduced power mode 0 Low power mode is disabled 1 Low power mode is enabled The maximum clock frequency for the SD16_A is reduced SD16DIVx Bits 7 6 SD16_A clock divider 00 1 01 2 10 4 11 8 SD16SSELx Bits 5 4 SD16_A clock source select 00 MCLK 01 SMCLK 10 ACLK 11 External TACLK SD16 VMIDON Bit 3 VMID buffer on 0 Off 1 On SD16 REFON Bit 2 Reference generator on 0 Reference ...

Page 794: ...uffer mode 00 Buffer disabled 01 Slow speed current 10 Medium speed current 11 High speed current SD16UNI Bit 12 Unipolar mode select 0 Bipolar mode 1 Unipolar mode SD16XOSR Bit 11 Extended oversampling ratio This bit along with the SD16OSRx bits select the oversampling ratio See SD16OSRx bit description for settings SD16SNGL Bit 10 Single conversion mode select 0 Continuous conversion mode 1 Sing...

Page 795: ...utomatically reset when the corresponding SD16MEMx register is read or may be cleared with software 0 No interrupt pending 1 Interrupt pending SD16SC Bit 1 SD16_A start conversion 0 No conversion start 1 Start conversion SD16GRP Bit 0 SD16_A group Groups SD16_A channel with next higher channel Not used for the last channel Reserved in MSP430F42x0 and MSP430FG42x0 devices 0 Not grouped 1 Grouped SD...

Page 796: ...ilable selections are device dependent See the device specific data sheet 000 Ax 0 A0 on MSP430F42x0 and MSP430FG42x0 devices 001 Ax 1 A1 on MSP430F42x0 and MSP430FG42x0 devices 010 Ax 2 A2 on MSP430F42x0 and MSP430FG42x0 devices 011 Ax 3 A3 on MSP430F42x0 and MSP430FG42x0 devices 100 Ax 4 A4 on MSP430F42x0 and MSP430FG42x0 devices 101 AVCC AVSS 11 110 Temperature Sensor 111 Short for PGA offset m...

Page 797: ...ts of the digital filter output depending on the SD16LSBACC bit SD16PREx SD16_A Channel x Preload Register Not present on MSP430F42x0 and MSP430FG42x0 7 6 5 4 3 2 1 0 Preload Value rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 SD16 Preload Value Bits 7 0 SD16_A digital filter preload value SD16AE SD16_A Analog Input Enable Register Only present on MSP430F42x0 and MSP430FG42x0 7 6 5 4 3 2 1 0 SD16AE7 SD1...

Page 798: ...rrupt Source Interrupt Flag Interrupt Priority 000h No interrupt pending 002h SD16MEMx overflow SD16CCTLx SD16OVIFG Highest 004h SD16_A Channel 0 Interrupt SD16CCTL0 SD16IFG 006h SD16_A Channel 1 Interrupt SD16CCTL1 SD16IFG 008h SD16_A Channel 2 Interrupt SD16CCTL2 SD16IFG 00Ah SD16_A Channel 3 Interrupt SD16CCTL3 SD16IFG 00Ch SD16_A Channel 4 Interrupt SD16CCTL4 SD16IFG 00Eh SD16_A Channel 5 Inte...

Page 799: ...og converter This chapter describes the DAC12 Two DAC12 modules are implemented in the MSP430FG43x and MSP430FG461x devices Only DAC12_0 is implemented in MSP430x42x0 devices Topic Page 29 1 DAC12 Introduction 29 2 29 2 DAC12 Operation 29 5 29 3 DAC12 Registers 29 11 Chapter 29 ...

Page 800: ...bration option for offset correction Synchronized update capability for multiple DAC12s Note Multiple DAC12 Modules Some devices may integrate more than one DAC12 module In the case where more than one DAC12 is present on a device the multiple DAC12 modules operate identically Throughout this chapter nomenclature appears such as DAC12_xDAT or DAC12_xCTL to describe register names When this occurs ...

Page 801: ...AT DAC12_1Latch TB2 TA1 DAC12DF DAC12RES AVSS 00 01 10 11 00 01 10 11 00 01 10 11 VeREF VREF DAC12DF DAC12RES Latch Bypass DAC12LSELx TB2 TA1 00 01 10 11 00 01 10 11 Latch Bypass DAC12IR To ADC12 module DAC12_1DAT Updated DAC12_0DAT Updated 1 0 0 1 DAC12ENC 0 1 DAC12ENC DAC12GRP 1 0 DAC12GRP DAC12SREFx AVSS 00 01 10 11 x3 3 DAC12_1OUT DAC12AMPx 3 x3 DAC12IR 3 Group Load Logic DAC12AMPx 3 ...

Page 802: ...x42x0 Devices DAC12_0 DAC12_0OUT 1 2V reference from SD16 DAC12SREFx VR VR DAC12_0DAT DAC12_0Latch AVSS 00 01 10 11 VREF DAC12DF DAC12RES DAC12LSELx TB2 TA1 00 01 10 11 00 01 10 11 Latch Bypass DAC12IR DAC12_0DAT Updated 0 1 ENC 1 0 DAC12GRP x3 3 DAC12AMPx 3 DAC12IR AVCC ...

Page 803: ...12_xDAT 256 In 8 bit mode the maximum useable value for DAC12_xDAT is 0FFh and in 12 bit mode the maximum useable value for DAC12_xDAT is 0FFFh Values greater than these may be written to the register but all leading bits are ignored DAC12 Port Selection On MSP430FG43x and MSP430FG461x devices the DAC12 outputs are multiplexed with the port P6 pins and ADC12 analog inputs and also the VeREF and P5...

Page 804: ...imized settling time vs power consumption Eight combinations are selected using the DAC12AMPx bits In the low low setting the settling time is the slowest and the current consumption of both buffers is the lowest The medium and high settings have faster settling times but the current consumption increases See the device specific data sheet for parameters 29 2 3 Updating the DAC12 Voltage Output Th...

Page 805: ...2 Bit Straight Binary Mode Full Scale Output 0 0FFFh 0 Output Voltage DAC Data When using 2s compliment data format the range is shifted such that a DAC12_xDAT value of 0800h 0080h in 8 bit mode results in a zero output voltage 0000h is the mid scale output voltage and 07FFh 007Fh for 8 bit mode is the full scale voltage output as shown in Figure 29 4 Figure 29 4 Output Voltage vs DAC12 Data 12 Bi...

Page 806: ... the output amplifier has a positive offset a digital input of zero does not result in a zero output voltage The DAC12 output voltage reaches the maximum output level before the DAC12 data reaches the maximum code This is shown in Figure 29 6 Figure 29 6 Positive Offset Vcc Output Voltage 0 DAC Data Full Scale Code The DAC12 has the capability to calibrate the offset voltage of the output amplifie...

Page 807: ...rouped both DAC12_xDAT registers must be written to before the outputs update even if data for one or both of the DACs is not changed Figure 29 7 shows a latch update timing example for grouped DAC12_0 and DAC12_1 When DAC12_0 DAC12GRP 1 and both DAC12_x DAC12LSELx 0 and either DAC12ENC 0 neither DAC12 will update Figure 29 7 DAC12 Group Update Example Timer_A3 Trigger DAC12_0 DAC12GRP DAC12_0 DAC...

Page 808: ...IFG flags to determine the source of the interrupt The DAC12IFG bit is set when DAC12LSELx 0 and DAC12 data is latched from the DAC12_xDAT register into the data latch When DAC12LSELx 0 the DAC12IFG flag is not set A set DAC12IFG bit indicates that the DAC12 is ready for new data If both the DAC12IE and GIE bits are set the DAC12IFG generates an interrupt request The DAC12IFG flag is not reset aut...

Page 809: ... 2 DAC12 Registers Register Short Form Register Type Address Initial State DAC12_0 control DAC12_0CTL Read write 01C0h Reset with POR DAC12_0 data DAC12_0DAT Read write 01C8h Reset with POR DAC12_1 control DAC12_1CTL Read write 01C2h Reset with POR DAC12_1 data DAC12_1DAT Read write 01CAh Reset with POR ...

Page 810: ..._0 output available internally and externally DAC12 SREFx Bits 14 13 DAC12 select reference voltage MSP430FG43x and MSP430FG461x Devices 00 VREF 01 VREF 10 VeREF 11 VeREF MSP430x42x0 Devices 00 AVCC 01 AVCC 10 VREF internal from SD16_A or external 11 VREF internal from SD16_A or external DAC12 RES Bit 12 DAC12 resolution select 0 12 bit resolution 1 8 bit resolution DAC12 LSELx Bits 11 10 DAC12 lo...

Page 811: ...off output high Z 001 Off DAC12 off output 0 V 010 Low speed current Low speed current 011 Low speed current Medium speed current 100 Low speed current High speed current 101 Medium speed current Medium speed current 110 Medium speed current High speed current 111 High speed current High speed current DAC12DF Bit 4 DAC12 data format 0 Straight binary 1 2s complement DAC12IE Bit 3 DAC12 interrupt e...

Page 812: ...12 core DAC12 Data Bits 11 0 DAC12 data DAC12 Data Format DAC12 Data 12 bit binary The DAC12 data are right justified Bit 11 is the MSB 12 bit 2s complement The DAC12 data are right justified Bit 11 is the MSB sign 8 bit binary The DAC12 data are right justified Bit 7 is the MSB Bits 11 to 8 are don t care and do not affect the DAC12 core 8 bit 2s complement The DAC12 data are right justified Bit ...

Page 813: ...scans sensors and measures linear or rotational motion This chapter describes the Scan interface The Scan IF is implemented in the MSP430FW42x devices Topic Page 30 1 Scan IF Introduction 30 2 30 2 Scan IF Operation 30 4 30 3 Scan IF Registers 30 35 Chapter 30 ...

Page 814: ... are passed into the processing state machine The processing state machine is used to analyze and count rotation or motion The timing state machine controls the analog front end and the processing state machine The Scan IF features include Support for different types of LC sensors Measurement of sensor signal envelope Measurement of sensor signal oscillation amplitude Support for resistive sensors...

Page 815: ...ate Machine TSM w oscillator Processing State Machine PSM Analog Input Multiplexer Interrupt Request Rotation Data ACLK SMCLK Analog Front End AFE SIFCH1 SIFCH0 SIFCH2 SIFCH3 SIFCI0 SIFCOM SIFVSS SIFCI SIFCI1 SIFCI2 SIFCI3 Scan I F To Timer_A DAC 10 Bit w RAM 1 2 Excit S H AVCC ...

Page 816: ...alog front end provides sensor excitation and measurement The analog front end is automatically controlled by the timing state machine according to the information in the timing state machine table The analog front end block diagram is shown in Figure 30 2 Note Timing State Machine Signals Throughout this chapter signals from the TSM are noted in the signal name with tsm For example The signal SIF...

Page 817: ...H1x SIF2OUT SIF3OUT SIFTCH0OUT SIF1OUT SIF0OUT SIFTCH1OUT SIFCAINV SIFRSON tsm 2 Output Stage SIFCHx tsm 2 Sync 00 01 10 11 00 01 10 11 S H S H S H SIFVSS SIFCOM Sample Hold 2 DAC 10 Bit SIFDACR0 SIFDACR1 SIFDACR2 SIFDACR3 SIFDACR4 SIFDACR5 SIFDACR6 SIFDACR7 SIFSH SIFCA tsm SIFDAC tsm SIFDACON SIFCI0 SIFCI1 SIFCI2 SIFCI3 S H VMID SIFVCC2 00 01 10 11 Excit Excit Excit Excit SIFTEN Excitation SIFLCE...

Page 818: ...ther channels are automatically disabled Only the selected channel is excited and measured The excitation period should be long enough to overload the LC sensor slightly After excitation the SIFCHx input is released from ground when SIFEX tsm 0 and the LC sensor can oscillate freely The oscillations will swing above the positive supply but will be clipped by the protection diode to the positive su...

Page 819: ...ion and Sample And Hold Circuitry SIFEX tsm SIFVSS 1 1 1 0 SIFCH0 SIFCOM Sample and Hold SIFLCEN tsm SIFTEN 1 0 Damping Excitation VSS 1 0 Excitation 00 VMID Gen SIFVCC2 1 2 AVCC 1 0 00 01 10 11 00 01 10 11 to Comparator From Channel Select Logic SIFSH ...

Page 820: ...n be measured sequentially using the channel select logic the comparator and the DAC The selected SIFCHx input can be modeled as an RC low pass filter during the sampling time tsample as shown below in Figure 30 4 An internal MUX on input resistance Ri SIFCHx max 3 kΩ in series with capacitor CSCH SIFCHx max 7 pF is seen by the resistor divider The capacitor voltage VC must be charged to within LS...

Page 821: ...STS1 tsm signal select between the SIFxOUT output bits and the SIFTCHxOUT output bits for the comparator output as described in Table 30 2 TESTDX is controlled by the SIFTESTD bit Table 30 2 Selected Output Bits TESTDX SIFCH tsm SIFTESTS1 tsm Selected Output Bit 0 00 X SIF0OUT 0 01 X SIF1OUT 0 10 X SIF2OUT 0 11 X SIF3OUT 1 X 0 SIFTCH0OUT 1 X 1 SIFTCH1OUT When TESTDX 0 the SIFCHx tsm signals select...

Page 822: ...o observe the envelope function of sensors The output logic is enabled by the SIFRSON tsm signal When the comparator output is high while SIFRSON 1 an internal latch is set Otherwise the latch is reset The latch output is written into the selected output bit with the rising edge of the SIFSTOP tsm signal as shown in Figure 30 5 Figure 30 5 Analog Front End Output Timing SIFRSON tsm Comparator Outp...

Page 823: ...it will be low The comparator output can be inverted by setting SIFCAINV The comparator output is stored in the selected output bit and processed by the processing state machine to detect motion and direction The comparator and the DAC are turned on and off by SIFCA tsm signal and the SIFDAC tsm signal when needed by the timing state machine They can also be permanently enabled by setting the SIFC...

Page 824: ...the sensors Table 30 3 Selected DAC Registers Selected Output Bit SIFxOUT Last Value of SIFxOUT DAC Register Used SIF0OUT 0 SIFDACR0 1 SIFDACR1 SIF1OUT 0 SIFDACR2 1 SIFDACR3 SIF2OUT 0 SIFDACR4 1 SIFDACR5 SIF3OUT 0 SIFDACR6 1 SIFDACR7 Figure 30 6 Analog Hysteresis With DAC Registers DAC Output Voltage Input Voltage SIF1OUT Time SIFDACR2 SIFDACR3 When TESTDX 1 the SIFDACR6 and SIFDACR7 registers are...

Page 825: ...he Analog Front End TimerA Output Stage SIF0OUT SIF1OUT SIF2OUT SIF3OUT SIFS1x SIFO0 SIFO1 SIFO2 SIFTESTS1 tsm SIFEX tsm SIFCS 11 10 01 00 SIFS2x 11 10 01 00 1 0 1 0 0 1 0 Comparator Output When SIFCS 1 the SIFEX tsm signal and the comparator output can be selected as inputs to different Timer1_A5 capture compare registers This can be used to measure the time between excitation of a sensor and the...

Page 826: ...e reset and the internal oscillator is stopped The TSM block diagram is shown in Figure 30 8 The TSM begins at SIFTSM0 and ends when the TSM encounters a SIFTSMx state with a set SIFTSTOP bit When a state with a set SIFSTOP bit is reached the state counter is reset to zero and state processing stops State processing re starts at SIFTSM0 with the next start condition when SIFTSMRP 0 or immediately ...

Page 827: ... SIFSTOP SIFACLK SIFREPEAT0 SIFREPEAT1 SIFREPEAT2 SIFREPEAT3 SIFREPEAT4 SIFCHx tsm SIFLCOFF tsm SIFEX tsm SIFCA tsm SIFCLKON tsm SIFRSON tsm SIFTESTS1 tsm SIFDAC tsm SIFSTOP tsm Set_SIFIFG1 ACLK SIFREPEATx SIFACLK SIFFLLON tsm SIFTSM1 SIFTSM22 SIFEN SIFTSMRP SIFCLKEN SMCLK SIFOSC SIFCNT3 Out Enable ACLK SIFCLK SIFCLKGON SIFCLKEN SIFDIV2x SIFDIV1x 0 1 Divider 1 2 4 8 Divider 1 2 4 8 SIFDIV3Ax Divid...

Page 828: ...of the AFE The TSM controls the AFE with the SIFCHx SIFLCEN SIFEX SIFCA SIFRSON SIFTESTS1 SIFDAC and SIFSTOP bits When any of these bits are set their corresponding signal s SIFCHx tsm SIFLCEN tsm SIFEX tsm SIFCA tsm SIFRSON tsm SIFTESTS1 tsm SIFDAC tsm and SIFSTOP tsm are high for the duration of the state Otherwise the corresponding signal s are low TSM State Duration The duration of each state ...

Page 829: ...ings of the MSP430 The TSM internal oscillator generates a nominal frequency of 1MHz or 4MHz selected by the SIFFNOM bit and can be tuned in nominal 5 steps from 40 to 35 with the SIFCLKFQx The frequency and the steps differ from device to device See the device specific data sheet for parameters The TSM internal oscillator frequency can be measured with ACLK When SIFCLKEN 1 and SIFCLKGON 1 SIFCNT3...

Page 830: ...n as shown in Figure 30 9 At the end of the test cycle the SIFTESTD bit is automatically cleared The TESTDX signal is active during the test cycle to control input and output channel selection TESTDX is generated after the SIFTESTD bit is set and the next TSM sequence completes Figure 30 9 Test Cycle Insertion TSM Start Signal Divided ACLK Normal Cycle Normal Cycle Test Cycle Normal Cycle Normal C...

Page 831: ... 00402h SIFTSM7 01812h SIFTSM8 00952h SIFTSM9 00200h The example also shows the affects of the clock synchronization when switching between SIFCLK and ACLK In state SIFTSM6 SIFACLK is set whereas in the previous state and the successive state SIFACLK is cleared The waveform shows the duration of SIFTSM6 is less than one ACLK cycle and the duration of state SIFTSM7 is up to one SIFCLK period longer...

Page 832: ...emory flash ROM or RAM The processing state machine measures rotation and controls interrupt generation based on the inputs from the timing state machine and the analog front end The PSM vector SIFPSMV must to be initialized to point to the PSM state table Multiple state tables are possible by reconfiguring the SIFPSMV to different tables as needed The PSM block diagram is shown in Figure 30 11 ...

Page 833: ... 10 01 00 11 10 01 00 Set_SIFIFG5 Set_SIFIFG7 Set_SIFIFG3 Δ1 Δ4 Δ64 Δ256 SIFSTOP tsm SIFCNTRST PSM Operation At the falling edge of the SIFSTOP tsm signal the PSM moves the current state byte from the PSM state table to the PSM output latch The PSM has one dedicated channel of direct memory access DMA so all accesses to the PSM state table s are done automatically with no CPU intervention The curr...

Page 834: ...ulation Bits 0 and 3 5 Q0 Q3 Q4 Q5 and if enabled by SIFQ6EN and SIFQ7EN bits 6 and 7 Q6 Q7 are used together with the signals S1 and S2 to calculate the next state When SIFQ6EN 1 Q6 is used in the next state calculation When SIFQ6EN 1 and SIFQ7EN 1 Q7 is used in the next state calculation The next state is Q7 Q6 Q5 Q4 Q3 Q0 S2 S1 When Q7 0 the PSM state is updated by the falling edge of the SIFST...

Page 835: ...1 decrements on a transition to a state where bit Q2 is set When SIFCNT1ENP 1 SIFCNT1 increments on a transition to a state where bit Q1 is set When both bits SIFCNT1ENM and SIFCNT1ENM are set and both bits Q1 and Q2 are set on a state transition SIFCNT1 does not increment or decrement SIFCNT2 decrements based on Q2 When SIFCNT2EN 1 SIFCNT2 decrements on a transition to a state where bit Q2 is set...

Page 836: ...1 0 S2 1 S1 0 S2 0 State 00 00000000 State 10 00000000 State 11 00000010 State 01 00000000 S1 0 S2 0 S1 0 S2 1 S1 1 S2 0 S1 1 S2 1 S1 1 S2 0 S1 0 S2 1 Simplest State Machine Example SIMPLEST_PSM db 000h State 00 State Table Index 0 db 000h State 01 State Table Index 1 db 000h State 10 State Table Index 2 db 002h State 11 State Table Index 3 PSM_INIT MOV SIMPLEST_PSM SIFPSMV Init PSM vector MOV SIF...

Page 837: ... calculate the next state the bits Q5 Q3 and Q0 of the state 01 table entry together with the S1 and S2 signals are combined to form the next state Q7 Q6 Q5 Q4 Q3 Q0 S2 S1 0 0 0 0 0 0 1 1 The state table entry for state 11 is loaded at the next state transition Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 0 0 0 0 0 0 1 0 Q1 is set in state 11 so SIFCNT1 will be incremented More complex state machines can be built by c...

Page 838: ... to SIFDEBUG After writing the lower two bits reading the SIFDEBUG contents gives the user different information After writing 00h to SIFDEBUG reading SIFDEBUG shows the last address read by the PSM After writing 01h to SIFDEBUG reading SIFDEBUG shows the index of the TSM and the PSM bits Q7 to Q0 After writing 02h to SIFDEBUG reading SIFDEBUG shows the TSM output After writing 03h to SIFDEBUG rea...

Page 839: ...sing edge of the SIFSTOP tsm signal SIFIFG2 SIFIFG2 is set at the start of a TSM sequence SIFIFG3 SIFIFG3 is set at different count intervals of the SIFCNT1 counter selected with the SIFIS1x bits SIFIFG4 SIFIFG4 is set at different count intervals of the SIFCNT2 counter selected with the SIFIS2x bits SIFIFG5 SIFIFG5 is set when the PSM transitions to a state with Q6 set SIFIFG6 SIFIFG6 is set when...

Page 840: ...nd observing the resulting oscillation The oscillation is either damped or un damped by the rotating disk The oscillation is always decaying because of energy losses but it decays faster when the damping material on the disk is within the field of the LC sensor as shown in Figure 30 14 The LC oscillations can be measured with the oscillation test or the envelope test Figure 30 14 LC Sensor Oscilla...

Page 841: ... the reference level the comparator will output a pulse train corresponding to the oscillations and the selected AFE output bit will 1 The measurement timing and reference level depend on the sensors and the system and should be chosen such that the difference between the damped and the undamped amplitude is maximized Figure 30 15 shows the connections for the oscillation test Figure 30 15 LC Sens...

Page 842: ...d the capture compare registers for Timer1_A5 are used to time the decay of the oscillation envelope The PSM is not used for the envelope test When the sensors are connected to the individual SIFCIx inputs as shown in Figure 30 16 the comparator reference level can be adjusted for each sensor individually When all sensors are connected to the SIFCI input as shown in Figure 30 17 only one comparato...

Page 843: ...eration 30 31 Scan IF Figure 30 17 LC Sensor Connections For The Envelope Test Power Supply Terminals SIFCI0 SIFCI SIFCI1 SIFCI2 SIFCI3 470 nF AVCC DVCC DVSS AVSS SIFVSS 470 nF SIFCOM SIFCH1 SIFCH0 SIFCH2 SIFCH3 ...

Page 844: ...ating different divider voltages The divider voltages are sampled with the sample and hold circuits After the signals have settled the dividers may be switched off to prevent current flow and reduce power consumption The DAC is used to set the reference level for the comparator and the comparator detects if the sampled voltage is above or below the reference level If the sampled voltage is above t...

Page 845: ...al waveform Figure 30 19 Sensor Position and Quadrature Signals Sensor B Signal S2 Sensor A Signal S1 A B A A A A B B B B A B Sensor A Signal S1 Sensor B Signal S2 Sensor B Signal S2 Sensor A Signal S1 90 45 01 11 10 00 01 11 10 Damping or dark area Quadrature decoding requires knowing the previous quadrature pair S1 and S2 as well as the current pair Comparing these two pairs will tell the direct...

Page 846: ...tate table entries for the processing state machine as shown in Table 30 8 Table 30 8 Quadrature Decoding PSM Table Previous Current Movement State Table Entry Quadrature Pair Quadrature Pair Q6 Q2 Q1 Q3 Q0 Pair Pair Error 1 1 Current Quadrature Pair Byte Code 00 00 No Rotation 0 0 0 0 0 000h 00 01 Turns right 1 0 0 1 0 1 003h 00 10 Turns left 1 0 1 0 1 0 00Ch 00 11 Error 1 0 0 1 1 049h 01 00 Turn...

Page 847: ...ead write 01CEh Unchanged Scan IF TSM 0 SIFTSM0 Read write 01D0h Unchanged Scan IF TSM 1 SIFTSM1 Read write 01D2h Unchanged Scan IF TSM 2 SIFTSM2 Read write 01D4h Unchanged Scan IF TSM 3 SIFTSM3 Read write 01D6h Unchanged Scan IF TSM 4 SIFTSM4 Read write 01D8h Unchanged Scan IF TSM 5 SIFTSM5 Read write 01DAh Unchanged Scan IF TSM 6 SIFTSM6 Read write 01DCh Unchanged Scan IF TSM 7 SIFTSM7 Read writ...

Page 848: ...ead SIFDEBUG shows the last address read by the PSM 01 When read SIFDEBUG shows the value of the TSM state pointer and the PSM bits Q7 Q0 10 When read SIFDEBUG shows the contents of the current SIFTSMx register 11 When read SIFDEBUG shows the currently selected DAC register and its contents SIFDEBUG Scan IF Debug Register Read Mode After 00h Is Written 15 14 13 12 11 10 9 8 Last Address Read by PS...

Page 849: ...Index Bits 12 8 When SIFDEBUG is read after 01h is written to it these bits show the TSM register pointer index PSM Bits Bits 7 0 When SIFDEBUG is read after 01h is written to it these bits show the PSM bits Q7 to Q0 SIFDEBUG Scan IF Debug Register Read Mode After 02h Is Written 15 14 13 12 11 10 9 8 Current SIFTSMx Register Contents r r r r r r r r 7 6 5 4 3 2 1 0 Current SIFTSMx Register Content...

Page 850: ...fter 03h is written to SIFDEBUG this bit is always read as zero DAC Register Bits 14 12 When SIFDEBUG is read after 03h is written to it these bits show which DAC register is currently selected to control the DAC Unused Bits 11 10 Unused After 03h is written to SIFDEBUG these bits are always read as zero DAC Data Bits 9 0 When SIFDEBUG is read after 03h is written to it these bits show value of th...

Page 851: ...set when SIFEN 0 or if read when SIFCNTRST 1 SIFCNT1x Bits 7 0 SIFCNT1 These bits are the SIFCNT1 counter SIFCNT1 is reset when SIFEN 0 or if read when SIFCNTRST 1 SIFPSMV Scan IF Processing State Machine Vector Register 15 14 13 12 11 10 9 8 SIFPSMVx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 SIFPSMVx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 SIFPSMVx Bits 15 0 SIF PSM vector These bit...

Page 852: ...his bit is set when the PSM transitions to a state with a set Q6 bit SIFIFG5 must be reset with software 0 No interrupt pending 1 Interrupt pending SIFIFG4 Bit 6 SIF interrupt flag 4 This bit is set by the SIFCNT2 counter conditions selected with the SIFIS2x bits SIFIFG4 must be reset with software 0 No interrupt pending 1 Interrupt pending SIFIFG3 Bit 5 SIF interrupt flag 3 This bit is set by the...

Page 853: ...are 0 No interrupt pending 1 Interrupt pending SIFTESTD Bit 1 Test cycle insertion Setting this bit inserts a test cycle between TSM cycles SIFTESTD is automatically reset at the end of the test cycle 0 No test cycle inserted 1 Test cycle inserted between TSM cycles SIFEN Bit 0 Scan interface enable Setting this bit enables the Scan IF 0 Scan IF disabled 1 Scan IF enabled ...

Page 854: ... This bit selects groups of signals for the comparator input 0 Comparator input is one of the SIFCHx channels selected with the channel select logic 1 Comparator input is one of the SIFCIx channels selected with the channel select logic and the SIFCISEL and SIFCACI3 bits SIFCISEL Bit 11 Comparator input select This bit is used with the SIFCACI3 bit to select the comparator input when SIFCAX 1 0 Co...

Page 855: ...X 0 Comparator input is SIFCI1 when SIFCAX 1 10 Comparator input is SIFCH2 when SIFCAX 0 Comparator input is SIFCI2 when SIFCAX 1 11 Comparator input is SIFCH3 when SIFCAX 0 Comparator input is SIFCI3 when SIFCAX 1 SIFTCH0x Bits 3 2 These bits select the comparator input for test channel 0 00 Comparator input is SIFCH0 when SIFCAX 0 Comparator input is SIFCI0 when SIFCAX 1 01 Comparator input is S...

Page 856: ...F1OUT is the S1 source 10 SIF2OUT is the S1 source 11 SIF3OUT is the S1 source SIFIS2x Bits 11 10 SIFIFG4 interrupt flag source 00 SIFIFG4 is set with each count of SIFCNT2 01 SIFIFG4 is set if SIFCNT2 modulo 4 0 10 SIFIFG4 is set if SIFCNT2 modulo 64 0 11 SIFIFG4 is set when SIFCNT2 decrements from 01h to 00h SIFIS1x Bits 9 8 SIFIFG3 interrupt flag source 00 SIFIFG3 is set with each count up or d...

Page 857: ...t when SIF0OUT is reset 010 SIFIFG0 is set when SIF1OUT is set 011 SIFIFG0 is set when SIF1OUT is reset 100 SIFIFG0 is set when SIF2OUT is set 101 SIFIFG0 is set when SIF2OUT is reset 110 SIFIFG0 is set when SIF3OUT is set 111 SIFIFG0 is set when SIF3OUT is reset SIF3OUT Bit 3 AFE output bit 3 SIF2OUT Bit 2 AFE output bit 2 SIF1OUT Bit 1 AFE output bit 1 SIF0OUT Bit 0 AFE output bit 0 ...

Page 858: ...en it is read SIFCNT2EN Bit 14 SIFCNT2 enable 0 SIFCNT2 is disabled 1 SIFCNT2 is enabled SIFCNT1 ENM Bit 13 SIFCNT1 decrement enable 0 SIFCNT1 decrement is disabled 1 SIFCNT1 decrement is enabled SIFCNT1 ENP Bit 12 SIFCNT1 increment enable 0 SIFCNT1 increment is disabled 1 SIFCNT1 increment is enabled SIFQ7EN Bit 11 Q7 enable This bit enables bit Q7 for the next PSM state calculation when SIFQ6EN ...

Page 859: ...ger The division rate is SIFDIV3Ax SIFDIV3Bx 000 001 010 011 100 101 110 111 000 2 6 10 14 18 22 26 30 001 6 18 30 42 54 66 78 90 010 10 30 50 70 90 110 130 150 011 14 42 70 98 126 154 182 210 100 18 54 90 126 162 198 234 270 101 22 66 110 154 198 242 286 330 110 26 78 130 182 234 286 338 390 111 30 90 150 210 270 330 390 450 SIFDIV2x Bits 3 2 ACLK divider These bits select the ACLK division 00 1 ...

Page 860: ... SIFCLKFQx Bits 6 3 Internal oscillator frequency adjust These bits are used to adjust the internal oscillator frequency Each increase or decrease of the SIFCLKFQx bits increases or decreases the internal oscillator frequency by approximately 5 0000 Minimum frequency 1000 Nominal frequency 1111 Maximum frequency SIFFNOM Bit 2 Internal oscillator nominal frequency 0 4 MHz 1 1 MHz SIFCLKG ON Bit 1 I...

Page 861: ...er Registers 15 14 13 12 11 10 9 8 0 0 0 0 0 0 DAC Data r0 r0 r0 r0 r0 r0 rw rw 7 6 5 4 3 2 1 0 DAC Data rw rw rw rw rw rw rw rw Unused Bits 15 10 Unused These bits are always read as zero and when written do not affect the DAC output DAC Data Bits 9 0 10 bit DAC data ...

Page 862: ...source is ACLK SIFSTOP Bit 9 This bit indicates the end of the TSM sequence The duration of this state is always one high frequency clock period regardless of the SIFACLK and SIFREPEATx settings 0 TSM sequence continues with next state 1 End of TSM sequence SIFDAC Bit 8 TSM DAC on This bit turns the DAC on during this state when SIFDACON 0 0 DAC off during this state 1 DAC on during this state SIF...

Page 863: ...IFEX Bit 3 Excitation and sample and hold This bit together with the SIFSH and SIFTEN bits enables the excitation transistor or samples the input voltage during this state SIFLCEN must be set to 1 when SIFEX 1 0 Excitation transistor disabled when SIFSH 0 and SIFTEN 1 Sampling disabled when SIFSH 1 and SIFTEN 0 1 Excitation transistor enabled when SIFSH 0 and SIFTEN 1 Sampling enabled when SIFSH 1...

Page 864: ...egardless of the SIFSTOP tsm signal and Q7 is used in the next state calculation Q6 Bit 6 When Q6 1 SIFIFG5 will be set When SIFQ6EN 1 Q6 will be used in the next state calculation Q5 Bit 5 Bit 5 of the next state Q4 Bit 4 Bit 4 of the next state Q3 Bit 3 Bit 3 of the next state Q2 Bit 2 When Q2 1 SIFCNT1 decrements if SIFCNT1ENM 1 and SIFCNT2 decrements if SIFCNT2EN 1 Q1 Bit 1 When Q1 1 SIFCNT1 i...

Page 865: ...edded Emulation Module EEM This chapter describes the Embedded Emulation Module EEM that is implemented in all MSP430 flash devices Topic Page 31 1 EEM Introduction 31 2 31 2 EEM Building Blocks 31 4 31 3 EEM Configurations 31 6 Chapter 31 ...

Page 866: ...eakpoints on CPU register write accesses MAB MDB and CPU register access triggers can be combined to form up to eight device dependent complex triggers breakpoints Trigger sequencing device dependent Storage of internal bus and control signals using an integrated trace buffer device dependent Clock control for timers communication peripherals and other modules on a global device level or on a per ...

Page 867: ...Module EEM Figure 31 1 Large Implementation of the Embedded Emulation Module EEM CPU Stop Trigger Blocks MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7 CPU0 CPU1 0 Trigger Sequencer AND Matrix Combination Triggers 1 2 3 4 5 6 7 Start Stop State Storage OR OR ...

Page 868: ...re either the MAB or the MDB with a given value Depending on the implemented EEM the comparison can be or The comparison can also be limited to certain bits with the use of a mask The mask is either bit wise or byte wise depending upon the device In addition to selecting the bus and the comparison the condition under which the trigger is active can be selected The conditions include read access wr...

Page 869: ...orage Internal Trace Buffer The state storage function uses a built in buffer to store MAB MDB and CPU control signal information ie read write or instruction fetch in a nonintrusive manner The built in buffer can hold up to eight entries The flexible configuration allows the user to record the information of interest very efficiently 31 2 4 Clock Control The EEM provides device dependent flexible...

Page 870: ... Low byte 2 High byte 1 Low byte 2 High byte All 16 or 20 bits CPU Register Write Triggers 0 1 1 2 Combination Triggers 2 4 6 8 Sequencer No No Yes Yes State Storage No No No Yes In general the following features can be found on any 4xx device At least two MAB MDB triggers supporting J Distinction between CPU DMA read and write accesses J or comparison in XS only At least two trigger combination r...

Page 871: ...ice and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyer...

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