Texas Instruments MSP430x4xx Family, User Manual

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USCI Operation: UART Mode
19-15 Universal Serial Communication Interface, UART Mode
Figure 19−9. Glitch Suppression, USCI Activated
URXDx
URXS
t
τ
Majority Vote Taken
19.3.8 USCI Transmit Enable
The USCI module is enabled by clearing the UCSWRST bit and the transmitter
is ready and in an idle state. The transmit baud rate generator is ready but is
not clocked nor producing any clocks.
A transmission is initiated by writing data to UCAxTXBUF. When this occurs,
the baud rate generator is enabled and the data in UCAxTXBUF is moved to
the transmit shift register on the next BITCLK after the transmit shift register
is empty. UCAxTXIFG is set when new data can be written into UCAxTXBUF.
Transmission continues as long as new data is available in UCAxTXBUF at the
end of the previous byte transmission. If new data is not in UCAxTXBUF when
the previous byte has transmitted, the transmitter returns to its idle state and
the baud rate generator is turned off.
19.3.9 UART Baud Rate Generation
The USCI baud rate generator is capable of producing standard baud rates
from non-standard source frequencies. It provides two modes of operation
selected by the UCOS16 bit.
Low-Frequency Baud Rate Generation
The low-frequency mode is selected when UCOS16 = 0. This mode allows
generation of baud rates from low frequency clock sources (e.g. 9600 baud
from a 32768Hz crystal). By using a lower input frequency the power
consumption of the module is reduced. Using this mode with higher
frequencies and higher prescaler settings will cause the majority votes to be
taken in an increasingly smaller window and thus decrease the benefit of the
majority vote.
In low-frequency mode the baud rate generator uses one prescaler and one
modulator to generate bit clock timing. This combination supports fractional
divisors for baud rate generation. In this mode, the maximum USCI baud rate
is one-third the UART source clock frequency BRCLK.
Timing for each bit is shown in Figure 19−10. For each bit received, a majority
vote is taken to determine the bit value. These samples occur at the N/2 − 1/2,
N/2, and N/2 + 1/2 BRCLK periods, where N is the number of BRCLKs per
BITCLK.