Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
Fig. 5-30. Simple logic diagram of processor clock.
Instruction Register and Decoder/Timing Control. Dur
ing the instruction fetch (the first one or more machine cy
cles), successive bytes of an instruction are loaded from the
program memory into the instruction register. The contents
of this register are then passed to the decoder and timing
logic. This block decodes the byte(s) and generates the ma
chine states and control signals that affect execution of the
instruction. The number of machine cycles this takes de
pends on the instruction and addressing mode.
Data and Address Buffers. These tri-state buffers iso
late the 6800 internal buses from the external
microcomputer bus.
Three-State Control (TSC). This input is tied low so the
address buffer and read/write line are always enabled.
Read/Write (R/W). This output sets the direction of data
flow—high when the 6800 is reading data and low when the
6800 is writing data. It is also high between read and write
operations.
Valid Memory Address (VMA). This output is asserted
high when the 6800 places a valid address on the
microcomputer bus. It enables the memory address
decoders.
Clocks. The two-phase TTL-level clock signals synchro
nize 6800 operation. A machine cycle is defined as the inter
val between two successive positive-going transitions of the
ψ
1
clock signal.
HALT. This input is unused (tied high through a pull-up).
Data Bus Enable (DBE). This input is paired with the
Φ2
clock input so the data buffer is enabled during
φ2
of the
machine cycle.
Figure 5-32 shows a read and a write cycle on the
microcomputer bus. This illustrates how the control signals
are used to control data transfers on the bus.
REV AUG 1981
5-79
