Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
In this configuration, only the low-order DAC uses the inter
nal operational amplifier. Thus, the low-order unit operates
in the voltage output mode, and the high-order unit operates
in the current output mode. The two devices feed the two
inputs of preamplifier U1044, which sums the two inputs,
amplifies the sum, and sends it through the switching circuit
to the integrator.
Since the DAC units generate the dc voltage that tunes
the entire instrument, noise and extraneous signals must be
kept at a minimum. Thus, each tune voltage is provided with
an isolated ground system, U1042A/U1042B for the Coarse
Tune voltage converter, and U3041A/U3041B for the Fine
Tune voltage converter.
Track/Hold Amplifiers
Since the coarse and fine amplifiers are identical in oper
ation, only the coarse amplifier is described here. The ampli
fier consists of preamplifier U1044, control transistor
Q2044, storage gate FET Q2046, and integrator amplifier
U2046.
The output of the low-order DAC (U1024) is fed through
input resistor R1048 to the inverting input of preamplifier
U1044. The current output of the high-order DAC U1030, is
fed directly into the non-inverting input of the preamplifier.
Feedback resistor R1044 establishes the gain of the stage
at about 10,000 (ratio of R1044 to R1046). The combination
of CR1046, CR1045, and R1047 in the feedback circuit, pre
vents the output from swinging to extreme voltages with
large input signals. Thus, whenever the output exceeds
about one volt in either direction, one of the diodes conducts
and connects R1047 and R1045 across the feedback path
to reduce the gain of the stage to about unity. The output
signal from the preamplifier is connected to the source of
storage gate FET Q2046. The gate of this device is con
trolled by transistor Q2044. Normally the circuit is tracking,
so line Q
8
(B7) from U2022 is low and Q2044 is conducting.
CR2042 is cut off since the voltage drop across R2043
holds the gate of Q2046 at about —0.3 V. (The -0 .3 V
back bias on the source-gate junction reduces memory
slewing while switching modes.) Q2044 holds the diode
back-biased as long as the transistor continues to conduct.
This permits Q2046 to pass the signal from the preamplifier
output to the integrator input.
Integrator U2046 tracks the preamplifier output during
track mode and serves as the inverting amplifier for the
feedback system shown in Fig. 5-28. Under normal circum
stances the incoming signal is routed through R2046. To
improve the amplifier’s slewing rate, CR2044 and CR2045
conduct to connect R2047 in parallel with R2046 when sig
nals in excess of one volt are applied. This speeds up the
response of the circuit when large scale tuning changes are
required.
When the hold mode is selected, line Q
8
(B7) of U2022
moves high, Q2044 cuts off and CR2044 pulls the gate of
Q2046 low enough to cut off the FET. This disconnects the
preamplifier from the integrator which then maintains the
charge on C2046 during the approximation routine.
COARSE TUNE RANGE adjustment R1032 is connected
across pins 16 and 18 of U1030. It compensates for the
different resistance values inside the DAC. This variation is
more serious in the higher-order DAC owing to its greater
effect on the output.
Write-Back Circuits
These circuits consist of amplifier U2044 and U3045,
plus enabling transistors Q1039 and Q2043. Since both are
identical, only the coarse circuit is described.
Following the command to shift to the hold mode, the
microcomputer will interrogate the circuit to see if the DAC
output and the stored voltage match. It does this by pulling
ADDRESS 80 high. This causes Q1039 to conduct, which in
turn furnishes U2044 with operating current. The output of
U2044 is at zero volts when the two input voltages match. If
the loop error voltage is high, U2044 will pull down on DATA
BUS line 7. This informs the microcomputer whether the bit
just set is too large or too small. The output of U2044 is
open-collector, so it has no effect on the data line when it is
not pulling the line low.
PHASELOCK SYSTEM
(Option 03)
Functional Description
The phaselock section, which is included when Option 03
is part of the instrument, is a frequency control system that
substantially improves the stabilization of the 1st LO (first
Local Oscillator).
The phaselock system consists of two frequency servo
loops, called the outer loop and inner loop. Operation of the
inner loop is as follows: The 100 MHz reference signal from
the 3rd Converter is applied to the Synthesizer, where it is
first divided by two, then sent to the phaselock circuits to be
used as a reference frequency. It is further divided to
25 MHz in the synthesizer circuits and applied to the
N
circuits which reduce the signal to a reference frequency
(depending on the
N number), between 32 and 94 kHz
and applied to the Offset Mixer, where it is compared with
the mixer output. The original 25 MHz is also applied to the
Offset Mixer.
5-70
REV JUN 1983
