Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
tains only one differential amplifier and acts as a buffer.
When the loop is first acquiring lock, such as at power-on,
the nominal 25 MHz IF may be as high as 34 MHz. Two
stages of amplification are necessary to ensure enough gain
for the phase/frequency detector to drive the IF back to
25 MHz; the buffer is necessary to provide ECL levels to the
detector.
The second input to the phase/frequency detector is the
100 MHz frequency from the reference oscillator in the 3rd
converter via coaxial connector P235. This signal is applied
through two amplifier stages, U1022A and U1022B, to a
divide-by-four circuit, U1036A and U1036B. These two flip-
flops divide the 100 MHz frequency to 25 MHz for applica
tion to the phase/frequency detector. (Two stages of
amplification are used to isolate the 100 MHz reference bus
from signals, generated in the local oscillator section of the
2nd Converter.) This stable 25 MHz reference output is
used to lock the difference frequency from the harmonic
mixer at 25 MHz.
The phase/frequency detector effectively measures the
phase difference between the 25 MHz reference and the IF
from the harmonic mixer, and determines the correction
voltage that is to be applied to the 719 MHz VCO. This cir
cuit consists of two D-type flip-flops, U2047A and U2047B,
and a differential amplifier stage used as a NAND-gate
(U1044A). The 25 MHz reference signal from the frequency
divider is applied to the clock input of flip-flop U2047A; the
nominal 25 MHz signal from the harmonic mixer is applied
to the clock input of flip-flop U2047B. The rising edge of the
input signal to each flip-flop causes the Q outputs to return
to the low level only after both flip-flops have been clocked.
If the harmonic mixer output frequency is below 25 MHz,
(or if its phase lags that of the 25 MHz reference) the Q
output of flip-flop U2047A will be high longer than that of
flip-flop U2047B. If the harmonic mixer output frequency is
above 25 MHz (or if its phase leads), the opposite will be
true. When the two flip-flops are clocked at the same fre
quency and phase, the two outputs will be high for the same
amount of time. From the two flip-flops, the Q outputs are
applied to compensation amplifier U3053, a differential am
plifier that determines which output is high for a longer time.
Compensation amplifier U3053 provides part of the loop
gain to ensure that the gain will be high enough to cause the
719 MHz oscillator to track the sweep of the 2182 MHz ref
erence oscillator. In addition, the compensation amplifier
limits the loop bandwidth to 100 kHz to make certain that
the loop will not oscillate. Note that the differential inputs to
the amplifier each include a lowpass RC filter (R3041 and
C3042 for the minus input; R2048 and C2055 for the plus
input) to attenuate the undesired high frequency clock
pulses from the phase/frequency detector.
The nominal swing of the U3053 output is from +12 to
— 12 volts. Since the compensation amplifier is capable of
considerably more output swing than is needed to control
the oscillator, a voltage divider is used to limit the output
and reduce amplifier related noise. This voltage divider, con
sisting of resistors R2053, R2054, R3051, and R3052, re
duces the possible ±12 volt swing to +5 V to +12 V, as
required by varactor diode CR1011. Nominal voltage in a
locked condition is +6.75 to +7.5 V.
Thus, dependent upon whether the harmonic mixer out
put frequency is above or below 25 MHz, the correction
voltage applied to diode CR1011 is higher or lower than
nominal to drive the oscillator frequency in the required
direction.
Front Panel 2nd Local Oscillator Output Circuit
A portion of each 2nd LO output signal is sent to the
front panel 2nd LO OUT connector. This output provides
signal for external accessory equipment, such as a tracking
generator. Each local oscillator (719 MHz and 2182 MHz)
output is applied through power dividers to a power combin
er for application to the 2nd LO OUT connector.
The 719 MHz oscillator frequency is applied from a pow
er splitter (R3027, R3028, R3029) through a 1 GHz low-
pass filter (C3025, C2024, C1023, C1021, and three printed
inductors), to the power combiner (R2024, R2025, R2026),
and the front panel 2nd LO OUTPUT. The 2182 MHz oscil
lator signal is applied through a power splitter (R1021,
R1022, R1023), a 2.2 GHz band-pass filter (consisting of
coupled 1/4 wavelength printed lines) to the power divider
(R2024, R2025, R2026) and the front panel 2nd LO
OUTPUT.
Both 2nd local oscillator signals, 2182 MHz and
719 MHz, are present at the front panel when the 829 MHz
2nd Converter is selected.
719 MHz Output Circuit
The 719 MHz 2nd Local Oscillator signal is applied
through divider resistors R2021, R2023, and R2024 to iso
lation amplifier Q2021. Q2021 boosts the signal level from
about 0 dBm to +12 dBm to drive the 829 MHz mixer. The
output of the amplifier includes a 3 dB attenuator (consisting
of resistors R2027, R2026, and R2029), to ensure a 50 Ω
non-reflective source impedance. The signal level at test
point J2026 is typically —6 dBm.
R E V FEB 1983
5-19
