Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
before the log amplifier, a digital-to-analog converter is used
to effectively move the display up or down the log curve.
This process is called “offset” and it accomplishes the
same effect as moving the POSITION control, except that
the display on screen does not change, only the signal level
required to reach the reference level changes.
Since the non-programmable 492 allows selection of ei
ther 10dB per division or 2dB per division, and the
programmable 492P allows selection of 1 to 15 dB per divi
sion, the system must allow the gain to change while keep
ing the top of the screen constant, and must allow any
16 dB segment (in 2 dB/div mode) to be displayed. Nominal
ly, the Log Amplifier operates with 0 dB or at the top of the
screen.
The output of preamplifier U4090A is equivalent to
20 mV/dB. Full screen is always 2.2 V. At 2.2 V, the output
of variable gain log amplifier U4090B is 0 volt, the only volt
age at which the resistors in the switching network in the
feedback circuit of preamplifier U4090B can be switched
without changing the output voltage. (The switching net
work will be described later.) The 2.2 volt output of U4090A
is adjusted during calibration to full screen by Input Ref Lvl
(input reference level) potentiometer R4071.
From U4090B, the output signal is applied through FET
Q5090 (if that transistor has been turned on by data bit 6
when 6 is high or a 1) to output operational amplifier
U4090C, then through emitter follower Q4100 to the Video
Processor via the front panel LOG CAL potentiometer. The
Output Ref Lvl (output reference level) potentiometer,
R4081 in the input circuit to U4090C, is used to adjust the
output to provide a full screen display after Input Reference
Level potentiometer R4071 is set for no change in the out
put of U4090B when switching from 10 to 2 dB or vice
versa.
As an aid to understanding the system operation, it is
probably useful to understand the basic calibration se
quence that includes the above two controls. The sequence
is as follows:
1) the digital-to-analog converter output voltage is calibrat
ed by adjusting the front panel AMPL CAL control so that
the output is appropriate for 10 dB per division;
2) the Log Amplifier detector circuit gain is adjusted so the
Log Amplifier output agrees with the digital-to-analog con
verter output;
3) input Ref Lvl potentiometer R4071, is adjusted for no
change in output level from U4090B when alternately press
ing the 10 dB and 2 dB selector switches on the front panel;
4) output Reference Level potentiometer R4081 is adjusted
for a full screen display.
The gain switching network provides for switching 15 re
sistance values into the feedback path of variable gain log
amplifier U4090B, and consists of four FET switches
(Q4075, Q4070, Q5070, and Q5075) and four resistors
(R7071, R6074, R6073, and R6082). The FET switches,
controlled by data bits 0, 1,2, and 3 from the analyzer data
bus,' connect feedback resistors for U4090B in 15 value
combinations as determined by the binary content of the
four data bits.
In the non-programmable 492, only the 10 dB per divi
sion and the 2 dB per division selections are available and
are controlled by front panel switches through the analyzer
microcomputer. In the programmable 492P, the full 15 com
binations are selectable through program control.
Linear Mode Circuits
The Linear Mode circuits accept the output from log
preamplifier U4090A and rescale the signal level to linear
values. Since no switching is provided in the Log Amplifier
(that is, all signals are logarithmically scaled), to operate the
system in linear mode requires that the signal level be re
exponentiated. Thus, high gain is required at the top of the
screen and low gain is required at the bottom of the screen
to offset the characteristics of the Log Amplifier.
In addition to the signal path described in the Log Mode
circuits, the output from preamplifier U4090A is also applied
to linear mode amplifier U4090D, an operational amplifier
with a successive resistor network in the feedback path.
From this amplifier, the output signal is applied through FET
Q5090 (if that transistor has been turned on by data bit 5
from the analyzer data bus being a 1) to the summing node
at the input to output amplifier U4090C. After this point, the
signal path is as described in the Log Mode circuits
description.
Starting at the signal level that represents the top of the
screen (0 volt) at the output of linear mode amplifier
U4090D, the operation of the network is as follows.
With a 0 dBm input from the Log Amplifier to the Video
Amplifier, the output of U4090D is 0 volt. At that level, the
feedback path is through only resistor R6104. The other
feedback path resistors (R7097, R7096, R7092, and R7093)
are not in the path because the switch transistors are bi
ased off by the bias network consisting of resistors R7082,
R7081, R6085, R7086, and R7095, plus diode CR7095.
(The diode is included for temperature compensation pur
poses.) As the display moves away from full screen, the
output of U4090D rises positive and transistor Q6115 is
biased on, thereby placing R7097 in parallel with R6104 and
reducing the gain of U4090D. Further increases in the out
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