Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
The microcomputer is based on a 6800 microprocessor;
its operating program
is stored
in
ROM.
The
microprocessor accesses the ROM-RAM, and I/O interface
via the microcomputer bus. The bus operates with 16-bit
addresses,
8
-bit bytes, and several control lines for data
transfers.
The front panel and the addressable registers that con
trol some other 492/492P assemblies reside on the instru
ment bus. This bus requires only
8
-bit addresses and
transfers
8
-bit bytes. The bytes may be codes to set or
indicate the status of an assembly or, in the case of digital
storage and crt readout, data values that correspond to the
display. When one of the assemblies requires the attention
of the microcomputer, it asserts a service request line. The
microcomputer responds by finding the source of the ser
vice request and executing the appropriate service routine.
Processor communication over the instrument bus can
be stopped by an external controller on the accessories
bus; the external controller can then override normal
operation.
The GPIB interface (492P only) resides on the
microcomputer bus. It contains added ROM for the operat
ing program used for GPIB I/O and added RAM. The inter
face is based on a general-purpose Interface adapter (GPIA)
IC that reduces processor overhead required for GPIB
operation.
PROCESSOR <^>
The Processor board contains the processor clock,
microprocessor, address decoders, microcomputer bus
buffers, and instrument bus interface. These blocks are
shown on the Processor board block diagram adjacent to
Diagram 31.
Processor Clock
The two-phase processor clock is derived by U4035 from
its internal oscillator. A simple logic diagram of this IC is
shown in Fig. 5-30.
The two clock signals,
φλ
and
φ2,
are complementary
and non-overlapping. They are divided by 4 from the oscilla
tor frequency for a processor clock frequency of about
850 kHz. The
φ
2 CLK is buffered for use by the rest of the
microcomputer system and is in phase with the
φ2
clock
signal used by the 6800. The undivided oscillator frequency
signal is distributed as CRT CLK for crt readout timing.
RST stays low while C3042 charges following power-up
and holds the microcomputer in a reset state until the power
supply is fully on. This signal does not disable the clock, so
the 6800 can initialize itself during this time.
6800 Microprocessor
The 6800 microprocessor (U3027) is an
8
-bit processor
with an
8
-bit bidirectional data bus and 16-bit address bus.
The 6800 block diagram in Fig. 5-31 shows the internal or
ganization of the IC. The function of each block is as
follows.
Accumulators. Eight-bit accumulators A and B hold
operands for and results of ALU operations.
Condition Code Register. Bits in the condition code reg
ister indicate results of ALU operations and whether inter
rupts are masked; see Table 5-20.
Program Counter. This 16-bit register holds the address
of the instruction being executed.
Stack Pointer. This 16-bit register acts as the pointer for
a previously defined stack in memory. The pointer is the
address of the next available location on a LIFO (last-in,
first-out) basis. The stack is used to store the contents of
MPU registers when an interrupt occurs or the 6800 ex
ecutes a subroutine. The stack pointer is decremented when
data is pushed onto the stack and incremented when data is
popped off the stack.
Table 5-20
CONDITION CODES
0
Carry from accumulator bit 7
1
Overflow
2
Zero result
3
Negative result
4
Interrupt mask
5
Carry from accumulator bit 3 (half-carry)
6
Unused (always 1)
7
Unused (always 1)
Index Register. This 16-bit register facilitates indexed-
mode addressing. Instructions can load, increment,
decrement, compare, etc., so it can also be used as a gener
al purpose register.
5-78
REV FEB 1983
