Thepry of Operation—492/492P Service Vol. 1 (SN B030000 & up)
starting point for table B is shifted slightly so that when both
tables are being read, the readout values are interlaced.
When the signals are recreated, the operator has the op
tion of displaying either A or B, or both A and B. If both are
to be displayed, and SAVE A mode is also selected, the
contents of both table A and table B are drawn, each display
in its own trace. If SAVE A mode is not selected, the con
tents of both table A and table B are displayed on one trace,
with 1024 value positions across the screen. A third trace
option is also available. In the B minus A mode, the dis
played values are those resulting from an arithmetic oper
ation and are the difference between the contents of table A
and table B for each X value of analog sweep voltage.
Since a signal waveform is continuous and a table has
discrete X values, an algorithm is used to determine the Y
value to be stored for a particular X value. This allows the
operator to select one of two methods for determining Y
values: peak or average. The Y analog voltage is continu
ously sampled, with the sampling rate dependent upon
sweep speed. For each X value, there are always at least
two samples and there may be as many as 217 samples.
From this set of samples then, the user may select either the
largest sample value (peak value) or the mean of all the
samples (average value). Selection between peak and aver
age is controlled by the front panel PEAK/AVERAGE con
trol, which sets a dc level that is compared with the analog
vertical input to produce the PEAK/AVERAGE logic signal.
When the input signal is below the level selected by the front
panel control, the signal is averaged; when the input is
above that level, the peak signal is displayed. The dc level
appears on the display as a positionable horizontal line. This
marker line is created by switching the dc level to the analog
output line during the marker cycle to produce the MARKER
logic control signal.
Superimposed on the marker line is an intensified spot
called the UPDATE MARKER, which indicates the X value
at which new Y values are being computed for display up
date. The update marker is formed by comparing the analog
sweep input to the display analog X output. When the two
are the same value, the sweep is forced to pause, thus in
creasing the marker intensity at that point. Refer to the
block diagrams, adjacent to Diagrams 24 and 25.
Central to the 492/492P digital storage system are two
specially designed and manufactured IC's; U1023 and
U2032. Vertical section IC U1023 contains the vertical ac
quisition and display logic, and peak detection, signal aver
aging, Z-axis blanking, and special Y-value processing
circuits. Horizontal section IC U2032 contains the horizontal
acquisition address counter, horizontal display counter, 10-
bit RAM address multiplexer, and a programmable logic ar
ray system control matrix. The remainder of the digital
storage control circuits consists of two 8-bit digital-to-ana-
log converters, two 10-bit digital-to-analog converters, one
10-bit latch, 8k bits of random access memory, and various
ancillary circuits. Timing is controlled by clock pulses from
the microcomputer board to pin 1 at approximately a 1 MHz
rate. The two primary IC’s, U1023 and U2032, are de
scribed as appropriate at the beginning of the vertical and
horizontal section detailed descriptions that follow.
Vertical Section
Vertical Control. (Refer to Fig. 5-15.) The vertical analog
voltage is converted to a Y binary value using an 8-bit
successive approximation register. Nine clock cycles are re
quired for each Y conversion. After the conversion has tak
en place, the successive approximation register produces
the negative-going SYNC signal. Most functions on both the
vertical and horizontal control IC’s are synchronized by this
signal. On the negative-going transition of SYNC, the
successive approximation register is reset to 10 00 00 00
(binary) and the next conversion cycle begins. Incoming data
bits are latched into the successive approximation register
on the negative-going clock transition. From the register, the
output data are applied to the peak and the averaging
circuits.
The averaging circuit consists of three groups of circuits:
those that accumulate the grand total of all of the Y values
for a given X value (this total is called the numerator), those
that count the number of samples that make up the numera
tor (this total is called the denominator), and those that sub
tract and shift to perform the division process.
As each new Y value is converted, it is added to the eight
least significant bits of the numerator. Each carry from the
most significant bit of this addition is counted by a 17-bit
ripple counter. The contents of this counter and the 8-bit
sum are cascaded to form a 25-bit grand total. Each time a
new sample is added to the numerator, a second 17-bit rip
ple counter is incremented to produce the denominator.
A division cycle is initiated when the horizontal control IC
U2032, located on Diagram 25, detects a change in the X
value. At that time, U2032 produces the ST DIV (start di
vide) signal. Upon receipt of this signal, and in synchroniza
tion with the SYNC signal, vertical control IC U1023
performs several functions (refer to Fig. 5-15):
1) it latches the current numerator in a 25-bit latch (25 to 1
data concentrator in the block diagram), and latches the de
nominator in a 17-bit latch (17 to 1 data concentrator in the
block diagram);
2) it clears the numerator adder circuits (25-bit summation
register in the block diagram);
3) it performs a 17-bit priority encode on the denominator
and loads a 1 in the appropriate cell of the 25-bit shift
register;
REV FEB 1983
5-39
