Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
voltage source. When J1091 is in the 115 V position (pins 1
and 2), rectifiers CR3096 and CR4094 operate in conjunc-
O
tion with energy storage filter capacitors C6101 and C6111
as a full-wave doubler; thus, the voltage across the two
capacitors is the peak-to-peak value of the line voltage.
When J1091 is in the 230 V position (pins 2 and 3), CR3096,
CR4095, CR3098, and CR4094 operate as a bridge rectifi
er. As a result, the output voltage applied to the inverter is
about the same for 115 V or 230 V operation.
Thermistors RT2093 and RT2097 limit current surge to
the supply at turn-on. After the analyzer is in operation, the
current demand drops, the resistance value of the
thermistors drops, and they have minimum effect on the
circuit.
W A R N I N G
Because C6011 and C6101 discharge very slowly,
hazardous potentials exist within the power supply for
several minutes after the power switch is turned off. A
relaxation oscillator, formed by C5113, R5111, and
DS5112, indicate the presence o f voltages in the cir
cuit until the potential across the filter capacitors is
below 80 V.
S2103 is a thermal cutout switch that opens if the interior
of the instrument reaches 103°C. It prevents overheating in
case the cooling fan fails.
E1094 and E2095 are surge voltage protectors. When
the line selector switch is in the 115 V position, only E1094
is connected across the line input. If a peak-voltage surge in
excess of 230 V occurs across the input, or if the instrument
is accidently connected to a 230 V source, E1094 will break
down and demand enough current to open the line fuse.
When the instrument is operated with the line selector at
230 V, E1094 and E2095 operate in series to protect the
input against line surges of about 460 V peak.
The voltage for the line trigger source is taken off the
input circuit just past S2103. It is coupled through C3085
and C3089 then off the board to the Sweep circuit to pro
vide instrument triggering at line frequencies. The voltage at
the top of R6093 is about 2 V peak-to-peak.
Inverter Circuit
The inverter consists of several stages; a multivibrator
that produces a square-wave signal to drive the ramp gener
ator and the inverter logic circuits. The ramp generator pro-
J
duces a low-level sawtooth ramp that is applied to the
primary regulator circuit. The inverter logic circuits control
the duty cycle of the inverter driver, and thus the inverter
output stage. The primary regulator compares the +17 V
supply output with a reference voltage, and gates the invert
er logic circuits off and on to control the inverter duty cycle
and thus the effective primary voltage. The inverter driver
stage amplifies the signal from the inverter logic circuit and
drives the output stage. The output stage consists of two
power switching transistors that drive the primary of the
main power transformer, T4071. Primary overcurrent sense
and soft start circuit add protection.
Multivibrator. U6059, a low power 555 timer, is a
multivibrator that operates at about
6 6
kHz and 80% duty
cycle. Oscillator frequency is adjusted by R6061. The output
square-wave signal is applied through R6052 to the primary
of T6044 in the ramp generator, and directly to U6053,
U6063A, U6063B, and U6069.
Ramp Generator. This circuit consists of T6044, Q5023,
Q6034, and Q5032, and surrounding components. The cir
cuit is a gated sawtooth generator that operates as follows:
The negative excursion of the square-wave signal from
Q6056 is coupled across T6044, forcing Q6034 into conduc
tion. This forward-biases Q5032 and its collector moves to
ward +17 V, charging C5038 to this value. Shortly
thereafter, Q6034 loses drive (since the pulse coupled
across T6044 has died away) and the two transistors cut
off. Q5023 acts as a constant-current drain to discharge
C5038 linearly. This signal is coupled across divider
R5036/R6032 then applied through C6039 to the input of
comparator U6036, part of the primary regulator.
Primary Regulator. This circuit consists of comparator
U6036 and U6046, photocoupler U6043, and related com
ponents. The circuit varies the duty cycle of the driving sig
nal for the inverter as follows: The +17 Vt voltage is divided
by R6038 and R6037 to about +4.8 V, and applied to the
inverting input of U6036. The + 5 V reference is applied
through R6022 to the non-inverting input of U6036, where it
is combined with the ramp signal from the ramp generator
stage. The non-inverting input thus receives a sawtooth sig
nal of about 500 mV peak-to-peak imposed on + 5 V dc lev
el. This is compared with the +4.8 V on the other input, so
the comparator switches with each sawtooth cycle. Now,
refering to Fig. 5-41, note that as the level at pin 3 (which
corresponds to +17 V supply variations) rises and falls, the
duty cycle of the output waveform varies also.
The signal from the output of U6036 is applied to U6043,
an optical isolator. The output of this stage is then applied
to the input of U6046, a comparator. The inverting input of
this device is referenced at +2.55 V, so the comparator
switches at the crossing point. The purpose of the last two
stages is to shift the dc level of the output signal of U6036
to CMOS levels to drive the inverter logic.
REV AUG 1981
5-95
