Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
Fig. 5-21. C haracter scan tim ing.
Bit 0 turns the crt readout display on (1) or off (0). When
set, this bit gates the off-timer to the GEN ON flip-flop J
input through U1038D, enables the INC gate (U1022C), and
steers the position counter onto the character RAM address
inputs through multiplexer U1024. When cleared, this bit
places an address, latched in U2024, on the character RAM
address inputs.
RAM (U1026) by setting its R/W input high. This high also
disconnects the instrument bus from the character RAM
data inputs by disabling U2028. Meanwhile, Q2 of U2034 is
low, enabling U2032D to gate the clock signal that latches
the address. The positive clock transition is applied to
U2024 when DATA VALID goes false at the end of a write
cycle to the address/data port, releasing DATA.
Bit 1 interprets data sent to the address/data port as an
address (1) or data (0) for the character RAM. Setting this
bit disables the character RAM for input and sets up the
clock signal to latch the address.
When this bit is set, Q2 of U2034 gates a high on the
output of U2032A. This high prevents input to the character
When this bit is cleared and DATA is asserted, U2032A
enables the character RAM for input and passes the data
through U2028.
Bit 2 selects information from the two halves of character
RAM space. When set, this bit selects page 1, the normal
front-panel readout. When cleared, this bit selects page 2, a
5-52
REV AUG 1981
