Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
The low state now at the Q output of U5026A is coupled
to the hoidoff circuits and the inverting input of U5085B, an
' open collector comparator. U5085B switches, its output
rises, and Q2107 conducts. This clamps the output of the
integrator to its input, and discharges the timing capacitors.
Q2107 continues to conduct until a trigger is furnished to
U4016C, which resets U5026A to begin the next sweep
cycle.
When manual scan or external sweep is selected, both
inputs to U5016D are high, which causes its output to be
low. This causes the output of comparator driver U5085C to
switch high and turn FET Q3100 on. As a result, feedback
resistor R3105 is placed across U4101, converting it into an
amplifier. Timing capacitor C2098 is still in the circuit, but its
small capacitance has negligible effect at the low frequency
of operation in this mode. The output of U5016C also resets
U5026A and the SWP GATE remains high. These levels will
remain until the output of U4101 overcomes the switching
point of U2015A.
The input signals from manual scan and external horizon
tal are multiplexed by U6102 and applied to U4101. Since
the summing node of the amplifier is not at ground, R7091
and R4093 shift the dc levels of the manual and external
drive signals, respectively. U6092A is an inverting buffer for
the external voltage; VR6086 is for overvoltage protection.
The sweep ramp from U4101 is applied through voltage
divider R6058— R6052, which reduces the ramp voltage to
U6061 to 11 V, centered around 0 V. The output of U6061
is applied to the Digital Storage and Deflection Amplifier cir
cuits. The extra volt of sweep amplitude is used to deflect
the beam 0.5 division off screen on each side.
The sweep signal from U4101 is also applied to U6071,
which amplifies the ramp to 22 V, centered around 0 V. This
signal drives the Span Attenuator and ultimately the 1 st Lo
cal Oscillator.
Sweep Control
This description is based on the assumption that the
sweep is in neither the manual nor the external mode. At the
end of the sweep, U5026A is in set state. Its Q output is
low, which causes the output of U4026C (the hoidoff gener
ator) to switch high. This starts the hoidoff cycle. The
hoidoff time between sweeps must be sufficiently long for
the timing capacitors to discharge and for any transient re
sponses in the swept circuits to die. As the sweep time
increases, the hoidoff time is increased.
When the output of U4026C rises, the hoidoff capacitors
charge to +5 V through R3027. Capacitor C1013 is always
in the hoidoff circuit. When U2043 latches Q4 or Q5 high,
this produces a low out of U4026F or U4026E which in
creases hoidoff time by adding C3028 or C3027 into the
hoidoff circuit. Diodes CR3034 and CR3035 protect the two
inverters from reverse voltage transients that might pass
through the capacitors.
When the voltage on the capacitors reaches + 5 V, the
output of U2015D switches high. If single sweep has not
been selected, both inputs to U3061C will now be high and
its output will enable trigger multiplexer U3034. When the
next sweep is ready to run (depending on the trigger selec
tion conditions), pin 7 output of U3034 switches high. This
change in state gated through U4016C resets U5026A and
begins the next sweep cycle.
When the single sweep mode has been selected, pin 2 of
U5016A is high. U2034A, the single-sweep flip-flop, must
furnish a low to U5016A to enable U3034 to trigger a single
sweep. This enabling occurs when the microcomputer
clocks U2034A. When the sweep starts, U5026A resets and
sets U2034A. This ensures that only one sweep occurs for
each microcomputer command.
Single-sweep mode is usually selected by front-panel
commands; however, in some modes, the microcomputer
will command single sweep. The microcomputer can also
abort a sweep and start another with the next trigger; a
pulse from U5052C, through U3061B, to pin 3 of U4016A
sets U5026A and causes the sweep circuit to reset.
Digital Control Circuits
As mentioned throughout this description, the sweep is
controlled by latched codes and pulses. The board has two
ports for receiving information from the microcomputer, ad
dresses F and 1F. U5033 buffers the data inputs, decreas
ing the loading instrument bus. Address decoder, U5043,
decodes the address bus and strobes the data onto the
board. Each output of U5043 goes to low when the corre
sponding port is addressed. Data is latched on the rising
edge of this strobe, which is the trailing edge of Data Valid.
The output of U5043 is inverted (U1052B inverts 1F;
U1052C inverts OF), then combines with the proper data
bus line to form each bit of pulsed data. The pulse is at the
low state for the duration of the Data Valid pulse (approxi
mately 1
MS).
U3042 latches the data from port OF. The combinations
of D3 to D7 select the sweep rate; D3 and D4 control timing
capacitor selection, and D5 to D7 control timing resistor se
lection. Table 5-11 lists the sweep rate selection codes. D2
is high during single sweep operations; otherwise, it is low.
DO commands a single sweep cycle.
REV AUG 1981
5-57
