Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
Fig. 5-38. The keyboard encoder.
When the control logic detects a difference between the
input and a bit in the shift register, it activates the debounce
mask, its latch output, and the encoder strobe output. The
mask signal holds off action by the control logic so the
encoder doesn’t see multiple switch closures caused by
switch bounce. The mask time is controlled by C4026. The
latch output causes the character code, in read-only mem
ory, addressed by the X and Y counters, to be entered in the
character store. The encoder strobe output activates the
encoder interrupt interface to request the microcomputer’s
attention.
Switch Interrupt Interface
The encoder strobe output is level controlled by the
switch interrupt interface. When the encoder asserts its
strobe output (high), it causes U3014C to pull down on SER
REQ. The strobe high also releases the preset input to
U2018B, which was holding the keyboard encoder strobe
control input low. Since the encoder is waiting for a low-to-
high transition on this input, to stop asserting its strobe out
put, SER REQ remains asserted.
When the microcomputer responds to the interrupt, it
learns that the keyboard encoder requested service from
DBO, the encoder’s parallel poll bit. DBO is set low by
U3014E at the same time SER REQ is asserted. The
microcomputer ends its poll sequence by clearing all inter
rupts it has read. It does this by first setting AB7 low, dis
abling U3014E so it cannot continue to assert DBO. The
microcomputer then writes the parallel poll byte back on the
5-90
REV AUG 1981
