Maintenance—492/492P Service Vol. 1 (SN B030000 & up)
A portion of one address block, decoded by U2044, is
further decoded by U1037B. Figure 4-27 shows the U1037B
enable line on top and below it in order, YO through Y2. Y3 is
i similar in width and follows in sequence.
The narrow pulses evident during the time each output of
U2044 and U1037B is asserted result from address lines
toggling between microcomputer cycles.
Clocks and Control Lines. The 6800 clock lines are
complementary, nonoverlapping square waves with periods
of about 1.17
ms
. VMA, RESET, NMI, and R/W should be
high (logic one). IRQ may be either high or low, depending
on how assemblies on the insrument bus powered up.
Memory Address Decoders. Address decoders U1036
and U1038 on the Memory board set their outputs low to
access blocks of ROM addresses. These outputs are
shown in relation to A15 in Fig. 4-25. The RAM (U2035 and
U2032) chip-select lines and option switch register (U1033)
enable line are also decoded on the Memory board as
shown in part d of Fig. 4-28. The narrow pulses which may
be evident during the time each output is asserted can be
ignored for the reason noted above under Processor Ad
dress Decoders.
GPIB Board Address Decoders. Address decoder
U1021 on the GPIB board sets its outputs low in sequence
while the 492P is operating in the microcomputer test mode.
YO through Y2 are shown in relation to A15 in Fig. 4-29.
Although not shown, Y3 through Y7 are asserted in order
with the same pulse width.
U1028 further decodes two address decoder signals
from the Processor board. One enable and two output sig
nals are shown in Fig. 4-30. The other output, ASR, is not
shown, but looks the same as GPS: they appear to be as
serted at the same time. These two signals can be com
pared for correct operation by speeding up the sweep and
noting that they toggle in a complementary fashion during
the time they appear to be low in the figure.
Fig. 4-27. Enable and YO through Y2 of address decoder
U1037B.
The pattern on the instrument bus toggles DATA VALID
and POLL and exercises the address and data lines at sepa
rate times. The address lines change when DATA VALID is
low and the data lines change when DATA VALID is high.
There may be an exception on DB4 through DBO; these
lines may continue to change after DATA VALID goes low if
an assembly on the bus is requesting service because of the
way it powered up. In this case, an assembly or assemblies
may respond to the high state of POLL and the changing
state of AB7 and attempt to report status.
The pattern for the upper address and data lines is
shown in Fig. 4-31. Each lower order line changes at a rate
that is twice the next higher line, resulting in 128 cycles on
the LSB lines. The initial pulse on the upper four data lines is
not part of the divide-by-two pattern and is not repeated on
the lower four data lines. By comparing the lines to those in
Fig. 4-31, checking that they divide-by-two, it is possible to
discover open or shorted lines. Look for lines that stay high
or low, change together or at wrong times in the pattern, or
go to indeterminate logic levels (—1 to —2 V).
Instrument Bus Check Mode
If the microcomputer performs the power-up self-test,
but fails to control the instrument properly, the instrument
bus check may uncover the problem. The instrument bus
check mode may be selected by setting the option switch as
shown in Fig. 4-24. In this mode, the microcomputer con
tinuously writes to the instrument bus to exercise it in a
repetitive manner. Consequently, the instrument does not
operate normally.
J
Firmware Operating Notes
The following are exceptions to normal instrument oper
ation that relate to the different firmware versions. The in
strument displays its version number during power-up for
about two seconds. To see the message, turn power off
then on; the version message will appear at the upper cen
ter of the screen.
REV JUN 1983
4-39
