Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
Trigger Circuits
The sweep generator can be triggered from three
sources: internal, external, and line signals. All three signals
are converted to TTL levels by input buffer stages. Each
output signal is coupled to U3034, the trigger multiplexer.
The external trigger signal (EXT TRIG/HORIZ IN) is ca-
pacitively coupled from the external trigger input connector
through a compensating network to the input of the external
trigger buffer and level shift circuit, which consists of differ
ential amplifier Q2084 and buffer U1052E which converts
the signal to TTL level. Diodes CR2075/CR2086 protect the
input stage from excessive voltage.
The signal for the internal trigger circuit (VIDEO FILTER
OUT) from the video filter is applied through Q2074 coupled
to differential amplifier Q1078, then converted to TTL levels
by U1052F. CR1088 and CR1089 protect the input of
Q1078 from excessive voltage.
The input line trigger signal amplitude is large enough to
overdrive Q1047 producing a line trigger output 0 to + 5 V
peak. Diode CR1035 protects the emitter-base junction
from reverse bias.
Upon instructions from U2043, the “2” side of dual trig
ger multiplexer U3034 selects the trigger signal for the clock
input of trigger flip-flop U2034B. The flip-flop clocks on the
rising edge of the applied signal, so the complement of the
signal at the D input appears at the output at the first trigger
after the multiplexer enable goes to a low state.
Upon instructions from U2043, the “1” side of U3034
selects either the output of U2034B or the high state at pin
6
. When the multiplexer is disabled, which occurs during
sweep hoidoff time, the multiplexer output is low. If free run
is selected, the output goes high as soon as the multiplexer
is enabled. However, if the sweep is in a triggered mode, the
output will not go high until the next trigger occurs. This
transition restarts the sweep. When the sweep starts again,
U2034B is set by sweep state flip-flop U5026A in prepara
tion for the next sweep end-holdoff-trigger cycle.
Sweep Generator
The sweep generator consists of the timing current gen
erator (timing resistor selector U6102, voltage regulator
U4095, U6092B, and surrounding circuitry), the integrator
(U4101, U5085C, Q3100, U5085A, Q3090, U5085D,
Q3095, and associated components), and the reset clamp
(U5085B, Q2107, and surrounding circuitry).
The timing reference voltage for the sweep circuits is set
by U4095 to —10 V. Divider R5092— R5094 sets the volt
age at the non-inverting input of U4101 to
— 8
V; feedback
sets the inverting input at the same potential. This input is
driven by the output of multiplexer U6102. Operation of the
circuit is as follows: The 1 to 10 V reference, from U4095, is
applied to U6092B, which changes this level to - 1 2 V,
which connects to one side of the timing resistors connect
ed to U6102. A 4 V difference then appears across the tim
ing resistor. Multiplexer U6102 decodes instructions from
U3042 (the OF port latch), and connects only one resistor or
resistor pair to its output pin, which then becomes the cur
rent source for integrator U4101. The multiplexer input
codes for each of the sweep rates are listed with the de
scription of the Digital Control circuits. Sweep accuracy ad
justment R5105 is set to compensate for errors in this
voltage or in the timing capacitor values. The timing capaci
tors are matched, so one adjustment can be used for the
entire set.
The timing current furnished by the multiplexed resistors
varies such that
1/1
is proportional to a
2
—5
—
1 0
sequence.
Decade switching of sweep rates is provided by timing ca
pacitor selection (C3079, C2094, and C2098). C2098 is
used in all sweep rates, and for the
2 0
με to
1
ms range.
When a sweep rate of 2 ms to 100 ms is selected, the out
put of open collector comparator U5085D goes high,
causing FET Q3095 to conduct and place timing capacitor
C2094 in parallel with C2098. Likewise, when a sweep rate
of 200 ms to 10 s is selected, U5085A causes Q3090 to
switch C3079 in shunt with the other two capacitors. (The
1 0
s/div sweep rate is only used in the auto-sweep routine,
or in the 492P.) VR2093, R2099, CR2101, CR2102, and
CR2103 clamp the output to prevent the negative sweep
retrace from causing the FETs to conduct.
A voltage divider consisting of R2012, R2013, and
R2017 set a switching threshold of about +7.4 V at the
input of the right-of-screen comparator U2015B. At the be
ginning of the sweep, the output of integrator U4101 is
—
8
V. The output voltge rises linearly to +7.4 V, then
U2015B switches, placing a low at the input to U5016B.
This causes the output PEN LIFT signal to move high. This
signal was low up to this point, because of the high SWP
GATE signal at the beginning of the sweep cycle and the
high level at the output of U2015B. The PEN LIFT signal
switches before retrace occurs to give the pen time to lift.
The sweep rises in amplitude until it reaches
+ 8
V, causing
U2015A (the end-of-sweep comparator) to switch. (The
same divider that was mentioned earlier sets a switching
threshold of about +
8
V at the non-inverting input of
U2015A.) The low state from U2015A is inverted by
U1052A and the high output applied to U4016A sets
U5026A. The high state at the Q output of U5026A is invert
ed by U4016B, causing the SWP GATE signal to move low,
blanking the crt display. The low out of U4016B also gates
PEN LIFT high through U5016B.
5-56
REV AUG 1981
