Theory of Operation— 492/492P Service Vol. 1 (SN B030000 & up)
The above description of the right-hand (inverting) sec
tion is applicable to the left-hand (non-inverting) section ex
cept for the circuit element designations.
Output signals from the second half of switch U7055 are
also supplied to the auto focus amplifier (IC’s U6093,
U6102, and transistors Q7097, Q7103). Amplifiers U6093
and U6102 produce a negative absolute value signal that is
three times higher in amplitude than the signal from switch
U7055. This amplified signal is then used to produce a
shaped current by transistors Q7097, Q7103, and resistors
R7102, R7101, R7107, R7108, to apply to the Z-Axis Inter
face circuit through edge connector pin 45. This signal will
sink from 0 to approximately 0.8 mA of current from an ex
ternal node at a voltage of approximately 0 V.
Vertical Section
Signal lines VIDEO FILTER OUT (from the Video Proces
sor circuits) and VERT SIG (from the Digital Storage cir
cuits), through edge connector pins 53 and 52 respectively,
are routed through switch IC U6055. One side of U6055,
under control of the STORAGE OFF signal from the Digital
Storage circuits, selects either VIDEO FILTER OUT or
VERT SIG. Note that the VIDEO FILTER OUT signal is buff
ered by IC U7065 to prevent changing load transients from
affecting the signal level. When the STORAGE OFF line is
floating or pulled high, the buffered VIDEO FILTER OUT
signal is selected; when the line is low, the VERT SIG signal
is selected. The selected signal is inverted and clamped to
ground by U6065. (Both the VIDEO FILTER OUT and VERT
SIG signals are specified at 0.5 V/div with 0 V for the base
line and positive voltages above the baseline. The signal is
re-inverted and offset by buffer U6073 so center screen rep
resents 0 V. From buffer U6073, a sample of this centered
signal is applied to a rear panel connector via edge connec
tor pin 46. The signal is also applied to the other side of
switch U6055 along with the VERT R/O signal from the
Readout circuits. Selection between these two signals is
controlled by the R/O OFF signals; also from the Readout
circuits. When R/O OFF is floating or pulled high the signal
from buffer U6073 is transmitted through the switch. When
the line is pulled low, the VERT R/O signal is selected.
The vertical section shaper (resistors R3061, R4065,
R4067, R3071, R3064, and diodes CR4063, CR4064) and
preamplifier (U2062) operate the same as the horizontal
section. Transistor Q4078 limits positive excursions to ap
proximately one division below the top of the screen to pro
tect the output stages from being overdriven.
The vertical output stages are similar to the horizontal
stages with the exception of higher bias current. Current
flow of approximately 1 mA through resistors R3095 and
R3098 result in approximately 5 mA in the output stages.
Resistors R5081 and R5099 are of less resistance than
R5041 and R5027 in the horizontal section to correct for the
increased current in dual input staqe transistors Q4083 and
Q4101.
Comparator U6024 compares the level of the signal from
baseline clamp U6065 with a reference level set by divider
R7032 and R7034 to produce the CLIP signal for the Z-Axis
Interface circuits. The CLIP line is pulled low when the Video
signal is more negative than the reference level (approxi
mately 1 division above baseline), and pulled high by R7021
if the signal is more positive than the reference level.
Z AXIS CIRCUITS <$>
Refer to the block diagram adjacent to Diagram 27. The
Z-Axis circuits take the various beam control inputs such as
SWP GATE, INTEN, etc., combine them, and furnish the
drive currents and bias voltages required to operate the crt
electrodes. The Z-Axis circuit consists of the Intensity Con
trol Logic circuits, which control the crt beam current for
normal signal display operations. It also includes the
unblanking gates which furnish current to the Z-Axis Drive
Amplifier to drive the crt control grid. The Z-Axis circuits
also include voltage-setting circuits for astigmatism, crt
trace rotation coil, geometry, and other crt electrode
voltages.
Z-A xis Driver Amplifier
The Z-Axis Drive Amplifier Q3047, Q4058, and Q4059, is
driven by two sources, exclusive to each other:
U2038B/Q2042 drives the amplifier during readout display
periods, and U2038A/Q2044 drives the amplifier during
sweep display periods. U2039 is an AND-NOR gate that is
connected to provide the logic to one input of NAND gate
U2038A which turns Q2044 on or off. The R/O OFF line and
the output of U2039 must both be high for U2038A to fur
nish current to Q2044. Table 5-8 lists the conditions under
which U2039 will output a high to U2038A.
Table 5-8
U2039 TRUTH TABLE
U3046 output (line 28)
0
0
0
1
1
1
0
0
0
CLIP
0
0
0
0
0
0
1
1
1
Z Axis Blank
1
1
1
1
1
1
1
1
1
Storage Off
0
0
1
0
0
1
0
0
1
SWP GATE
1
0
1
1
0
1
1
0
1
U2034, pin 13
0
0
0
0
0
0
0
0
0
Only the combinations shown in the truth table plus a
high on R/O line will gate a low out of U2038A. When
5-46
REV FEB 1983
