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Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
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cycle after the last sample as indicated by the least signifi
cant bit from the successive approximation register in
U1023. The switched sample is then applied through buffer
U2032 to a summing junction, at which point the output
current from the digital-to-analog converter (U2024) that is
supplied from the successive approximation register is sub
tracted from the sample current, and the difference current
is applied through comparator U1031B to pin 18 of U1023
as the UP/DOWN signal. Thus, the combination of the
successive approximation register, the digital-to-analog
converter, and the sample and hold circuit effectively pro
duces the binary equivalent of the input sample.
A d d r e s s D ecoding.
The address decode logic accepts
inputs from the address bus and produces the control sig
nals for read and write operations:
CONT
W (control write),
DATA W (data write), and DATA R (data read). The control
write signal is used to gate the control word from the data
bus into control register U
1 0 2 2
to generate mode control
signals. This control word consists of five bits that represent
front-panel functions. If output Q
6
is low, a peak operation
is forced: if output Q
6
is high and Q7 is low, an average
operation is forced. The data read and data write signals are
applied to the interface logic to control memory read and
write operations.
in te rfa c e Logic.
The interface logic in general performs
control and interface functions between the active data cir
cuits in both the vertical and horizontal sections and the rest
of the 492/492P. It allows the microcomputer to control the
functions of the storage system and to access the digital
storage memory, and it contains the circuitry for serial-to-
parallel and parallel-to-serial conversion. (The micro
computer uses parallel transfer; the digital storage memory
uses serial transfer.) Shift register U2021 is used to read
data from memory to the data bus. Register U1021 is used
to store information from the data bus for transfer to mem
ory. Multiplexer U2016 performs the parallel-to-serial con
version and applies the data output to gate U2015B, which
acts as a buffer to supply either the multiplexer output or
the MEM OUT (memory output) signal from U1023 to the
memory as the DSDI (digital storage data input) data train.
The interface circuit group at the lower right corner of the
diagram is the handshaking logic that works with the hori
zontal control circuits for access to memory and for control
of when to increment the memory address counter. In either
a data read or data write operation (when the corresponding
signal goes high), flip-flop U2014B is triggered, which in turn
releases the BUS REQ (bus request) line, allowing that sig
nal to go high. This signals the horizontal control circuit that
access to memory is required. When the horizontal circuits
recognize that request, those circuits pull the BUS REQ line
low at the same time that SYNC is low. The interface logic
detects the BUS REQ and SYNC low condition through
U1013A, U1013B, U2011A, and U2012C, and produces the
low BUS GRANT signal to indicate access to memory. The
5-42
BUS GRANT signal then enables shift register U2021 to
shift data from memory or enable register U1021 and
multiplexer U2016 to shift data to memory as indicated by
the DATA R and DATA W lines. At the end of a data read
cycle, gates U1012B and U2023C produce the INCR ADRS
(increment address) signal to increment the address register
in the horizontal circuits.
M axim um Hold.
As described previously, when MAX
HOLD mode is selected, circuits in U1023 compare the bina
ry equivalent of the input signal for a given X value with the
information in memory for that same X value and cause the
larger of the two to be stored in memory. The control signal
that initiates this action is produced from Q5 of control reg
ister U1022. In combination with the VALID signal from the
horizontal circuits, this signal produces the MAX HOLD
command to U1023 through buffer U2023E and gate
U1025A.
C o n s t a n t Circuit.
As described previously, in the B mi
nus A operation, a constant is used. This constant is inter
nally selectable with switch S1014. This switch, in
combination with multiplexer U1015, supplies the constant
to U1023. Multiplexer U1015 is in turn controlled by address
bits
0
,
1
, and
2
to provide the proper switch signal to
U1023.
O u tp u t C ircuits.
From the U1023 vertical display regis
ter, the parallel data output is applied to
8
-bit digital-to-ana-
log converter U1024. The converter output is then applied
through a vector generator, consisting of an integrator
(U1032 and C1031) with an associated feedback loop sam
ple and hold circuit, to the output storage/cursor switch.
Integrator U1032 has a time constant that provides a ramp
lasting between the existing sample and the new sample
(that is, between sync pulses). Circuits U1033A and U1034
and capacitor C1038 make up a sample and hold circuit with
U1034 acting as an output buffer. From U1034, the output
current through resistor R1032 subtracts from the digital-to-
analog converter output current to modify the slope of the
output ramp. The output of the vector generator is then ap
plied to switch U1033B, which selects between the stored
data and the marker under control of the buffered
PEAK/AVG (peak/average) level control signal from U2034B
and supplies the output to the horizontal circuits.
P e a k / A v e r a g e Level Circuits.
The buffered PEAK/AVG
signal is also supplied as a mode control signal to U1023 in
combination with: the sample and hold up/down output from
U2032, the VALID signal from the horizontal circuits, and
Q7 of the control word from U1022 (always a 1), through
buffer U1031 A, gates U1025C, U1025D, U1025B, and in
verter U2023D.
REV FEB 1983
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