Tektronix 492, 492P, Service Manual

Page: 246 / 303

Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
Table 5-21
ADDRESS SELECT LINES
Line Selects
Address
SYS RAM RAM on Memory board
0000—07FF
GPIB RAM
RAM on GPIB board 0800—OFFF
U1037B-12 Instrument bus
1000— 11 FF
GPIB GPIA on GPIB board
1200—13FF
OPSW Switch register on Memory board 1400— 15FF
Table 5-22
492/492P MICROCOMPUTER ADDRESS SPACE
0 0 0 0
-------------------------
System RAM
0800 -------------------------------------------------------
GPIB RAM
1000 ---------------------------------------------------------------
Instrument Bus Interface
GPIA on GPIB board
I/O
Options switch on Memory board
1600 -------------------------------------------------------
Unused
1800 -------------------------------------------------------
ROM on Memory board (Four 2K EPROM’s)
3800 -------------------------------------------------------
Unused
4000 -------------------------------------------------------
ROM on GPIB board (B 2K EPROM’s or 2
8
K ROM’s)
ROM on Memory board (Four
8
K sockets
with 2K EPROM’s or
8
K ROM's)
FFFF -------------------------------------------------------
Other addresses are decoded on the Processor board for
diagnostics, turning on LEDs on some outputs of U2044.
Diagnostic routines can cause the 6800 to access an ad­
dress that turns on an LED as a test indicator. For further
information, see the self-test instructions in the Mainte­
nance section.
ROM addresses on the Memory board and the GPIB
board are decoded there and do not rely on address select
lines from the Processor board.
U2044 is enabled by VMA and zeros on A15 and A14
(3FFF and below). It decodes the 3-bit binary input of A11,
A12, and A13 to assert one of eight outputs (Y
6
and Y7 are
unused).
U1037B is enabled when U2044 decodes an address in
the range 1000—17FF and decodes A9 and A10 to assert
one of four outputs.
Address Map
Microcomputer memory is mapped in Table 5-22 (ad­
dresses in hexadecimal).
Instrument Bus Interface
The microcomputer communicates with the rest of the
instrument over the instrument bus (with the notable excep­
tion of the GPIB interface). Peripheral interface adapter
(PIA) U3022 is programmed to send addresses and send or
receive data on the instrument bus. It also handles control
lines for writing to and reading from registers on the instru­
ment bus. It does not, however, handle service requests;
the SER REQ line goes directly to the 6800.
The PIA is reset at power-up and the 6800 then pro­
grams it for each of its tasks. How the 6821 PIA is
configured in the 492/492P microcomputer system is shown
in Fig. 5-34.
Chip Select. Chip select lines CS0 and CS1 are always
enabled; the 6800 selects the PIA by addressing 1000,
REV AUG 1981 5-83