Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 7 Timers (TIMER)
7 – 15
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
7.4.4 Timer Interrupt Requests and Overflow Flags
Timers generate timer interrupt requests when the timer counter register overflows. The overflow flag toggles
between “1” and “0” at each overflow. The output of the overflow flag of timers 0 and 1 can be output to
secondary port functions PB.0/TM0OVF and PB.1/TM1OVF pins.
Figure 7-5 indicates the operation timing for timer counter register overflow. Table 7-1 lists timer interrupts.
Figure 7-5 Timer Counter Register Overflow Timing (for Timer 0)
Table 7-1 List of Timer Interrupts
Interrupt factor Symbol
IRQ flag
(IRQ2)
IE flag
(IE2)
Interrupt
vector address
Timer 0 interrupt TM0INT QTM0 ETM0 0020H
Timer 1 interrupt TM1INT QTM1 ETM1 0022H
Timer 2 interrupt TM2INT QTM2 ETM2 0024H
Timer 3 interrupt TM3INT QTM3 ETM3 0026H
When the master interrupt enable flag (MIE) is set to “1” with the interrupt enable flags (ETM0–3) set to “1”, and
a timer overflow occurs, a CPU interrupt request is generated.
Timer clock
TM0CH, TM0CL
TM0DH, TM0DL
TM0INT
TM0OVF
10
FE FF 10 11 FF 10 11