Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 3 CPU Control Functions
3 – 4
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
3.3 Halt Mode
3.3.1 Transfer to and State of Halt Mode
Transfer to the halt mode is performed by the software when a HALT instruction is executed.
When a HALT instruction is executed, the CPU enters the HALT mode at the S2 state of the HALT instruction.
Oscillation and time base counter operation continue while in the halt mode.
If an interrupt request occurs at the same time as execution of a HALT instruction, interrupt processing has
priority and the HALT instruction will not be executed. After the HALT instruction performs the equivalent
operation of a NOP instruction, the interrupt routine is entered. When an RTI instruction is used to complete the
interrupt routine, the main routine is resumed beginning from the instruction immediately following the HALT
instruction.
Figure 3-5 shows the timing when a HALT instruction and interrupt request occur simultaneously.
S1 S2 S1 S2 S1 S2 S2 S1 S2 S1 S2 S1 S2 S1 S2
HALT
HLT (halt flag)
Interrupt request
INT
PC flow in main
routine
: HALT instruction address
: Starting address of interrupt routine
: RTI instruction address
Interrupt routine Main
routine
System clock
n n+1 n+2 (INT) (RTI)
n
(INT)
(RTI)
HALT
instruction
execution
(equivalent
to NOP)
RTI
instruction
execution
Figure 3-5 Timing of Simultaneous HALT Instruction and Interrupt Request
Note:
While an interrupt request is generated, execution of a HALT instruction will not transfer operation to the halt mode.
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