Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 7 Timers (TIMER)
7 – 21
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
7.4.7 Frequency Measurement Mode Operation
The frequency measurement mode is used to measure the frequency of the RC oscillator clock, which has wide
product variation.
Timers 0 and 1, and timers 2 and 3 can be used in the frequency measurement mode. These timers are set as
follows for the frequency measurement mode:
•
Timer 0: Set FMEAS0 (bit 2 of TM0CON0) to “1”, and set TM0ECAP (bit 1 of TM0CON0) and
TM0RUN (bit 0 of TM0CON0) to “0”.
•
Timer 1: Set TM1ECAP (bit 1 of TM1CON0) and TM1RUN (bit 0 of TM1CON0) to “0”.
•
Timer 2: Set FMEAS2 (bit 2 of TM2CON0) to “1”, and set TM2RUN (bit 0 of TM2CON0) to “0”.
•
Timer 3: Set TM3RUN (bit 0 of TM3CON0) to “0”.
The count obtained in the frequency measurement mode can be used to determine the auto-reload mode timer data
register value, thereby making the timer overflow to generate various signals with required cycles. During serial
transmission, the timer 3 interrupt signal (TM3INT) is used as the baud rate clock.
Figure 7-11 indicates frequency measurement mode timing when timers 2 and 3 are used as a 16-bit timer.
Figure 7-11 Frequency Measurement Mode Timing
The operation sequence for Figure 7-11 is as follows.
①
Timer 3 control registers 0 and 1 (TM3CON0, TM3CON1) are set for 16-bit timer mode, and the timer
counter and timer data register are cleared to “0”. Enable the high-speed clock by the frequency control
register (FCON) and the timer clock is set to HSCLK.
②
Wait 10 ms or more in the ceramic oscillation mode or 300 µs or more in the RC oscillation mode after
starting the high-speed clock and set FMEAS2 to “1” to enter the frequency measurement mode.
③
When FMEAS2 is “1”, the counter starts at the 64 Hz falling edge.
④
When the 437C signal is “1”, FMEAS2 is reset to “0”, and the counter stops at the falling edge of the next
clock. The 437C signal is a pulse signal which rises in 437/32768 second after the 64 Hz falling edge.
⑤
Timer counter register value N1 is read.
FFFF
N1
TM3CH
TM3CL
TM2CH
TM2CL
TM3DH, TM3DL
TM2DH, TM2DL
64 Hz
437C
FMEAS2
437/32768 s
(H)
➀
↓
➄
↓
➂
↑
➁
➃
0000