Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 3 CPU Control Functions
3 – 5
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
3.3.2 Halt Mode Release
The following two methods are available to release the halt mode.
•
Release by interrupt generation (transfer to normal operation mode)
•
Release by RESET pin (transfer to system reset mode)
3.3.2.1 Release of Halt Mode by Interrupt
If the halt mode is to be released by an interrupt, the enable flag of the interrupt used for release must be set to “1”
prior to entering the halt mode. When the halt mode is released by an interrupt, operation transfers to the normal
operation mode.
Figure 3-6 shows the timing of transferring to the halt mode by execution of a HALT instruction and of releasing
the halt mode by an interrupt.
When the halt mode is released by an interrupt request, the first instruction immediately following the HALT
instruction is executed and then the interrupt routine is entered. When an RTI instruction is used to complete the
interrupt routine, the main routine is resumed beginning from the second instruction after the HALT instruction.
S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2
HALT
HLT (halt flag)
Interrupt request
INT
PC flow in main
routine
: HALT instruction address
: Starting address of interrupt routine
: RTI instruction address
Halt mode
RTI
instruction
execution
Main
routine
Interrupt
routine
System clock
n (RTI) n+2 n+1 (INT)
n
(INT)
(RTI)
HALT
instruction
execution
Execution of
instruction
immediately after
HALT instruction
Figure 3-6 Timing of Transfer to Halt Mode and Release of Halt Mode by Interrupt
Note:
If the halt mode is to be released, set individual interrupt enable flags to “1”. If an individual interrupt enable flag is “0”,
the corresponding interrupt request signal cannot reset the HLT flag, regardless of whether the master interrupt
enable flag (MIE) is “0” or “1”.
3.3.2.2 Release of Halt Mode by RESET Pin
If the RESET pin is held at a “H” level for 1 ms or more, the CPU is released from the halt mode and transfers to
the system reset mode. The CPU also transfers to the system reset mode when there is a Port 0 simultaneous key
depression (for 2 to 3 seconds) or the low-speed clock oscillation is stopped (selected by mask option).
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