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ML63611 User’s Manual
Appendix D

Appendix – 22

OPTION B (D): 1.5 V (3.0 V), With regulator

circuit for LCD bias

OPTION A (C): 1.5 V (3.0 V), Without regulator

circuit for LCD bias

Mask Operation Instructions

INSTRUCTION CODE

FLAG

MNEMONIC

OPERATION

W C

15 14 13 12 11 10

Z C G

MTST sfr,A

Testing of all bits in sfr not
masked by A

√

— —

MTST \cur,A

Testing of all bits in cur not
masked by A

√

— —

MTST [HL],A

Testing of all bits in [HL] not
masked by A

√

— —

MTST [XY],A

Testing of all bits in [XY] not
masked by A

√

— —

MTST E:[HL],A

Testing of all bits in
E:[HL] not masked by A

√

— —

MTST E:[XY],A

Testing of all bits in
E:[XY] not masked by A

√

— —

MTST [HL+],A

Testing of all bits in [HL] not
masked by A, HL

←

HL + 1

√

—

√

MTST [XY+],A

Testing of all bits in [XY] not
masked by A, XY

←

XY + 1

√

—

√

MTST E:[HL+],A

Testing of all bits in E:[HL] not
masked by A, HL

←

HL + 1

√

—

√

MTST E:[XY+],A

Testing of all bits in E:[XY] not
masked by A, XY

←

XY + 1

√

—

√

MTST \cur,#m

Testing of all bits in cur not
masked by #m

√

— —

MTST [HL],#m

Testing of all bits in [HL] not
masked by #m

√

— —

MTST [XY],#m

Testing of all bits in [XY] not
masked by #m

√

— —

MTST E:[HL],#m

Testing of all bits in E:[HL] not
masked by #m

√

— —

MTST E:[XY],#m

Testing of all bits in E:[XY] not
masked by #m

√

— —

MTST [HL+],#m

Testing of all bits in [HL] not
masked by #m, HL

←

HL + 1

√

—

√

MTST [XY+],#m

Testing of all bits in [XY] not
masked by #m, XY

←

XY + 1

√

—

√

MTST E:[HL+],#m

Testing of all bits in E:[HL] not
masked by #m, HL

←

HL + 1

√

—

√

MTST E:[XY+],#m

Testing of all bits in E:[XY] not
masked by #m, XY

←

XY + 1

√

—

√

Summary of Contents for ML63611

Page 1: ...ML63611 User s Manual CMOS 4 bit microcontroller SECOND EDITION ISSUE DATE Jun 2001 1 Preliminary PEUL63611 02...

Page 2: ...and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringem...

Page 3: ...Describes the base architecture and instruction set of nX 4 250 core and nX 4 300 core SASM63K User s Manual Describes the structured assembler operation and assembler language specification Dr 63611...

Page 4: ...ytes Symbol Note Gives more information about mistakable items Terminology H level Indicates high side voltage signal levels VIH and VOH as specified by the electrical characteristics L level Indicate...

Page 5: ...1 2 2 2 1 Carry Flag C 2 1 2 2 2 2 Zero Flag Z 2 2 2 2 2 3 G Flag G 2 2 2 2 3 Master Interrupt Enable Flag MIE 2 2 2 2 4 Current Bank Register CBR Extra Bank Register EBR HL Register HL XY Register XY...

Page 6: ...r Configuration 6 1 6 3 Time Base Counter Registers 6 2 6 4 Time Base Counter Operation 6 2 Chapter 7 Timers TIMER 7 1 7 1 Overview 7 1 7 2 Timer Configuration 7 1 7 3 Timer Registers 7 3 7 4 Timer Op...

Page 7: ...nction External Interrupt 2 10 31 Chapter 11 Melody Driver MELODY 11 1 11 1 Overview 11 1 11 2 Melody Driver Configuration 11 1 11 3 Melody Driver Registers 11 2 11 4 Melody Circuit Operation 11 4 11...

Page 8: ...ation 15 5 15 3 4 Operation of the OPTION B Power Supply Circuit 15 6 15 3 5 OPTION C Power Supply Circuit Configuration 15 7 15 3 6 Operation of the OPTION C Power Supply Circuit 15 8 15 3 7 OPTION D...

Page 9: ...Chapter 1 Overview...

Page 10: ...a melody circuit a serial port four 8 bit timers and a 64 segment LCD driver 60 segment lines and 4 common lines max A part of the SEG pins can also be selected as output port pins or COM pins depend...

Page 11: ...ort Port 0 0 to Port 0 3 Selectable as input with pull up resistor high impedance input Provided with the reset function that resets the system when there is a simultaneous key depression of multiple...

Page 12: ...directly connected to the power supply voltage 1 5 3 0 4 5 V Frame frequency 64 Hz at 1 1 1 2 1 4 duty 85 3 Hz at 1 3 duty Contrast OPTION B OPTION D Adjustable up to 16 levels in steps of 0 03 V OPT...

Page 13: ...e operation will only be at the battery voltage and no voltage halver circuit can be used OPTION C OPTION D 3 0 V versions 1 8 to 3 6 V Note It is possible to select by software to use the output of t...

Page 14: ...specification is selected VDD1 will be the pin for the LCD bias reference voltage and when a 3 0 V power supply specification is selected VDD2 will be the pin for the LCD bias reference voltage In ad...

Page 15: ...ng to the pins L0 to L63 can also be used as a DATA area Notes When the selection is made as output port pins the selection applies to all four bits When the segment register is selected as the DATA a...

Page 16: ...ramic oscillation circuit High speed clock OSC 200 kHz max 700 kHz max 5 3 Time base counter TBC 15 bits 1 ch 6 1 Timer TIMER 8 bits 4 ch 7 1 100 Hz timer counter 100HzTC 1 ch 8 1 Watchdog timer WDT 1...

Page 17: ...STACK CAL S 16 levels REG S 16 levels PC ALU RAM 1 KN INT TBC RST TST XT0 XT1 XT RESET TM0CAP TM1CAP TIMER 8 bit 4ch TM0OVF TM1OVF T02CK T13CK SIO Sync Async RXC TXC MELODY MD INT 4 TXD LCD DSPR L0 to...

Page 18: ...M 1 KN INT TBC RST TST XT0 XT1 XT RESET TM0CAP TM1CAP TIMER 8 bit 4ch TM0OVF TM1OVF T02CK T13CK SIO Sync Async RXC TXC MELODY MD INT 4 TXD LCD DSPR L0 to L63 INT 4 TST2 DATA BUS WDT INT 1 TST1 MDB 100...

Page 19: ...INT TBC RST TST XT0 XT1 XT RESET TM0CAP TM1CAP TIMER 8 bit 4ch TM0OVF TM1OVF T02CK T13CK SIO Sync Async RXC TXC MELODY MD INT 4 TXD LCD DSPR L0 to L63 INT 4 TST2 DATA BUS BLD WDT INT 1 TST1 MDB 100Hz...

Page 20: ...NT TBC RST TST XT0 XT1 XT RESET TM0CAP TM1CAP TIMER 8 bit 4ch TM0OVF TM1OVF T02CK T13CK SIO Sync Async RXC TXC MELODY MD INT 4 TXD LCD DSPR L0 to L63 INT 4 TST2 DATA BUS BLD WDT INT 1 TST1 MDB 100HzTC...

Page 21: ...3 60 PE 0 61 PE 1 62 PE 2 63 PE 3 64 VSS 65 L35 L34 L33 68 L32 69 L31 70 L30 71 L29 72 L28 73 L27 74 L26 75 L25 76 L24 77 L23 78 L22 79 L21 80 L20 81 L19 82 L18 83 L17 84 L16 85 L15 86 L14 87 L13 88...

Page 22: ...62 35 CS1 3 L61 36 RS1 4 L60 37 RT1 5 L59 38 VDD 6 L58 39 TST1 7 L57 40 TST2 8 L56 41 MD 9 L55 42 MDB 10 L54 43 P0 0 11 L53 44 P0 1 12 L52 45 P0 2 13 L51 46 P0 3 14 L50 47 PA 0 15 L49 48 PA 1 16 L48 4...

Page 23: ...0 100 TRIMB5 70 L29 101 TRIMB4 71 L28 102 TRIMB3 72 L27 103 TRIMDB1 73 L26 104 TRIMB2 74 L25 105 TRIMB1 75 L24 106 TRIMB0 76 L23 107 TRIMDB2 77 L22 108 TRIM3 78 L21 109 TRIM2 79 L20 110 TRIMD 80 L19 1...

Page 24: ...wer supply pin for the internal regulator A capacitor 0 1 F should be connected between this pin and VSS Leave this pin open for the OPTION A and OPTION B VXT 119 Power supply pin for the voltage regu...

Page 25: ...O Melody output pin inverted output VDD or VSS is selectable for the pin output voltage when melody output is turned off P0 0 43 P0 1 44 P0 2 45 P0 3 46 I 4 bit input port Pull up resistor input pull...

Page 26: ...M4 L4 95 L5 94 L6 93 L7 92 L8 91 L9 90 L10 89 L11 88 L12 87 L13 86 L14 85 L15 84 L16 83 L17 82 L18 81 L19 80 L20 79 L21 78 L22 77 L23 76 L24 75 L25 74 L26 73 L27 72 L28 71 L29 70 L30 69 L31 68 O Outpu...

Page 27: ...Output pins dedicated to the LCD segment signal L40 to L63 RT0 29 Resistance temperature sensor connection pin for channel 0 CRT0 30 Resistance capacitance temperature sensor connection pin for chann...

Page 28: ...to occur The Port 0 Interrupt Enable register P0IE enables or disables an interrupt for each bit PB 0 TM0CAP 51 Timer 0 capture trigger input pin Capture PB 1 TM1CAP 52 I Timer 1 capture trigger inpu...

Page 29: ...PA 0 to PA 3 Open PB 0 to PB 3 Open PC 0 to PC 3 Open PE 0 to PE 3 Open L0 to L63 Open MD MDB Open RT0 CRT0 RS0 CS0 Open IN0 IN1 Open CS1 RS1 RT1 Open Notes 1 If a pin set as a high impedance input is...

Page 30: ...uctions are classified according to the number of machine cycles 1 machine cycle instructions M1 2 machine cycle instructions M1 M2 and 3 machine cycle instructions M1 M2 M3 Most instructions are exec...

Page 31: ...ta capture interval 1 will be captured in the internal register only if a H level is maintained of Figure 1 8 throughout the data capture interval Therefore if noise occurs in the input data implement...

Page 32: ...igure when an interrupt factor is generated the interrupt factor is sampled at the falling edge of CLK and an interrupt request IRQ is set at the first half of S1 When an interrupt condition is establ...

Page 33: ...Chapter 2 CPU and Memory Spaces...

Page 34: ...cumulator and register set The register set is a programming model consisting of the HL and XY registers that store data memory addresses the current bank register CBR the extra bank register EBR the...

Page 35: ...m reset the G flag is initialized to 0 2 2 3 Master Interrupt Enable Flag MIE MIE bit 0 of MIEF is a flag that disables or enables all interrupts except for the watchdog timer interrupt MIEF is a 4 bi...

Page 36: ...Register Combinations A11 to A0 in Figure 2 1 indicate data memory addresses 4K nibbles max At system reset the CBR EBR HL and XY registers are initialized to 0 When an interrupt occurs a PUSH HL or P...

Page 37: ...of RA3 to RA0 Registers Within the A15 to A0 of Figure 2 2 A14 to A0 indicate program memory addresses 32K words max RA3 to RA0 are assigned to special function register SFR addresses 0F2H to 0F5H At...

Page 38: ...estores The call stack has 16 levels from address 0H to address 0FH Because the hardware requires 1 level of the call stack during program execution only 15 levels can be used for stack saves The cont...

Page 39: ...d or written by the program Figure 2 4 shows the relation between RSP and the register stack Figure 2 4 Relation between RSP and Register Stack The various registers shown in Figure 2 5 are saved onto...

Page 40: ...area 0000H 0010H 0037H 1FFFH 32 words 1FE0H Test data area 1FDFH Figure 2 6 Program Memory Space Configuration After system reset instruction execution begins at address 0000H The interrupt area from...

Page 41: ...g BANKS are data RAM Figure 2 7 shows the configuration of the data memory space BANK5 BANK2 BANK1 BANK0 5FFH 300H 2FFH 200H 1FFH 100H 0FFH 000H Data RAM area 1024 nibbles Segment register for LCD 256...

Page 42: ...Chapter 3 CPU Control Functions...

Page 43: ...ut causes the CPU to begin system reset processing where registers and pins are initialized The CPU remains in this state until instruction execution begins After system reset processing instruction e...

Page 44: ...imultaneously can be selected by mask option to be 2 bits P0 0 P0 1 3 bits P0 0 P0 1 and P0 2 or 4 bits P0 0 P0 1 P0 2 and P0 3 For details of the mask option settings refer to Section 1 3 Mask Option...

Page 45: ...he 4 bit simultaneous key depression detection setting 1 Hz P0 3 RESET0 P0 0 P0 1 P0 2 P0RST b When P0PUD 1 in the case of the 4 bit simultaneous key depression detection setting 1 Hz P0 3 RESET0 Figu...

Page 46: ...tion performs the equivalent operation of a NOP instruction the interrupt routine is entered When an RTI instruction is used to complete the interrupt routine the main routine is resumed beginning fro...

Page 47: ...omplete the interrupt routine the main routine is resumed beginning from the second instruction after the HALT instruction S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 HALT HLT halt flag Interrupt...

Page 48: ...ecuted then the melody data is transferred to the melody circuit and the HALT instruction is executed again This sequence is indicated in Figure 3 7 Figure 3 7 Melody Data Request Interrupt Operation...

Page 49: ...Chapter 4 Interrupt INT...

Page 50: ...chdog timer interrupt WDTlNT 0010H 2 Melody end interrupt MDlNT 0012H 3 External interrupt 0 PB 4 bit OR input XI0lNT 0014H 4 External interrupt 1 PC 4 bit OR input XI1lNT 0016H 5 External interrupt 2...

Page 51: ...IRQ1 0 QXI2 IRQ1 XI2INT IE1 0 EXI2 IE1 IRQ2 0 QTM0 IRQ2 2 QTM2 IRQ2 1 QTM1 IRQ2 3 QTM3 IRQ2 TM0INT TM1INT TM2INT TM3INT IE2 0 ETM0 IE2 1 ETM1 IE2 2 ETM2 IE2 3 ETM3 IE2 IRQ3 3 Q10Hz IRQ3 T10HzINT IE3...

Page 52: ...sables or enables all interrupts except for the watchdog timer interrupt If MIE is 0 all interrupts are disabled If MIE is 1 all interrupts are enabled with the exception of the watchdog timer When an...

Page 53: ...U at the same time the interrupts are accepted in order of highest priority and low priority interrupts are placed on hold see Table 4 1 for the order of priority When an interrupt is received the mas...

Page 54: ...ble initial value 1 Enable 16 Hz interrupt enable flag 0 Disable initial value 1 Enable 32 Hz interrupt enable flag 0 Disable initial value 1 Enable IE4 054H R W ETM3 ETM2 ETM1 ETM0 Timer 3 interrupt...

Page 55: ...er to 1 allows software interrupts to be generated When an interrupt request is received the corresponding bits of IRQ0 to IRQ4 are cleared to 0 At system reset each bit of IRQ0 through IRQ4 is initia...

Page 56: ...5 request flag 0 No request initial value 1 Request bit 3 bit 2 bit 1 bit 0 IRQ1 056H R W A D interrupt request flag 0 No request initial value 1 Request External interrupt 2 request flag 0 No request...

Page 57: ...er timer 2 overflows bit 1 QTM1 reQuest TiMer 1 Timer 1 interrupt request flag A timer 1 interrupt request is generated whenever timer 1 overflows bit 0 QTM0 reQuest TiMer 0 Timer 0 interrupt request...

Page 58: ...ansmit interrupt request flag A serial port transmit interrupt request is generated when a serial port transmit operation is completed bit 0 QSR Serial port receive interrupt request flag A serial por...

Page 59: ...he time base counter bit1 Q16Hz reQuest 16 Hz 16 Hz interrupt request flag A 16 Hz interrupt request is generated at every falling edge of the 16 Hz output of the time base counter bit 0 Q32Hz reQuest...

Page 60: ...nterrupt factor is generated The following processes are performed when an interrupt is generated 1 MIE and the corresponding interrupt request flag are cleared to 0 2 The program counter PC is saved...

Page 61: ...MIE flag is 0 interrupt disabled state if a watchdog timer interrupt is processed and an RTI instruction is executed the MIE flag will be set to 1 and interrupts enabled Use RTNMI instructions to ret...

Page 62: ...Chapter 5 Clock Generator Circuit OSC...

Page 63: ...nit 700 kHz max between the pins OSC0 and OSC1 and connect a capacitor CL0 between the pins OSC0 and VSS and a capacitor CL1 between the pins OSC1 and VSS When not using the high speed clock generator...

Page 64: ...lock for the time base counter etc and is used as the system clock For the crystal oscillation mode attach an external crystal unit and a capacitor CG as shown in Figure 5 2 Inside the IC Low speed cl...

Page 65: ...mode If the high speed clock is not to be used leave the OSC0 and OSC1 pins open unconnected For the RC oscillation mode attach an external resistor ROSH as shown in Figure 5 3 a For the ceramic osci...

Page 66: ...5 3 lists example external components to be attached when the high speed side ceramic oscillation mode is selected Table 5 2 Typical Oscillation Frequencies for the High Speed Side RC Oscillation Mode...

Page 67: ...ted as the system clock the high speed clock must be in the oscillating state ENOSC 1 The low speed clock generator circuit will continue to oscillate even when the high speed generator circuit is sel...

Page 68: ...ops oscillation of the high speed clock generator circuit At system reset this bit is cleared to 0 stopping oscillation of the high speed clock generator circuit bit 0 CPUCLK This bit selects the syst...

Page 69: ...ion stop ENOSC 0 Stop high speed clock oscillation initial value ENOSC 1 Start high speed clock oscillation Software processing Software processing ENOSC bit 1 of FCON 1 2 High speed clock oscillation...

Page 70: ...ck TWAIT High speed clock Low speed clock 0 5 to 1 0 high speed clocks 0 5 to 1 0 low speed clocks VCH Internal logic power supply VDD VSS 0 V Approx 1 15 V typ Low speed clock Figure 5 4 System Clock...

Page 71: ...Chapter 6 Time Base Counter TBC...

Page 72: ...z 16 Hz 4 Hz 2 Hz output The TBC is initialized to 0000H at system reset 6 2 Time Base Counter Configuration The configuration of the time base counter TBC is shown in Figure 6 1 Figure 6 1 Time Base...

Page 73: ...errupt to the CPU TBC outputs are also used as clocks for various circuits TBC 1 to 8 Hz output and 16 to 128 Hz output can be read through the time base counter register 0 1 TBCR0 TBCR1 A write opera...

Page 74: ...ircuit for LCD bias OPTION A C 1 5 V 3 0 V Without regulator circuit for LCD bias Figure 6 2 Interrupt Timing and Reset Timing by Writing 1 to TBCR0 and TBCR1 Write TBCR0 Shows interrupt timing Write...

Page 75: ...Chapter 7 Timers TIMER...

Page 76: ...locks for timers 1 and 3 respectively Timers can be used not only for pulse generation and time measurement but as baud rate generators used in serial transmission Timer 0 Timer 1 Timer 2 Timer 3 8 bi...

Page 77: ...TM1CK RESETS TM0 overflow OV TM1 overflow Inside the IC Inside the IC Figure 7 2 Timer 1 Configuration Control circuit Frequency measurement control circuit TM2CL TM2CH TM2DL TM2DH 8 Reload 4 4 4 4 D...

Page 78: ...timer data registers store the reload values During the capture mode timer data registers store the capture data Writing to a timer data register causes the contents of the timer counter register to b...

Page 79: ...e same value is also written to the corresponding timer data register However when writing to a timer data register the same value is not written to the corresponding timer counter register Timer 0 Re...

Page 80: ...C2 T1C1 T1C0 06EH R W TM1CL Timer 1 lower bit 3 bit 2 bit 1 bit 0 T1C7 T1C6 T1C5 T1C4 06FH R W TM1CH Timer 1 upper bit 3 bit 2 bit 1 bit 0 T2C3 T2C2 T2C1 T2C0 07AH R W TM2CL Timer 2 lower bit 3 bit 2...

Page 81: ...r However when writing to a timer data register the same value is not written to the corresponding timer counter register Timer 0 Registers To use timer 1 in combination as a 16 bit timer set timer 1...

Page 82: ...k HSCLK high speed clock or external clock T02CK secondary function of PB 2 Note If HSCLK is used as the clock after ENOSC bit 1 of FCON is set to 1 wait for the following time interval before startin...

Page 83: ...r the timer 0 overflow flag When using as a 16 bit timer select timer 0 overflow for the clock Note If HSCLK is used as the clock after ENOSC bit 1 of FCON is set to 1 wait for the following time inte...

Page 84: ...can be selected as TBCCLK low speed clock HSCLK high speed clock or external clock T02CK secondary function of PB 2 Note If HSCLK is used as the clock after ENOSC bit 1 of FCON is set to 1 wait for th...

Page 85: ...ondary function of PB 3 or the timer 2 overflow flag When using as a 16 bit timer select timer 2 overflow for the clock Note If HSCLK is used as the clock after ENOSC bit 1 of FCON is set to 1 wait fo...

Page 86: ...d At system reset TM0CAP is cleared to 0 In the capture mode if the level of the capture input pin PB 0 TM0CAP changes and a capture is generated TM0CAP is automatically set to 1 If TM0STAT is read TM...

Page 87: ...is automatically cleared to 0 bit 0 TM1OVF TiMer1 OVerFlow This bit indicates that the timer counter register has overflowed This bit toggles between 0 and 1 whenever overflow occurs At system reset T...

Page 88: ...gister L TM1CL 06EH 0H Timer 1 counter register H TM1CH 06FH R W 0H Timer 1 control register 0 TM1CON0 072H 0CH Timer 1 control register 1 TM1CON1 073H R W 0CH Timer 1 status register TM1STAT 075H R 0...

Page 89: ...els of the external clock should be longer than 1 cycle of the system clock CLK 7 4 2 Timer Data Registers TM0DL TM0DH TM1DL TM1DH TM2DL TM2DH TM3DL and TM3DH are 4 bit registers In the auto reload mo...

Page 90: ...Figure 7 5 indicates the operation timing for timer counter register overflow Table 7 1 lists timer interrupts Figure 7 5 Timer Counter Register Overflow Timing for Timer 0 Table 7 1 List of Timer Int...

Page 91: ...r data register value is reloaded into the timer counter register and counting begins from the value Setting the RUN bits TM0RUN TM1RUN TM2RUN TM3RUN for each timer control register to 1 will restart...

Page 92: ...mer 1 overflow flag TM1OVF toggles The timer counter register continues to count up from BFFFH Before the timer counter register overflows write the next reload value 534FH to the timer data register...

Page 93: ...a into the timer counter register is inhibited and when the timer counter register overflows counting is restarted from 00H When a capture occurs the capture flags TM0CAP TM1CAP of the timer status re...

Page 94: ...0CAP input changes repeat operations and second capture The high level pulse width t1 of the PB 0 input can be determined as follows t1 F0H 50H tCLK tCLK TMCLK cycle TM0INT is generated when the timer...

Page 95: ...to two cycles of the timer clock Typical examples of valid pulse widths of the trigger signal are shown below When a low speed clock 32 768 kHz is used as the timer clock a pulse width of 62 s or mor...

Page 96: ...signals with required cycles During serial transmission the timer 3 interrupt signal TM3INT is used as the baud rate clock Figure 7 11 indicates frequency measurement mode timing when timers 2 and 3...

Page 97: ...s every 72 counts of the 700 kHz clock in auto reload mode As a result overflow produces a TM3INT cycle tTM3INT of tTM3INT 1 700000 72 0 102857 ms 9722 Hz In the same way assuming that RC oscillation...

Page 98: ...as OPTION A C 1 5 V 3 0 V Without regulator circuit for LCD bias Figure 7 12 illustrates the operation of baud ratae clock for an RC oscillator clock frequency of 600 kHz Figure 7 12 Baud Rate Clock G...

Page 99: ...Chapter 8 100 Hz Timer Counter 100HzTC...

Page 100: ...t 512 Hz of the time base counter to generate a 10 Hz interrupt The 100 Hz timer consists of a 5 6 base counter and two decimal counters 8 2 100 Hz Timer Counter Configuration Figure 8 1 indicates the...

Page 101: ...egister T100CR This is a 4 bit special function register SFR to read the 100 Hz counter of the 100 Hz timer counter The content of the T100CR is latched by a 4 bit latch in T10CR read operation so the...

Page 102: ...is input to the 100 Hz counter T100CR and the carry output of that counter is input to the 10 Hz counter T10CR The T10HzINT signal which is the carry output 10 Hz of the T100CR 100 Hz counter also ge...

Page 103: ...Chapter 9 Watchdog Timer WDT...

Page 104: ...unter WTDC counting the 256 Hz output of the TBC7 of the time base counter TBC and a watchdog timer control register WDTCON to start and clear WDTC 9 2 Watchdog Timer Configuration Figure 9 1 shows th...

Page 105: ...hen writing 0AH while the internal pointer is 1 When WDTC overflows 1FFH 000H a watchdog timer interrupt request WDTINT is generated WDTINT cannot be disabled by the software non maskable interrupt an...

Page 106: ...t of watchdog timer processing Figure 9 2 Watchdog Timer Processing Flowchart System reset Write 5H to WDTCON to WDTCON to WDTCON Processing Write 0AH to WDTCON Processing WDT operation is stopped Int...

Page 107: ...er 0 1 Write 0AH to WDTCON to clear WDTC Internal pointer 1 0 Write 5H to WDTCON Internal pointer 0 1 After a fault occurs 5H is written to WDTCON but is not accepted since the internal pointer is 1 I...

Page 108: ...Chapter 10 Ports INPUT I O PORT...

Page 109: ...interrupt function Port E has the function of RC oscillator clock output for an A D converter the low speed oscillation clock output function the high speed oscillation clock output function and the e...

Page 110: ...ing for each bit using the Port 0 interrupt enable register P0IE The function of transfer to system reset due to simultaneous key depression is the function of transferring to the system reset mode wh...

Page 111: ...g P0PUD to 0 selects pull down resistors and setting to 1 selects pull up resistors Individual specification of pull down or pull up resistors for the pins of port 0 0 to 0 3 is not possible Note Use...

Page 112: ...ll bits in the port interrupt enable register are cleared to 0 and port 0 is initialized to the interrupt disabled state P03IE P02IE P01IE P00IE P0IE 012H R W bit 3 bit 2 bit 1 bit 0 Port 0 3 interrup...

Page 113: ...bit of port 0 generated the interrupt The interrupt vector address for external interrupt 5 is 001EH Figure 10 2 shows an equivalent circuit of external interrupt 5 control P0 0 Level change detection...

Page 114: ...h regulator circuit for LCD bias OPTION A C 1 5 V 3 0 V Without regulator circuit for LCD bias Figure 10 3 Interrupt Generation Timing of External Interrupt 5 128 Hz or 4 kHz P0 0 P0 1 P0 2 P0 3 XI5IN...

Page 115: ...t regulator circuit for LCD bias 10 4 Port A PA 0 PA 3 The ML63611 has Port A a 4 bit input output port 10 4 1 Port A Configuration The circuit configuration for port A is shown in Figure 10 4 Data bu...

Page 116: ...ster PAD is read with the corresponding port direction register bit set to output the value of the bit in the port data register is read When a bit in the port data register PAD is read with the corre...

Page 117: ...a 4 bit special function register SFR which specifies the port input output direction for each bit Pins corresponding to PADIR bits set to 0 are input and those corresponding to bits set to 1 are outp...

Page 118: ...it 2 bit 1 bit 0 Port A 3 input output mode select Input mode bit 3 0 1 bit 2 Port A 2 input output mode select Input mode bit 1 0 1 bit 0 Output mode bit 3 0 0 1 1 bit 2 Output mode bit 1 0 0 1 1 bit...

Page 119: ...tput or high impedance output These modes are selected by the port B control registers 0 1 PBCON0 PBCON1 An external 0 interrupt is assigned as an external interrupt function External 0 interrupts are...

Page 120: ...ode the content of the corresponding bit in the port B data register is output to the port B When a bit in the port B data register is read with the corresponding PBDIR bit set to output the value of...

Page 121: ...ial function register SFR which specifies the port input output direction for each bit Pins corresponding to PBDIR bits set to 0 are input and those corresponding to PBDIR bits set to 1 are output At...

Page 122: ...0 0 1 1 bit 0 PB3MD1 PB3MD0 PB2MD1 PB2MD0 PBCON1 02FH R W bit 3 bit 2 bit 1 bit 0 Port B 3 input output mode select Input mode bit 3 0 1 bit 2 Port B 2 input output mode select Input mode bit 1 0 1 b...

Page 123: ...10 2 Port B Secondary Functions Port Secondary function Description PB 0 TM0CAP Timer 0 capture input PB 1 TM1CAP Timer 1 capture input PB 2 T02CK Timer 0 timer 2 external clock input PB 3 T13CK Timer...

Page 124: ...At system reset all bits in PBIE are cleared to 0 and port B is initialized to the interrupt disabled state PB3IE PB2IE PB1IE PB0IE PBIE 031H R W bit 3 bit 2 bit 1 bit 0 Port B 3 interrupt enable dis...

Page 125: ...E PB3IE PBIE PB 0 PB 1 PB 2 PB 3 IE0 2 EXI0 to interrupt priority encoder IRQ0 IE0 IRQ0 2 QXI0 XI0INT PB0MD1 PB1MD1 PB2MD1 PB3MD1 PBCON0 PBCON1 Figure 10 8 External Interrupt 0 Control Equivalent Circ...

Page 126: ...r LCD bias OPTION A C 1 5 V 3 0 V Without regulator circuit for LCD bias 128 Hz or 4 kHz PB 0 PB 1 PB 2 PB 3 XI0INT QXI0 a When PB0MD1 to PB3MD1 0 b When PB0MD1 and PB1MD1 0 and PB2MD1 and PB3MD 1 128...

Page 127: ...has Port C a 4 bit input output port 10 6 1 Port C Configuration The circuit configuration for port C is shown in Figure 10 10 Figure 10 10 Input Output Port Port C Configuration Output port control P...

Page 128: ...corresponding pin of port C is read At system reset all bits in the port C data register PCD are set to 0 When data is written to the port C data register the actual pin change timing is at the risin...

Page 129: ...0 0 1 1 bit 0 PC3MD1 PC3MD0 PC2MD1 PC2MD0 PCCON1 034H R W bit 3 bit 2 bit 1 bit 0 Port C 3 input output mode select Input mode bit 3 0 1 bit 2 Port C 2 input output mode select Input mode bit 1 0 1 b...

Page 130: ...errupt and to select secondary functions other than external interrupt The external interrupt sampling frequency is either 128 Hz or 4 kHz At system reset all lthe valid bits in the PCMOD0 and PCMOD1...

Page 131: ...t mode irrespective of PC3DIR Port C 2 pin function select 0 Input output port function initial value 1 Serial port receive clock input output RXC function switching of input output mode depends on SR...

Page 132: ...At system reset all bits in PCIE are cleared to 0 and port C is initialized to the interrupt disabled state PC3IE PC2IE PC1IE PC0IE PCIE 036H R W bit 3 bit 2 bit 1 bit 0 Port C 3 interrupt enable dis...

Page 133: ...alent circuit for external interrupt 1 control Level change detect circuit 128 Hz 4 kHz PCMOD PCF PC0IE PC1IE PC2IE PC3IE PCIE PC 0 PC 1 PC 2 PC 3 IE0 3 EXI1 to interrupt priority encoder IRQ0 IE0 IRQ...

Page 134: ...level OR either PC 2 or PC 3 input is at a L level External interrupt 1 is generated when both PC 0 and PC 1 inputs change to a L level AND both PC 2 and PC 3 inputs change to a H level 128 Hz or 4 kH...

Page 135: ...nnel open drain output N channel open drain output CMOS output and high impedance and one of the modes can be selected by the Port E control registers PECON0 and PECON1 The external 2 interrupt has be...

Page 136: ...the corresponding pin of port E is read At system reset all bits in the port E data register PED are reset to 0 When data is written to the port E data register the pin change timing is at the rising...

Page 137: ...0 0 1 1 bit 0 PE3MD1 PE3MD0 PE2MD1 PE2MD0 PECON1 03EH R W bit 3 bit 2 bit 1 bit 0 Port E 3 input output mode select Input mode bit 3 0 1 bit 2 Port E 2 input output mode select Input mode bit 1 0 1 b...

Page 138: ...Secondary function Description PE 0 MON RC oscillation clock output for an A D converter PE 1 TBCCLK Low speed oscillation clock output PE 2 HSCLK High speed oscillation clock output PE 3 INT2 Externa...

Page 139: ...ort level changes the interrupt request signal XI2INT is output and the interrupt request flag QXI2 is set The maximum delay for this sequence is one cycle of the sampling clock 128 Hz or 4 kHz The in...

Page 140: ...Chapter 11 Melody Driver MELODY...

Page 141: ...d as either VDD or VSS using the mask option Refer to Section 1 3 Mask Options and the MOGTOOL Mask Option Generator User s Manual for details The melody circuit can select 29 different tones 63 diffe...

Page 142: ...river TMP3 TMP2 TMP1 TMP0 TEMPO 096H R W bit 3 bit 2 bit 1 bit 0 Melody tempo select bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b...

Page 143: ...not executed melody output may not be stopped even if MSF is set to 0 Example programming is shown below Program part DI 0 Disable master interrupt MIE MSA MDSTOP_DATA 1 Write melody end data to the...

Page 144: ...f Melody Driver Output Pins 11 4 Melody Circuit Operation After the melody tempo is set in the tempo register TEMP execution of an MSA instruction will start operation of the melody circuit The melody...

Page 145: ...tone length Tempo data is set in the tempo register TEMPO The tempos number of counts per minute set by TEMPO are shown in Table 11 1 Table 11 1 Melody Tempo TEMPO TP3 0 TP3 TP2 TP1 TP0 Tempo 0H 0 0...

Page 146: ...e is no melody output for the time specified by the tone length code Values for N1 and N0 are irrelevant Table 11 2 indicates the relations between tones and tone codes Table 11 2 Tone and Tone Code C...

Page 147: ...680 0 1 0 0 1 0 1 25H A2 1771 0 1 0 0 0 1 1 23H Ais2 1872 0 1 0 0 0 0 1 21H B2 1986 0 0 1 1 1 1 1 1FH C3 2114 0 0 1 1 1 0 1 1DH D3 2341 0 0 1 1 0 1 0 1AH Dis3 2521 0 0 1 1 0 0 0 18H E3 2621 0 0 1 0 1...

Page 148: ...e lengths specified by the tone length code and the tempo data are expressed by the following 1 953125 TP 1 L 1 ms where TP is an integer from 1 to 15 and L is an integer from 1 to 63 TP is a value se...

Page 149: ...le Note code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note END L5 L4 L3 L2 L1 L0 N6 N5 N4 N3 N2 N1 N0 Hex G2 0 0 1 0 1 1 1 1 0 0 1 0 1 0 0 0 2F28H D2 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0F35H G2 0 0 0 0 1 1...

Page 150: ...the 8 Hz output of the time base counter is output In the intermittent tone 2 mode a waveform synchronized to the logical AND of 8 Hz signal output and a L level of 1 Hz signal of the time base counte...

Page 151: ...Without regulator circuit for LCD bias Figure 11 5 Buzzer Driver Output Waveforms in Each Output Mode EMBD 8 Hz Output MD ON OFF a MBM1 0 MBM0 0 intermittent tone 1 EMBD 8 Hz Output MD ON OFF 1 Hz EMB...

Page 152: ...Chapter 12 Serial Port SIO...

Page 153: ...Table 12 1 Serial Port Modes Mode Baud rate UART mode Can be set to a user specified value with timers 2 3 TM2 3 Internal clock mode 32 768 kHz Send side Synchronous mode External clock mode From exte...

Page 154: ...3INT from timers 2 3 SRINT to interrupt PC 2 RXC PC 1 TXC PC 0 RXD PC 3 TXD RXCI RXCO TXCI TXCO Transmitter RXD Receiver 32 kHz RXCI 32 kHz 0ACH SRBRT 0AAH SRCON0 0A9H SRBUFH 0ADH SSTAT 0A5H STBUFH OE...

Page 155: ...Transmission STop Bit This bit specifies stop bit length Valid only when bit 0 is 0 UART mode bit 2 1 STL1 Serial Transmission Length select bit 1 STL0 Serial Transmission Length select bit 0 These bi...

Page 156: ...when bit 1 is 1 parity bit bit 1 STPEN Serial Transmission Parity ENable bit This bit specifies whether or not a parity bit is added bit 0 STCLK Serial Transmission CLock select bit This bit specifies...

Page 157: ...d register is a shift register that handles the shift operation in send At system reset it is cleared to 00H The send register cannot be directly accessed from the CPU The hardware send flow is indica...

Page 158: ...thout regulator circuit for LCD bias START Has send data been written to STBUFH BFULL 1 Is interrupt generated or BFULL 0 STBUFL H to send register BFULL 0 Start send STINT generated No Yes No Yes del...

Page 159: ...eive is enabled in the synchronous mode this bit is reset to 0 after receiving one frame of data In the UART mode it does not change bit 2 1 SRL1 Serial Reception Length select bit 1 SRL0 Serial Recep...

Page 160: ...when bit 1 is 1 parity bit bit 1 SRPEN Serial Reception Parity ENable bit This bit specifies whether or not a parity bit is added bit 0 SRCLK Serial Reception CLocK select bit This bit specifies the e...

Page 161: ...6 Receive buffer registers SRBUFL SRBUFH SRBUFL and SRBUFH are 4 bit special function registers SFRs used to hold the received data in serial port reception SRBUFL and SRBUFH are initialized to 0 at...

Page 162: ...a 4 bit special function register SFR used to set the receive baud rate for serial port receive operation in UART mode SRBRT is initialized to 0CH at system reset bit 1 0 BRT1 Baud RaTe select bit 1...

Page 163: ...2 PERR Parity ERRor flag This bit is enabled in both UART and synchronous modes and is set to 1 when the parity for the received data does not match the parity bit attached to the data bit 1 OERR Over...

Page 164: ...data frames Figure 12 3 UART Mode Data Format 2 Synchronous mode The data format for the UART mode is shown in Figure 12 4 SRCON0 1 and STCON0 1 can be set to specify a data bit length of 5 to 8 bits...

Page 165: ...mode is specified by setting STMOD bit 0 of STCON0 to 0 Figure 12 5 is the UART mode send timing chart The UART mode send procedure is described below The send baud rate is set first then the timer a...

Page 166: ...XD STOP PARITY 8 Interrupt request generation TM3INT Less than 3 clocks TBCCLK Less than 2 5 clocks TBCCLK Base clock TM3INT Baud rate clock from timers 2 and 3 WSTBUFH STBUFH write signal LSTSF Send...

Page 167: ...TBUFL H The send data is transferred from STBUFL H to the send register and send operation begins At the same time the interrupt request signal STINT is generated Check that BFULL 0 then set the next...

Page 168: ...L LSTSF Send register STINT TXD Interrupt request generation TBCCLK 2 5 clocks TBCCLK 2 5 clocks max 8 PARITY TBCCLK 3 5 clocks 1 2 3 4 5 6 7 1 2 3 4 TXCO TBCCLK Base clock WSTBUFH STBUFH write signal...

Page 169: ...0 and STCON1 Set send data to STBUFL H The send data is transferred from STBUFL H to the send register and at the same time the interrupt request signal STINT is generated Send operation is started by...

Page 170: ...BFULL LSTSF Send register STINT TXD Interrupt request generation TBCCLK 2 5 clocks TBCCLK 3 5 clocks min 8 1 2 3 4 5 6 7 TXCI TBCCLK Base clock WSTBUFH STBUFH write signal asynchronous to Low speed cl...

Page 171: ...rity bit etc in SRCON0 and SRCON1 Set SREN bit 3 of SRCON0 to 1 to enable receive At the negative edge of the receive data RXD start bit receive operation will start Receive operation ends If a framin...

Page 172: ...STOP BIT 68 BRTC clocks Tc Tc Tc Tc Note Ta BRTC 7 clocks Tb BRTC 6 clocks Tc BRTC 1 clock WSRCONL SRCONL write signal SREN Receive enable disable flag BRTC Base clock for selected baud rate RXD Rece...

Page 173: ...Set SREN bit 3 of SRCON0 to 1 receive enable 3 to 4 BRTC clock cycles later the receive shift clock RXCO is generated and the receive operation starts The shift clock is supplied from the PC 2 RXC pin...

Page 174: ...RXCO Receive shift register initial state SREND LSRBUF SRINIT SRINT SRBUFL H OERR PERR OERR Overrun error flag PERR Parity error flag TBCCLK Base clock WSRCONL SRCONL write signal SREN Receive enable...

Page 175: ...1 receive enable At the positive edge of the receive shift clock input through PC 2 RXC pin the receive data from PC 0 RXD pin is written to the receive register Receive operation ends If an overrun...

Page 176: ...itial state SREND LSRBUF SRINIT SRINT SRBUFL H OERR PERR OERR Overrun error flag PERR Parity error flag TBCCLK Base clock WSRCONL SRCONL write signal SREN Receive enable disable flag SRFREE Signal ind...

Page 177: ...is TB0 bit 0 of STBUFL Set STLMB to 1 to send the MSB first The correspondence between MSB first send data and the send buffer register bit is shown in Figure 12 12 In this case the MSB is TB7 bit 3...

Page 178: ...gister Figure 12 14 Correspondence Between MSB First Receive Data and Receive Buffer Register RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 1 2 3 4 5 6 7 8 RB0 RB1 RB2 RB3 RB4 RB5 RB6 1 2 3 4 5 6 7 Receive first Re...

Page 179: ...Chapter 13 LCD Driver LCD...

Page 180: ...the duty ratio 1 1 to 1 4 DSPCNT is the register for selecting the contrast value However this will not be effective in the OPTION A and OPTION C The LCD driver circuits consist of the segment driver...

Page 181: ...4 13 5 and 13 6 show the peripheral circuits of the LCD driver and segment register Internal data bus Mask option Inside the IC LCD driver circuit 64 lines Bias generator circuit BIAS L0 L64 C1 Voltag...

Page 182: ...bias OPTION A C 1 5 V 3 0 V Without regulator circuit for LCD bias Internal data bus Mask option Inside the IC LCD driver circuit 64 lines Bias generator circuit BIAS L0 L64 C1 Segment register DSPCON...

Page 183: ...D Q L D Q L VDD3 VDD2 VDD1 VSS L4 to L31 L40 to L63 SEG only pins OUT LCD driver Segment register bit select C LCD frame clock Segment register address select D CM4 CM3 CM2 CM1 Common timing signal D3...

Page 184: ...VDD3 VDD2 VDD1 VSS L0 to L3 L36 to L39 SEG or COM pins OUT LCD driver Segment register bit select C LCD frame clock Segment register address select D CM4 CM3 CM2 CM1 Common timing signal D3 D2 D1 D0...

Page 185: ...VDD1 VSS L32 to L35 SEG or output port pins OUT LCD driver Segment register bit select C LCD frame clock Segment register address select D CM4 CM3 CM2 CM1 Common timing signal D3 D2 D1 D0 VSS Data bus...

Page 186: ...L0 to L63 are all set to the VSS level reducing supply current At system reset it is cleared to 0 bit 1 ALLON When ALLON is set to 1 all segment drivers are turned on The ALLON bit has priority over...

Page 187: ...er DSPCNT DSPCNT is a 4 bit special function register SFR used to adjust display contrast At system reset each bit of DSPCNT is initialized to 0 This adjustment function is disabled in the OPTION A an...

Page 188: ...ed as output port pins by the mask option At system reset LP0CON is initialized to 0 LP0MD3 LP0MD2 LP0MD1 LP0MD0 L32 LP0 3 pin output mode select 0 CMOS output initial value 1 N channel open drain out...

Page 189: ...h that common signal to the segment register is output to the segment driver The segment driver uses bit 0 ALLON and bit 1 LCDON of the display control register 0 DSPCON0 to control all OFF and all ON...

Page 190: ...quivalent circuit when the pins L32 to L35 are allocated collectively as an output port In this case the output voltage level will be VDD for the H level output and VSS for the L level output The outp...

Page 191: ...ted and the pin VDD2 VDD1 for the OPTION A is shorted to VDD by multiplying the power supply voltage VDD 1 The configuration of the bias generator circuit of the OPTION B and OPTION D is shown in Figu...

Page 192: ...nerator configuration To LCD driver Bias generator circuit VDD3 VDD2 VDD1 1 5 V 4 5 V 3 0 V 1 5 V VSS C1 ML63611 C2 C12 C2 C3 1 kHz from time base counter VDD VDD3 VDD2 VDD1 0 V Inside the IC VDD Figu...

Page 193: ...nerator configuration To LCD driver Bias generator circuit VDD3 VDD2 VDD1 3 0 V 4 5 V 3 0 V 1 5 V VSS C1 ML63611 C2 C12 C1 C3 1 kHz from time base counter VDD VDD3 VDD2 VDD1 0 V Inside the IC VDD Figu...

Page 194: ...1 15 6H 0 1 1 0 1 08 1 13 1 18 7H 0 1 1 1 1 11 1 16 1 21 8H 1 0 0 0 1 14 1 19 1 24 Light Dark Table 13 3 OPTION D Display Contrast Adjusting Voltages VDD1 Ta 25 C VSS 0 V DSPCNT VDD1 Voltage V CN3 0 C...

Page 195: ...D1 Typ 0 1 VDD Typ 0 1 VDD2 Typ 0 1 VDD Typ 0 1 1 1 2 bias VDD3 Typ 0 2 2 VDD Typ 0 2 Table 13 6 OPTION C Display Contrast Adjusting Voltages VDD1 VDD2 VDD3 VSS 0 V Voltage V BISEL Mode Power supply M...

Page 196: ...LCD Driver Output Waveform Figures 13 11 a and 13 11 b show the output waveforms for 1 4 duty and 1 3 bias and Figures 13 12 a and 13 12 b show the output waveforms for 1 3 duty and 1 3 bias COM1 VDD3...

Page 197: ...3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS COM1 series ON COM2 series OFF COM3 series OFF COM4 series OFF COM1 series OFF COM2 series ON COM3 series OF...

Page 198: ...V 3 0 V With regulator circuit for LCD bias OPTION A C 1 5 V 3 0 V Without regulator circuit for LCD bias COM1 VDD3 Frame frequency 85 3 Hz 1 2 3 1 2 3 VDD2 VDD1 VSS COM2 VDD3 VDD2 VDD1 VSS COM3 VDD3...

Page 199: ...SS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS VDD3 VDD2 VDD1 VSS seg n COM1 series ON COM2 series OFF COM3 series OFF seg n COM1 series OFF COM2 series ON COM3 series...

Page 200: ...Chapter 14 Battery Low Detect Circuit BLD...

Page 201: ...ltage value Four levels of judgment voltage can be selected by the BLDCON bits Judgment voltage values Ta 25 C 1 8 0 1 V 2 0 0 1 V 2 4 0 1 V 2 6 0 1 V Note Does not apply to the OPTION A and OPTION B...

Page 202: ...nt result of the battery low detect circuit This bit is set to 1 when VDD is lower than the judgment voltage selected by LD0 and LD1 and is set to 0 when VDD is higher This bit is 0 when the BLD circu...

Page 203: ...ower supply voltage is lower than the judgment voltage If BLDF is 0 the power supply voltage is higher than the judgment voltage BLDF is valid when ENBL is 1 The judgment circuit of the battery low de...

Page 204: ...Chapter 15 Power Supply Circuit POWER...

Page 205: ...oltage regulator circuits are incorporated in the OPTION A and OPTION C 1 V R1 Output voltage 1 15 V The voltage regulator circuit generating the power supply voltage VCH for the CPU ROM RAM and other...

Page 206: ...age supplied to the internal different voltage regulator circuits This register is available in the OPTION C and OPTION D but not in the OPTION A and OPTION B where the halver circuit cannot be used V...

Page 207: ...D bias generation reference voltage Since the power supply voltage is used as the LCD bias generation reference voltage VDD1 has to be shorted to VDD The OPTION A power supply circuit configuration is...

Page 208: ...s the internal logic power supply VCH and the power supply voltage VXT for the low speed clock generator circuit Further the battery voltage is connected directly to the power supply of the high speed...

Page 209: ...for the LCD bias generation reference voltage The OPTION B power supply circuit configuration is shown in Figure 15 2 OSC1 OSC0 Halver circuit Low speed clock generator circuit 1 2VDD LCD bias circuit...

Page 210: ...supply VCH the power supply voltage VXT for the low speed generator circuit and the reference voltage VDD1 for the LCD bias generator circuit Further the battery voltage is connected directly to the...

Page 211: ...s shown in Figure 15 3 OSC1 OSC0 Halver circuit Low speed clock generator circuit 1 2VDD LCD bias circuit V R2 0 7 V Internal logic circuits ROM RAM CPU etc VHF VDD HC2 HC1 XT1 XT0 VDD3 VDD2 VDD1 C1 C...

Page 212: ...the battery voltage is supplied directly to the different voltage regulator circuits during heavy load During normal load VDD 2 4 to 3 6 V use the halver circuit by setting VH bit 0 of VHCON to 1 and...

Page 213: ...circuit V R2 0 7 V Internal logic circuits ROM RAM CPU etc VHF VDD HC2 HC1 XT1 XT0 VDD3 VDD2 VDD1 C1 C2 VSS Ceramic resonator 30 pF CL0 CL1 CXT 5 to 25 pF C3 1 8 to 3 6 V During heavy load when VDD 1...

Page 214: ...irectly supplied to the different voltage regulator circuits during heavy load During normal load VDD 2 4 to 3 6 V use the halver circuit by setting VH bit 0 of VHCON to 1 and during heavy load VDD le...

Page 215: ...Chapter 16 A D Converter ADC...

Page 216: ...digit decade counter Counter B CNTB0 to 3 which is a 14 bit binary counter and A D converter control registers 0 and 1 ADCON0 ADCON1 By counting oscillation frequencies due to resistance or capacitanc...

Page 217: ...entiation OVFB CLK OVFA Differ entiation Interrupt request ADINT RESETS ADCON0 SADI R EADC R Internal data bus 8 OSCCLK 0 1 4 OM 0 to 3 ADCON1 Decoder RESETS EADC CRON System clock CLK 32 768 kHz 700...

Page 218: ...0 overflow of Counter A is selected and by setting SADI to 1 overflow of Counter B is selected The vector address of ADINT is at address 02FH Bit 0 EADC of ADCON0 is a bit to select operation halt of...

Page 219: ...he same oscillation circuit and a pair of the reference side and the sensor side is usually used Table 16 1 shows the oscillation mode by Bits 3 to 0 OM3 to OM0 of the A D converter control register A...

Page 220: ...on operation when two are operated simultaneously The relation between oscillation frequency fOSCCLK capacitance value C and resistance value R is expressed by the following tOSCCLK kOSCCLK C R where...

Page 221: ...ion with reference resistance RT0 1 and CS0 Figure 16 3 Measurement of CROSC0 by a Resistance Sensor when two point adjustment with two reference resistances OM3 OM2 OM1 OM0 Oscillation mode 0 0 0 1 O...

Page 222: ...A0 and the period of CLK indicates the gate time Counter A 80 000 nA0 Clear Counter B CNTB3 to 0 to 0000H Counter B 0000H Set the bits OM3 to OM0 of ADCON1 to a necessary oscillation mode refer to Tab...

Page 223: ...LK In other words nB0 is directly proportional to the RC oscillation frequency fOSCCLK EADC CLK CRON Counter A 80000 nA0 1 2 3 79996 79997 79998 79999 Gate time nA0 tSYSCLK Overflow 00000 tOSCCLK RC o...

Page 224: ...of VHCON is not required Write ADCON0 to 5H STV 1 SADI 0 EADC 1 after waiting for about 120 s Note The order of to is arbitrary After setting STV bit 2 of ADCON0 to 1 wait for about 120 s and then se...

Page 225: ...LCD bias EADC tSYSCLK CLK CRON Counter A nA1 tSYSCLK nA1 tOSCCLK RC oscillation circuit input waveform IN0 IN1 OSCCLK Counter B 0000H nB1 tOSCCLK Gate time nA1 measured count value nB1 reference count...

Page 226: ...of RC Oscillation Circuit of a Thermistor Using CROSC0 Figure 16 9 shows the temperature characteristics of the resistance value RT0 of the thermistor Thermistor resistance RT0 RT0 f T Temperature T D...

Page 227: ...istics fOSC T using these resistances is ideal if the solid lines of Figures 16 12 and 16 13 can be realized However in reality the dotted lines are obtained due to error factors of the temperature ch...

Page 228: ...g the ratio of them In this example those two steps are taken by the following combination First step RC oscillation by RS0 with Counter A reference mode Second step RC oscillation by RT0 with Counter...

Page 229: ...started by OSCCLK RS0 Overflow nA1 Counting started by CLK 00000 00000 Overflow Counting started by CLK 68 000 Stop Oscillates at RS0 Oscillates at RT0 Stop Stop nB0 tOSCCLK RT0 nA1 tSYSCLK nA0 tSYSCL...

Page 230: ...lver circuit to turned OFF set bit 0 of VHCON to 0 Next wait for about 120 s and then set EADC to 1 In the OPTION A and OPTION B the setting of VHCON is not required Execute the HALT instruction to en...

Page 231: ...ode is released e and the A D conversion operation is stopped f the EADC bit 0 The contents of Counter A becomes the A D conversion value of nA1 and is expressed by the following nA1 nB0 equation c By...

Page 232: ...C oscillation monitor is useful when checking the characteristics of the RC oscillation circuit For instance it is possible to measure the relationship between sensors such as a thermistor and an osci...

Page 233: ...peration of Counter A and Counter B However carry out the setting of this bit only after setting the halver circuit to turned OFF Wait for about 120 s before starting RC oscillation Note that Counter...

Page 234: ...register SFR to select oscillation mode of the RC oscillation circuit OM2 OM1 OM0 ADCON1 0BBH bit 3 bit 2 bit 1 bit 0 R W OM3 Selection of oscillation mode bit 3 bit 2 bit 1 bit 0 0 0 0 0 IN0 pin exte...

Page 235: ...ers SFRs to read write the Counter A Note CNTA0 to CNTA3 are decimal counters and can handle only data from 0H to 9H a2 a1 a0 CNTA0 0B0H bit 3 bit 2 bit 1 bit 0 R W a3 Bits 0 to 3 of Counter A a6 a5 a...

Page 236: ...The A D converter counter B registers CNTB0 to 3 are 4 bit special function registers SFRs to read write the Counter B b2 b1 b0 CNTB0 0B6H bit 3 bit 2 bit 1 bit 0 R W b3 Bits 0 to 3 of Counter B b6 b5...

Page 237: ...H A D converter counter A register 4 CNTA4 0B4H R W 8H A D converter counter B register 0 CNTB0 0B6H R W 0H A D converter counter B register 1 CNTB1 0B7H R W 0H A D converter counter B register 2 CNTB...

Page 238: ...Appendixes...

Page 239: ...0 interrupt enable register P0IE 012H P03IE P02IE P01IE P00IE R W 0H Reserved 013H to 029H Port A control register 0 PACON0 02AH PA1MD1 PA1MD0 PA0MD1 PA0MD0 R W 0H Port A control register 1 PACON1 02B...

Page 240: ...3 IE3 053H E10Hz EST ESR R W 4H Interrupt enable register 4 IE4 054H E2Hz E4Hz E16Hz E32Hz R W 0H Interrupt request register 0 IRQ0 055H QXI1 QXI0 QMD QWDT R W 0H Interrupt request register 1 IRQ1 05...

Page 241: ...ster L TM3DL 078H T3D3 T3D2 T3D1 T3D0 R W 0H Timer 3 data register H TM3DH 079H T3D7 T3D6 T3D5 T3D4 R W 0H Timer 2 counter register L TM2CL 07AH T2C3 T2C2 T2C1 T2C0 R W 0H Timer 2 counter register H T...

Page 242: ...ter counter A register 1 CNTA1 0B1H CA7 CA6 CA5 CA4 R W 0H A D converter counter A register 2 CNTA2 0B2H CA11 CA10 CA9 CA8 R W 0H A D converter counter A register 3 CNTA3 0B3H CA15 CA14 CA13 CA12 R W...

Page 243: ...D bias Appendix B Input Output Circuit Configuration 1 I O Port PA 0 PA 3 PB 0 PB 3 PC 0 PC 3 PE 0 PE 3 2 Input Port P0 0 P0 3 VSS VDD VDD VSS VDD I O Gate control circuit Pull up pull down control Ou...

Page 244: ...V Without regulator circuit for LCD bias 3 Low Speed Oscillation Circuit 4 High Speed Oscillation Circuit 5 RESET TST1 and TST2 Inputs XT0 XT1 CMOS input Time base clock TBCCLK inside the IC VXT OSC0...

Page 245: ...OPTION A VDD3 15 pF Open C3 Open Open 1 0 F 1 0 F 1 0 F C2 0 1 F 0 1 F Ceramic resonator PC 3 PC 2 PC 1 PC 0 PE 3 PE 2 PE 1 PE 0 IN0 CS0 CRT0 RT0 RS0 IN1 CS1 RT1 RS1 C12 CL0 1 When L0 to L3 are made...

Page 246: ...Open C3 Open Open 1 0 F 1 0 F 1 0 F C2 0 1 F 0 1 F PC 3 PC 2 PC 1 PC 0 PE 3 PE 2 PE 1 PE 0 IN0 CS0 CRT0 RT0 RS0 IN1 CS1 RT1 RS1 C12 C1 1 0 F ROSH 1 When L0 to L3 are made COM pins and L4 to L63 are ma...

Page 247: ...F 0 1 F 1 0 F C2 0 1 F 0 1 F Ceramic resonator PC 3 PC 2 PC 1 PC 0 PE 3 PE 2 PE 1 PE 0 IN0 CS0 CRT0 RT0 RS0 IN1 CS1 RT1 RS1 C12 CL0 VDD1 C1 1 0 F 0 1 F 1 When L0 to L3 are made COM pins L4 to L31 and...

Page 248: ...F 1 0 F C2 0 1 F 0 1 F Ceramic resonator PC 3 PC 2 PC 1 PC 0 PE 3 PE 2 PE 1 PE 0 IN0 CS0 CRT0 RT0 RS0 IN1 CS1 RT1 RS1 C12 CL0 VDD1 C1 1 0 F 0 1 F C2 1 0 F 1 When L0 to L3 are made COM pins and L4 to L...

Page 249: ...ERATION W C 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Z C G Flags marked with are affected by instruction execution and those that are not affected with a dash Indicates the instruction code content For a...

Page 250: ...i3 i2 i1 i0 MOV XY i4 XY A i4 XY XY 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 i3 i2 i1 i0 MOV E HL i4 E HL A i4 HL HL 1 1 1 0 0 0 0 0 1 1 1 0 1 0 0 i3 i2 i1 i0 MOV E XY i4 E XY A i4 XY XY 1 1 1 0 0 0 0 0 1 1 1 0...

Page 251: ...0 0 1 0 0 0 0 1 0 1 1 1 0 ROL XY C 3 XY 0 C A XY XY XY 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 ROL E HL C 3E HL 0 C A E HL HL HL 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 ROL E XY C 3E XY 0 C A E XY XY XY...

Page 252: ...HL 1 HL HL 1 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 INC XY XY A XY 1 XY XY 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 INC E HL E HL A E HL 1 HL HL 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 INC E XY E XY A E XY 1...

Page 253: ...i4 HL A HL i4 1 1 0 0 0 0 0 0 0 0 1 0 1 0 i3 i2 i1 i0 ADD XY i4 XY A XY i4 1 1 0 0 0 0 0 0 0 0 1 0 1 1 i3 i2 i1 i0 ADD E HL i4 E HL A E HL i4 1 1 0 0 0 0 0 0 0 0 1 0 0 0 i3 i2 i1 i0 ADD E XY i4 E XY...

Page 254: ...0 0 1 0 1 0 0 1 0 1 1 0 0 ADCD XY A XY A decimal adjustment XY A C XY XY 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 ADCD E HL A E HL A decimal adjustment E HL A C HL HL 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0...

Page 255: ...UB HL i4 HL A HL i4 1 1 0 0 0 0 0 0 1 0 1 0 1 0 i3 i2 i1 i0 SUB XY i4 XY A XY i4 1 1 0 0 0 0 0 0 1 0 1 0 1 1 i3 i2 i1 i0 SUB E HL i4 E HL A E HL i4 1 1 0 0 0 0 0 0 1 0 1 0 0 0 i3 i2 i1 i0 SUB E XY i4...

Page 256: ...0 0 1 0 1 0 0 1 0 1 1 1 1 SBCD XY A XY A decimal adjustment XY A C XY XY 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 1 SBCD E HL A E HL A decimal adjustment E HL A C HL HL 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1...

Page 257: ...CMP HL A XY A HL HL 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 CMP XY A XY A XY XY 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 CMP E HL A E HL A HL HL 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 CMP E XY A E XY A XY...

Page 258: ...r1 r0 AND HL i4 HL A HL i4 1 1 0 0 0 0 0 1 0 0 0 1 1 0 i3 i2 i1 i0 AND XY i4 XY A XY i4 1 1 0 0 0 0 0 1 0 0 0 1 1 1 i3 i2 i1 i0 AND E HL i4 E HL A E HL i4 1 1 0 0 0 0 0 1 0 0 0 1 0 0 i3 i2 i1 i0 AND E...

Page 259: ...cur A cur A 1 1 0 0 1 1 1 1 0 1 r7 r6 r5 r4 r3 r2 r1 r0 XOR HL A HL A HL A 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 XOR XY A XY A XY A 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 XOR E HL A E HL A E HL A 1 1 0 0 0...

Page 260: ...l bits in XY not masked by A XY XY 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 MTST E HL A Testing of all bits in E HL not masked by A HL HL 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 MTST E XY A Testing of all...

Page 261: ...all bits in XY not masked by m A XY 1 1 0 0 0 0 0 1 0 0 0 1 1 1 m3 m2 m1 m0 MCLR E HL m Clearing of all bits in E HL not masked by m A E HL 1 1 0 0 0 0 0 1 0 0 0 1 0 0 m3 m2 m1 m0 MCLR E XY m Clearin...

Page 262: ...of all bits in XY not masked by m A XY 1 1 0 0 0 0 0 0 1 0 0 1 1 1 m3 m2 m1 m0 MSET E HL m Setting of all bits in E HL not masked by m A E HL 1 1 0 0 0 0 0 0 1 0 0 1 0 0 m3 m2 m1 m0 MSET E XY m Settin...

Page 263: ...all bits in XY not masked by m A XY 1 1 0 0 0 0 0 0 0 0 0 1 1 1 m3 m2 m1 m0 MNOT E HL m Inverting of all bits in E HL not masked by m A E HL 1 1 0 0 0 0 0 0 0 0 0 1 0 0 m3 m2 m1 m0 MNOT E XY m Inverti...

Page 264: ...n2 n1 n0 r7 r6 r5 r4 r3 r2 r1 r0 BCLR HL n HL n 0 A HL 1 1 0 0 0 0 0 1 0 0 0 1 1 0 n3 n2 n1 n0 BCLR XY n XY n 0 A XY 1 1 0 0 0 0 0 1 0 0 0 1 1 1 n3 n2 n1 n0 BCLR E HL n E HL n 0 A E HL 1 1 0 0 0 0 0 1...

Page 265: ...n HL n HL n A HL 1 1 0 0 0 0 0 0 0 0 0 1 1 0 n3 n2 n1 n0 BNOT XY n XY n XY n A XY 1 1 0 0 0 0 0 0 0 0 0 1 1 1 n3 n2 n1 n0 BNOT E HL n E HL n E HL n A E HL 1 1 0 0 0 0 0 0 0 0 0 1 0 0 n3 n2 n1 n0 BNOT...

Page 266: ...0 0 0 0 1 1 0 0 1 0 0 1 0 0 MOVHB HL cadr16 HL HL 1 cadr16 15 8 2 3 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 MOVHB XY cadr16 XY XY 1 cadr16 15 8 2 3 a15 a1...

Page 267: ...0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 MOVLB HL cadr16 HL HL 1 cadr16 7 0 2 3 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 MOVLB XY cadr16 XY XY 1 cadr16 7 0 2 3 a15...

Page 268: ...TRUCTION CODE FLAG MNEMONIC OPERATION W C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Z C G FCLR G G 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 FCLR C C 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 FCLR Z Z 0 1 1 0 0 0...

Page 269: ...a7 1 a6 a5 a4 a3 a2 a1 a0 BLE radr8 If C 1 Z 1 then PC Next PC radr8 1 1 0 0 0 0 1 1 1 a7 0 a6 a5 a4 a3 a2 a1 a0 BGT radr8 If C 0 Z 0 then PC Next PC radr8 1 1 0 0 0 0 1 1 1 a7 1 a6 a5 a4 a3 a2 a1 a0...

Page 270: ...0 0 0 0 1 1 0 0 1 INCW RA RA RA 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 MOV CBR i4 CBR i4 1 1 0 0 0 0 0 0 0 0 0 0 1 1 i3 i2 i1 i0 MOV EBR i4 EBR i4 1 1 0 0 0 0 0 0 0 0 0 0 1 0 i3 i2 i1 i0 MOV RA0 i4 RA...

Page 271: ...ML63611 User s Manual First Edition May 2001 Second Edition June 2001 2001 Oki Electric Industry Co Ltd PEUL63611 02...

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