ML63611 User’s Manual
Chapter 4 Interrupt (INT)
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OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
4.3.2 Return from an Interrupt Routine
Return from a watchdog timer interrupt routine is performed with an “RTNMI” instruction.
Return from all other interrupt routines is performed with an “RTI” instruction.
Execution of “RTI” and “RTNMI” instructions both require 1 machine cycle.
When returning from an interrupt routine, the CPU performs the following processes.
(1) The call stack pointer (SP) is decremented by 1. (SP
←
SP–1)
(2) MIE is set to “1” (when an “RTNMI” instruction is used, MIE is restored to its state prior to the interrupt).
(3) 1 is added to the call stack contents and that value is loaded into the program counter (PC)
Note:
•
While the MIE flag is “0” (interrupt disabled state), if a watchdog timer interrupt is processed and an “RTI”
instruction is executed, the MIE flag will be set to “1” and interrupts enabled.
•
Use “RTNMI” instructions to return from watchdog timer interrupts only. Use “RTI” instructions for normal
interrupts.
4.3.3 Interrupt Hold Instructions
Interrupt requests are not received after execution of interrupt hold instruction. They are received after execution
of an instruction other than interrupt hold instructions.
The interrupt hold instructions follow.
•
ROM table reference instructions
•
Stack operation instructions
•
Jump instructions
•
Conditional branch instructions
•
Call/return instructions
•
“EI” (set MIE flag) instructions, “DI” (clear MIE flag) instructions and “MSA cadr15” (start melody output)
instructions within control instructions
Note:
If interrupt hold instructions are to be used consecutively, consider that a generated interrupt will be put on hold for a
considerable amount of time before the interrupt routine begins.
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Summary of Contents for ML63611
Page 9: ...Chapter 1 Overview...
Page 33: ...Chapter 2 CPU and Memory Spaces...
Page 42: ...Chapter 3 CPU Control Functions...
Page 49: ...Chapter 4 Interrupt INT...
Page 62: ...Chapter 5 Clock Generator Circuit OSC...
Page 71: ...Chapter 6 Time Base Counter TBC...
Page 75: ...Chapter 7 Timers TIMER...
Page 99: ...Chapter 8 100 Hz Timer Counter 100HzTC...
Page 103: ...Chapter 9 Watchdog Timer WDT...
Page 108: ...Chapter 10 Ports INPUT I O PORT...
Page 140: ...Chapter 11 Melody Driver MELODY...
Page 152: ...Chapter 12 Serial Port SIO...
Page 179: ...Chapter 13 LCD Driver LCD...
Page 200: ...Chapter 14 Battery Low Detect Circuit BLD...
Page 204: ...Chapter 15 Power Supply Circuit POWER...
Page 215: ...Chapter 16 A D Converter ADC...
Page 238: ...Appendixes...