Oki ML63611, User Manual

Page: 17 / 271

ML63611 User’s Manual
Chapter 1 Overview
1 – 8
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
1.5 Block Diagram
Block diagrams of the ML63611 are shown in Figures 1-1, 1-2, 1-3 and 1-4.
Asterisks (
*
) indicate port secondary functions.
CPU CORE : nX-4/250
TIMING
CON-
TROL
CBR
EBR
H L
X Y
RA
MIE
A
INSTRUCTION
DECODER
IR
BUS
CON-
TROL
ROM
(8 KW)
SP
RSP
C G Z
STACK
CAL.S:16 levels
REG.S:16 levels
PC
ALU
RAM
(1 KN)
INT
TBC
RST
TST
XT0
XT1
XT
RESET
TM0CAP/TM1CAP*
TIMER
(8-bit, 4ch)
TM0OVF/TM1OVF*
T02CK*
T13CK*
SIO
(Sync/Async)
RXC*
TXC*
MELODY
MD
INT
4
TXD*
LCD
&
DSPR
L0 to L63
INT
4
TST2
DAT
A
BUS
WDT
INT
1
TST1
MDB
100HzTC
INT
1
BIAS
V
SS
INPUT
PORT
INT
1
P0.0 to P0.3
I/O
PORT
INT
3
INT
1
INT
2
V/H
PA.0 to PA.3
PB.0 to PB.3
V
DD3
V
DD2
V
DD1
C1
C2
(open) V
HF
(open) HC1
(open) HC2
V/R2
V
CH
V/R1
OSC0
OSC1
OSC
TBCCLK*
OUTPUT
PORT
LP0.0 to LP0.3
(mask option of LCD
segments)
RXD*
PC.0 to PC.3
PE.0 to PE.3
ADC
RT0
CRT0
RS0
CS0
IN0
RT1
RS1
CS1
IN1
INT
1
MON*
HSCLK*
V
DD
Figure 1-1 OPTION A Block Diagram