Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 4 Interrupt (INT)
4 – 4
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
(2) Interrupt enable registers (IE0 to IE4)
IE0, IE1, IE2, IE3, and IE4 are registers that consist of 4 bits each.
A logical AND of the corresponding bits of an interrupt enable register (IE0 to IE4) and an interrupt request
register (IRQ0 to IRQ4) determines whether or not each interrupt request is issued to the CPU. The watchdog
timer interrupt is non-maskable, and is therefore not dependent upon the interrupt enable registers (IE0 to
IE4) and the master interrupt enable register (MIEF).
If multiple interrupts request the CPU at the same time, the interrupts are accepted in order of highest priority
and low priority interrupts are placed on hold (see Table 4-1 for the order of priority).
When an interrupt is received, the master interrupt enable flag (MIE) is cleared to “0”. The corresponding
bits in the interrupt enable registers (IE0 to IE4) do not change.
At system reset, each bit of IE0 through IE4 is initialized to “0”.
EXI1 EXI0 EMD

External interrupt 0 enable flag
0: Disable (initial value)
1: Enable
bit 3 bit 2 bit 1 bit 0
IE0 (050H)
(R/W)
Melody end interrupt enable flag
0: Disable (initial value)
1: Enable
EXI5

EAD
EXI2
External interrupt 5 enable flag
0: Disable (initial value)
1: Enable
bit 3 bit 2 bit 1 bit 0
IE1 (051H)
(R/W)
A/D interrupt enable flag
0: Disable (initial value)
1: Enable
External interrupt 1 enable flag
0: Disable (initial value)
1: Enable
External interrupt 2 enable flag
0: Disable (initial value)
1: Enable