Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 16 A/D Converter (ADC)
16 – 18
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
16.4 Registers Related to A/D Converter
(1) A/D converter control register 0 (ADCON0)
The A/D converter control register 0 (ADCON0) is a 4-bit special function register (SFR) that selects
start/stop of RC oscillation of the A/D converter and the A/D converter interrupt by Counter A or Counter B.
STV SADI
EADC
ADCON0 (0BAH)
bit 3 bit 2 bit 1 bit 0
(R/W)

A/D converter operation standby bit (switching of internal power supply)
0: Regulator voltage (initial value)
1: Power supply voltage
Selection of A/D interrupt
0: Interrupt request by Counter A overflow (initial value)
1: Interrupt request by Counter B overflow
Selection of A/D conversion start/stop
0: Stop of RC oscillation (initial value)
1: RC oscillation start
bit 2: STV
This bit is used for setting the internal power supply as the power supply voltage in order to enable the
operation of Counter A and Counter B. However, carry out the setting of this bit only after setting the
halver circuit to “turned OFF”.
Wait for about 120
µ
s before starting RC oscillation. Note that Counter A or Counter B may operate
improperly if the RC oscillator circuit is made to operate when the internal power supply has not
become stable. When this bit is “0”, the RC oscillator circuit does not operate.
bit 1: SADI
This bit selects the A/D converter interrupt request (ADINT) by overflow of either Counter A or
Counter B. By resetting SADI to “0”, the interrupt request by overflow of Counter A is selected and
by setting SADI to “1”, the interrupt request by overflow of Counter B is selected. At system reset,
SADI is reset to “0”.
bit 0: EADC
This bit selects start/stop of conversion of the A/D converter. When set to “1”, A/D conversion is
started and when reset to “0”, A/D conversion is stopped. When either Counter A or Counter B
overflows while EADC is set to “1” to start counting, the EADC bit is set to “0” automaticaly.
Consequently, EADC indicates that the measurement is in progress. At system reset, the EADC bit is
reset to “0” and the system is in stop state.
When the STV bit is “0”, A/D conversion is not started.