Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 2 CPU and Memory Spaces
2 – 2
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
2.2.2.2 Zero Flag (Z)
The zero flag (Z) is a 1-bit flag that is set to “1” when the contents of the accumulator (A) are loaded with “0H”.
The zero flag is set to “0” when the contents of the accumulator (A) are loaded with a value other than “0H”.
However, the XCH instruction does not change the zero flag. At system reset, the zero flag is initialized to “0”.
2.2.2.3 G Flag (G)
The G flag (G) changes to “1” when the HL, XY or RA registers overflow as the result of execution of a post-
increment register indirect addressing instruction or as the result of an increment instruction for the HL, XY or RA
registers. At system reset, the G flag is initialized to “0”.
2.2.3 Master Interrupt Enable Flag (MIE)
MIE (bit 0 of MIEF) is a flag that disables or enables all interrupts except for the watchdog timer interrupt.
MIEF is a 4-bit register in which bit 0 is the master interrupt enable flag (MIE).
If MIE is “0”, all interrupts are disabled. If MIE is “1”, all interrupts are enabled (with the exception of the
watchdog timer).
When any interrupt is received, MIE is cleared to “0”. MIE is set to “1” by execution of a return from interrupt
instruction (RTI instruction).
If multi-level interrupt processing is to be performed, execute a RTI instruction (MIE
←
“1”) during the interrupt
processing routines.
At system reset, MIE is initialized to “0”. MIEF only supports data reference (R) of data memory through
addressing instructions.
Note:
When setting MIE, use “EI” instructions (MIE
←
“1”) and “DI” instructions (MIE
←
“0”).
!
 
MIE
MIEF (0FFH)
bit 3 bit 2 bit 1 bit 0
(R)

Master Interrupt Enable Flag
0: Interrupts disabled (initial value)
1: Interrupts enabled