Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 12 Serial Port (SIO)
12 – 8
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
bit 3: SRLMB (Serial Reception Least significant bit first or Most significant Bit first)
This bit specifies either LSB first or MSB first for receive data.
bit 2: SRPOE (Serial Reception Parity Odd or Even number bit)
This bit specifies whether the parity bit is even or odd. Valid only when bit 1 is “1” (parity bit).
bit 1: SRPEN (Serial Reception Parity ENable bit)
This bit specifies whether or not a parity bit is added.
bit 0: SRCLK (Serial Reception CLocK select bit)
This bit specifies the external/internal receive clock for synchronous mode. Valid only when
SRMOD (bit 0 of SRCON0) is “1” (synchronous mode).
SRLMB SRPOE SRPEN
SRCLK
LSB/MSB head select
0 : Start at LSB (initial value)
1 : Start at MSB
Odd/even parity select
0 : Odd parity (initial value)
1 : Even parity
Parity set
0 : No parity bit (initial value)
1 : Parity bit
Receive external/internal clock select
0 : External clock mode (initial value)
1 : Internal clock mode
SRCON1 (0ABH)
(R/W)
bit 3 bit 2 bit 1 bit 0