ML63611 User’s Manual
Appendix D
Appendix – 16
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
Arithmetic Instructions (continued)
INSTRUCTION CODE
FLAG
MNEMONIC
OPERATION
W C
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Z C G
ADCD sfr,A
sfr,A
←
decimal adjustment
{sfr + A + C}
1
1
0
0
1
0
0
1
1
0
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
√ √
—
ADCD \cur,A
cur,A
←
decimal adjustment
{cur + A + C}
1
1
0
0
1
1
0
1
1
0
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
√ √
—
ADCD [HL],A
[HL],A
←
decimal adjustment
{[HL] + A + C}
1
1
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
0
√ √
—
ADCD [XY],A
[XY],A
←
decimal adjustment
{[XY] + A + C}
1
1
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
√ √
—
ADCD E:[HL],A
E:[HL],A
←
decimal
adjustment {E:[HL] + A + C}
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
√ √
—
ADCD E:[XY],A
E:[XY],A
←
decimal
adjustment {E:[XY] + A + C}
1
1
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
√ √
—
ADCD [HL+],A
[HL],A
←
decimal adjustment
{[HL] + A + C}, HL
←
HL + 1
1
1
0
0
0
0
0
1
0
1
0
0
1
0
1
1
0
0
√ √ √
ADCD [XY+],A
[XY],A
←
decimal adjustment
{[XY] + A + C}, XY
←
XY + 1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
1
0
0
√ √ √
ADCD E:[HL+],A
E:[HL],A
←
decimal
adjustment {E:[HL] + A + C},
HL
←
HL + 1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
√ √ √
ADCD E:[XY+],A
E:[XY],A
←
decimal
adjustment {E:[XY] + A + C},
XY
←
XY + 1
1
1
0
0
0
0
0
1
0
1
0
0
0
1
1
1
0
0
√ √ √
ADCJ \cur,n
cur,A
←
n-ary adjustment
{cur + C}
1
1
0
0
0
1
0
n
2
n
1
n
0
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
√ √
—
ADCJ [HL],n
[HL],A
←
n-ary adjustment
{[HL] + C}
1
1
0
0
0
0
0
1
1
0
0
0
1
0
0
n
2
n
1
n
0
√ √
—
ADCJ [XY],n
[XY],A
←
n-ary adjustment
{[XY] + C}
1
1
0
0
0
0
0
1
1
0
0
0
1
1
0
n
2
n
1
n
0
√ √
—
ADCJ E:[HL],n
E:[HL],A
←
n-ary adjustment
{E:[HL] + C}
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
n
2
n
1
n
0
√ √
—
ADCJ E:[XY],n
E:[XY],A
←
n-ary adjustment
{E:[XY] + C}
1
1
0
0
0
0
0
1
1
0
0
0
0
1
0
n
2
n
1
n
0
√ √
—
ADCJ [HL+],n
[HL],A
←
n-ary adjustment
{[HL] + C}, HL
←
HL + 1
1
1
0
0
0
0
0
1
1
1
0
0
1
0
0
n
2
n
1
n
0
√ √ √
ADCJ [XY+],n
[XY],A
←
n-ary adjustment
{[XY] + C}, XY
←
XY + 1
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
n
2
n
1
n
0
√ √ √
ADCJ E:[HL+],n
E:[HL],A
←
n-ary adjustment
{E:[HL] + C}, HL
←
HL + 1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
n
2
n
1
n
0
√ √ √
ADCJ E:[XY+],n
E:[XY],A
←
n-ary adjustment
{E:[XY] + C}, XY
←
XY + 1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
n
2
n
1
n
0
√ √ √
Summary of Contents for ML63611
Page 9: ...Chapter 1 Overview...
Page 33: ...Chapter 2 CPU and Memory Spaces...
Page 42: ...Chapter 3 CPU Control Functions...
Page 49: ...Chapter 4 Interrupt INT...
Page 62: ...Chapter 5 Clock Generator Circuit OSC...
Page 71: ...Chapter 6 Time Base Counter TBC...
Page 75: ...Chapter 7 Timers TIMER...
Page 99: ...Chapter 8 100 Hz Timer Counter 100HzTC...
Page 103: ...Chapter 9 Watchdog Timer WDT...
Page 108: ...Chapter 10 Ports INPUT I O PORT...
Page 140: ...Chapter 11 Melody Driver MELODY...
Page 152: ...Chapter 12 Serial Port SIO...
Page 179: ...Chapter 13 LCD Driver LCD...
Page 200: ...Chapter 14 Battery Low Detect Circuit BLD...
Page 204: ...Chapter 15 Power Supply Circuit POWER...
Page 215: ...Chapter 16 A D Converter ADC...
Page 238: ...Appendixes...