ML63611 User’s Manual
Chapter 9 Watchdog Timer (WDT)
9 – 2
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
9.3
Watchdog Timer Control Register (WDTCON)
The watchdog timer control register (WDTCON) is a 4-bit write-only special function register (SFR) used to
start/clear the watchdog timer counter (WDTC).
9.4
Watchdog Timer Operation
At system reset, WDTC (watchdog timer counter) stops counting.
WDTC begins counting by writing “5H” to WDTCON (watchdog timer control register) while the internal pointer
is “0”, and then writing “0AH” (while the internal pointer is “1”).
The internal pointer is cleared to “0” at system reset or when WDTC overflows, and toggles every time a write
operation to WDTCON is performed.
After WDTC is activated, WDTC is cleared by writing “5H” to WDTCON while the internal pointer is “0”, and
then writing “0AH” while the internal pointer is “1”. When WDTC overflows (1FFH
→
000H), a watchdog timer
interrupt request (WDTINT) is generated. WDTINT cannot be disabled by the software (non-maskable interrupt)
and has the highest level of interrupt priority.
The WDTC overflow cycle (T) is given by:
T =
= 2 s
The minus deviation (t) of the WDTC overflow cycle is given by:
t =
= approximately 3.9 ms
Therefore, the WDTC clear cycle (Ct) can be computed as follows.
Ct = T – t = 2 s – 3.9 ms = 1.9961 s
If 32.768 kHz is to be used as the low-speed clock, the software must be programmed to clear WDTC within
1.9961 s.
If the CPU malfunctions due to a power failure or other factor and the WDTC cannot be cleared normally, WDTC
will overflow and WDTINT will be generated. Program the watchdog timer interrupt routine to handle recovery
operations by returning to the normal routine.
Note:
The watchdog timer cannot detect all operating faults. If the CPU malfunctions but WDTC can still be cleared, a fault
will not be detected.
128
×
512
32768 (Hz)
128
32768 (Hz)
d3
d2
d1
d0
WDTCON (09FH)
(W)
bit 3
bit 2
bit 1
bit 0
!
Summary of Contents for ML63611
Page 9: ...Chapter 1 Overview...
Page 33: ...Chapter 2 CPU and Memory Spaces...
Page 42: ...Chapter 3 CPU Control Functions...
Page 49: ...Chapter 4 Interrupt INT...
Page 62: ...Chapter 5 Clock Generator Circuit OSC...
Page 71: ...Chapter 6 Time Base Counter TBC...
Page 75: ...Chapter 7 Timers TIMER...
Page 99: ...Chapter 8 100 Hz Timer Counter 100HzTC...
Page 103: ...Chapter 9 Watchdog Timer WDT...
Page 108: ...Chapter 10 Ports INPUT I O PORT...
Page 140: ...Chapter 11 Melody Driver MELODY...
Page 152: ...Chapter 12 Serial Port SIO...
Page 179: ...Chapter 13 LCD Driver LCD...
Page 200: ...Chapter 14 Battery Low Detect Circuit BLD...
Page 204: ...Chapter 15 Power Supply Circuit POWER...
Page 215: ...Chapter 16 A D Converter ADC...
Page 238: ...Appendixes...