Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 4 Interrupt (INT)
4 – 7
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
bit 1: QMD (reQuest Melody Driver)
Melody end interrupt request flag.
Melody end interrupts are generated when the melody driver outputs the end note data
(END bit = “1”).
bit 0: QWDT (reQuest WatchDog Timer)
Watchdog timer interrupt request flag.
When the watchdog timer is started and then overflow occurs, an interrupt is requested. The
watchdog timer interrupt is non-maskable and does not depend upon the interrupt enable registers
or the master interrupt enable register (MIE).
QXI5

QAD
QXI2
External interrupt 5 request flag
0: No request (initial value)
1: Request
bit 3 bit 2 bit 1 bit 0
IRQ1 (056H)
(R/W)
A/D interrupt request flag
0: No request (initial value)
1: Request
External interrupt 2 request flag
0: No request (initial value)
1: Request
bit 3: QXI5 (reQuest eXternal Interrupt 5)
External interrupt 5 request flag.
The external interrupt 5 is assigned as a secondary function to each bit (P0.0 to 0.3) of port 0.
An external interrupt request is generated through the 4-bit ORed input.
bit 1: QAD (reQuest AD)
A/D interrupt request flag.
If the selected counter A or B overflows, an interrupt request is generated.
bit 0: QXI2 (reQuest eXternal Interrupt 2)
External interrupt 2 request flag.
The external interrupt 2 is assigned as a secondary function of port E.3 (PE.3). Generation of the
external interrupt 2 is triggered by the falling edge of the 128 Hz or 4 kHz output of the time base
counter.