Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 16 A/D Converter (ADC)
16 – 9
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
(2) Operation of Counter B Reference Mode
Figure 16-7 shows the operating timing of Counter B reference mode.
Counter B reference mode is performed by the following procedure: (refer to Figure 16-7)
①
Subtract “nB1” (the count value) from the maximum value +1 (4000H) and set the result to Counter B
(CNTB3 to 0). Here, the product of the count value, “nB1”, and the period of OSCCLK denotes the
gate time.
Counter B
←
(4000 – nB1)
②
Clear Counter A (CNTA4 to 0) to 0000H.
Counter A
←
0000H
③
Set the bits OM3 to 0 of ADCON1 to a necessary oscillation mode (refer to Table 16-1).
④
Set the internal power supply as the power supply voltage by first setting the halver circuit to “turned
OFF” (set bit 0 of VHCON to “0”) and then writing “4H” to ADCON0 (STV = 1). In the OPTION A
and OPTION B, the setting of VHCON is not required.
⑤
Write ADCON0 to “5H” (STV =1, SADI = 0, EADC = 1) after waiting for about 120
µ
s.
Note:
The order of
➀
to
➂
is arbitrary.
After setting STV (bit 2 of ADCON0) to “1”, wait for about 120
µ
s and then set EADC to “1”. In the OPTION A and
OPTION B, the setting of VHCON is not required.
By
⑤
, A/D conversion starts.
Counter B starts counting the RC oscillation clock (OSCCLK) when the EADC bit is set to “1” and the
CRON signal (signal that synchronizes with the falling of the system clock) is set to “1”. When Counter B
overflows, the EADC bit is automatically reset (
⑥
) and the conversion is finished. At the same time, the
A/D converter interrupt request signal (ADINT) becomes “1” to generate the A/D converter interrupt request
(
⑦
).
When the CRON signal is set to “1”, Counter A starts counting the system clock (CLK). When Counter B
overflows and the EADC bit is automatically reset, the counting of counter A is finished.
The last count value of “nA1” at Counter A is the count value of SYSCLK during the gate time
“nB1•t
OSCCLK
” and is expressed by
nA1
≅
nB1 •
∝
In other words, “nA1” is inversely proportional to the RC oscillation frequency (f
OSC
).
!
t
OSCCLK
t
SYSCLK
1
f
OSCCLK