Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 1 Overview
1 – 21
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
1.8 Basic Timing
1.8.1 Basic Timing of CPU Operation
The low-speed oscillation clock from the XT0/XT1 pins or the high-speed oscillation clock from the OSC0/OSC1
pins are used without frequency division as the system clock (CLK). The system clock signal is in phase with the
signal from the XT1 pin or the OSC1 pin.
As shown in Figure 1-6, a single machine cycle is composed of two states, S1 and S2. One state is the interval
from a falling edge of CLK to the falling edge of the next CLK.
Instructions are processed in machine cycle units and each instruction is executed in 1 to 3 machine cycles.
Instructions are classified according to the number of machine cycles: 1-machine-cycle instructions (M1), 2-
machine-cycle instructions (M1 + M2), and 3-machine-cycle instructions (M1 + M2 + M3).
Most instructions are executed in 1 machine cycle.
Figure 1-6 Clock Configuration of Each Machine Cycle
1.8.2 Port I/O Basic Timing
Figure 1-7 shows the basic I/O timing.
During the execution of an instruction that outputs data to a port, setting data (data A) is output at the rising edge
of the clock in the S2 state during the machine cycle of that instruction.
During the execution of an instruction that inputs data from a port, data at the input pin (data B) is captured
internally while the clock is at a “H” level in the S1 state during the machine cycle of that instruction. That data is
transferred to the accumulator at the start of the next machine cycle.
CLK
M1 M1 M2 M1 M2 M3
S1 S2 S1 S2 S2 S1 S2 S1 S2 S1 S2 S1
(2 clocks) (4 clocks) (6 clocks)
1 machine cycle 2 machine cycles 3 machine cycles