Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 3 CPU Control Functions
3 – 3
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
RESET0
Crystal oscillation
output
RESETS
32.768 kHz
125 ms
CPU start
Figure 3-3 Signals When System Reset is Generated
Figure 3-4 shows the timing of transferring to the system reset mode when there is simultaneous key depression at
the input Port 0. When all four bits are pressed simultaneously, all of P0.0 to P0.3 go to the “H” (or the “L”) level,
and the transfer to the system reset mode is made at the second falling edge of the 1 Hz signal.
P0.0
P0.1
P0.2
P0RST
(a) When P0PUD = 0
(in the case of the 4-bit simultaneous key depression detection setting)
1 Hz
P0.3
RESET0
P0.0
P0.1
P0.2
P0RST
(b) When P0PUD = 1
(in the case of the 4-bit simultaneous key depression detection setting)
1 Hz
P0.3
RESET0
Figure 3-4 Timing of Transferring to the System Reset Mode When There Is Simultaneous Key
Depression at the Input Port
Notes:
•
A system reset is given priority over all other executions, and the executions up to that point in time will be
terminated. Therefore, the contents of the RAM and the display registers that are not initialized during the
system reset are not guaranteed.
•
When transferring to the system reset mode if there is simultaneous key depression at the input port, keep the
bits pressed for more than about 2 to 3 seconds.
•
When transferring to the system reset mode by taking the RESET pin to the “H” level, make sure that the width of
the RESET pulse is 1 ms or more.
!