Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 12 Serial Port (SIO)
12 – 21
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
(2) Synchronous internal clock mode
The synchronous internal clock mode is selected by setting SRMOD (bit 0 of SRCON0) to “1” and SRCLK
(bit 0 of SRCON1) to “1”.
Figure 12-9 is the receive timing chart for the synchronous internal clock mode.
The synchronous internal clock receive procedure is indicated below.
First set the receive format (data bit length, parity bit, etc.) in SRCON1 and SRCON0.
①
Set SREN (bit 3 of SRCON0) to “1” (receive enable).
②
3 to 4 BRTC clock cycles later the receive shift clock (RXCO) is generated, and the receive operation
starts.
(The shift clock is supplied from the PC.2/RXC pin.)
③
At the positive edge of RXCO the data received from the PC.0/RXD pin is written to the receive
register.
④
Receive operation ends.
If an overrun error occurs the OERR flag in status register (SSTAT) is set to “1”.
⑤
Received data is transferred to SRBUFL/H.
If a parity error occurs, the PERR flag of status register (SSTAT) is set to “1”.
⑥
The serial port receive interrupt request signal (SRINT) is generated.
⑦
At the negative edge of SRINT, SREN is reset to “0”.
Repeat step
①
required number of times. In the synchronous internal clock mode the receive baud rate is
fixed to TBCCLK.