Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 5 Clock Generator Circuit (OSC)
5 – 8
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
When ENOSC (bit 1 of FCON) is set to “1”, oscillation starts in the mode selected by OSCSEL. At the same time,
the internal logic power supply (V
CH
) switches from the voltage regulator circuit (V/R1) output level (approx. 1.15
V) to the V
DD
level. Next, if CPUCLK is set to “1”, the system clock switches from crystal oscillation output
(TBCCLK) to high-speed clock output (HSCLK).
Figure 5-4 shows the system clock select timing and status of the internal logic power supply (V
CH
).
ENOSC
CPUCLK
OSC1
System clock
T
WAIT
High-speed clock
Low-speed clock
0.5 to 1.0 high-speed clocks 0.5 to 1.0 low-speed clocks
V
CH
Internal logic
power supply
V
DD
V
SS
= 0 V
Approx. 1.15 V
(typ.)
Low-speed clock
Figure 5-4 System Clock Select Timing
In the ceramic oscillation mode, 10 ms are required from the time when ENOSC is set to “1” until the high-speed
clock generator circuit enters the oscillating state. Therefore, in this mode, when switching CPUCLK to a high-
speed setting, wait for an interval of at least T
WAIT
= 10 ms after the rising edge of ENOSC.
In the RC oscillation mode, oscillation begins soon after setting ENOSC to “1”. When switching CPUCLK to a
high-speed setting, wait for an interval of at least T
WAIT
= 300 µs after the rising edge of ENOSC.
When switching from the high-speed mode to the low-speed mode, set the CPUCLK bit to “0”, and sometime
after the next instruction, set the ENOSC bit to “0”.