Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 15 Power Supply Circuit (POWER)
15 – 9
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
15.3.7 OPTION D Power Supply Circuit Configuration
The power supply section of the OPTION D consists of the halver circuit, the voltage regulator circuit (V/R1) for
internal logic power supply, the voltage regulator circuit (V/R2) for the power supply of the low-speed clock
generator circuit, and the voltage regulator circuit (V/R3) for the LCD bias generation reference voltage.
The OPTION D power supply circuit configuration is shown in Figure 15-4.
OSC1
OSC0
Halver circuit
Low-speed clock
generator circuit
1/2V
DD
LCD bias circuit
V/R2
0.7 V
Internal logic circuits (ROM, RAM, CPU, etc.)
V
HF
V
DD
HC2
HC1
XT1
XT0
V
DD3
V
DD2
V
DD1
C1
C2
V
SS
Ceramic resonator
30 pF
C
L0
C
L1
C
XT
5 to 25 pF
C
3
1.8 to 3.6 V
During heavy load
(when V
DD
= 1.8 to 2.4 V)
VH (bit 0 of VHCON) = “0”
V
HF
V
XT
C
G
0.1
µ
F
3.0 V
C
V
High-speed clock generator circuit
ENOSC (bit 1 of FCON) = “0”
V/R1
1.15 V
C
1
32.768 kHz
1.0
µ
F
1.0
µ
F
1.0
µ
F
0.1
µ
F
0.1
µ
F
V
XT
ENOSC (bit 1 of FCON) = “1”
C
CH
V
CH
C
12
ML63611
Software selection
During normal load
(when V
DD
= 2.4 to 3.6 V)
VH (bit 0 of VHCON) = “1”
0.1
µ
F
C
HF
0.1
µ
F
C
H12
C
2
1.0
µ
F
V/R3
0.95 V
V
DD1
0.95 V min.
1.40 V max.
V
CH
Figure 15-4 OPTION D Power Supply Circuit Configuration
Note:
When operating with the high-speed clock, first set VH (bit 0 of VHCON) to “0” and then set ENOSC (bit 1 of
FCON) to “1”.
If VH is the “1” state, the halver circuit output voltage (V
HF
) becomes the power supply (V
CH
) for the internal logic
circuits and the operation will not be made properly.
!