Oki ML63611, User Manual

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ML63611 User’s Manual
Chapter 8 100 Hz Timer Counter (100HzTC)
8 – 3
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
8.4 100 Hz Timer Counter Operation
The 100 Hz timer counter begins counting when bit 0 (ECNT) of the 100 Hz timer counter control register
(T100CON) is set to “1”. The 512 Hz output of the time base counter is divided into 100 Hz by the 5/6-base
counter.
The 100 Hz signal is input to the 100 Hz counter (T100CR) and the carry output of that counter is input to the 10
Hz counter (T10CR). The T10HzINT signal, which is the carry output (10 Hz) of the T100CR 100 Hz counter,
also generates an interrupt request, setting bit 3 (Q10Hz) of interrupt request registers 3 (IRQ3) to “1”.
If either T100CR or T10CR is written to, both are reset to “0”. The write data used has no significance. For
example, the “MOV T100CR,A” instruction is not dependent on the contents of the accumulator.
If T10CR is read, the contents of T100CR at that time are latched to the 4-bit latch. Therefore, the contents of
T100CR at the time T10CR is read can be read correctly.