NXP Semiconductors K22F series, Reference Manual, Page: 987 / 1407

update FTM counter with
CNTIN register value
update the channels outputs
with their initial value
clear SWSYNC bit
end
FTM counter is reset by
software trigger
legacy
PWM synchronization
end
clear TRIGn bit
HWTRIGMODE
bit ?
= 1
= 0
update the channels outputs
with their initial value
update FTM counter with
CNTIN register value
wait hardware trigger n
enhanced PWM synchronization
FTM counter is reset by
hardware trigger
begin
= 1
= 1
= 1
= 1
end end
HWRSTCNT
bit ?
SWRSTCNT
bit ?
SWSYNC
bit ?
software
trigger
SYNCMODE
bit ?
hardware
trigger
TRIGn
bit ?
= 0
= 0
= 0
= 0
= 0
1 =
Figure 39-59. FTM counter synchronization flowchart
In the case of legacy PWM synchronization, the FTM counter synchronization depends
on REINIT and PWMSYNC bits according to the following description.
If (SYNCMODE = 0), (REINIT = 1), and (PWMSYNC = 0) then this synchronization is
made on the next enabled trigger event. If the trigger event was a software trigger then
the SWSYNC bit is cleared according to the following example. If the trigger event was a
hardware trigger then the TRIGn bit is cleared according to
Hardware trigger . Examples
with software and hardware triggers follow.
Chapter 39 FlexTimer Module (FTM)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 987