NXP Semiconductors K22F series, Reference Manual, Page: 723 / 1407

Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
S0 S1 S2 S3 S0 WS
Wait State
Write-Bus Cycle (1 Wait State)
S0 S1 S2 S3 S0 WS
W
rit
e1WS
.s
vg
TIP
FB_AD[31: X ] indicates a 32-, 16-, 8-bit address/data bus (or custom size).
FB_AD[ Y :0] indicates a 32-, 16-, 8-bit address bus (or custom size).
FB_AD[ Y :0]
FB_AD[31: X ]
Figure 31-16. Write-Bus Cycle (One Wait State)
31.4.11.4.2 Address Setup and Hold
The timing of the assertion and negation of the chip selects, byte selects, and output
enable can be programmed on a chip-select basis. Each chip-select can be programmed to
assert one to four clocks after transfer start/address-latch enable (FB_TS/FB_ALE) is
asserted. The following figures show read- and write-bus cycles with two clocks of
address setup respectively.
Chapter 31 External Bus Interface (FlexBus)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 723