NXP Semiconductors K22F series, Reference Manual, Page: 160 / 1407

Table 5-2. Module clocks (continued)
Module Bus interface clock Internal clocks I/O interface clocks
UART2 Bus clock — —
LPUART0 Bus clock LPUART0 clock —
I
2
S Bus clock I
2
S master clock I2S_TX_BCLK,
I2S_RX_BCLK
Human-machine interfaces
GPIO Platform clock — —
5.7.1 PMC 1-kHz LPO clock
The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all
modes of operation, including all low power modes except VLLS0. This 1-kHz source is
commonly referred to as LPO clock or 1-kHz LPO clock.
5.7.2 IRC 48MHz clock
The integrated 48 MHz internal reference clock source (IRC48MCLK) is available in
High Speed Run, Run, WAIT and Stop modes of operation. IRC48MCLK is also
available in Compute Only, PSTOP2 and PSTOP1 modes of operation when entered
from Run mode. IRC48MCLK is forced disabled when the MCU transitions into VLPS,
LLSx, and VLLSx low power modes.
NOTE
IRC48MCLK is not forced disabled in Stop modes and should
be disabled by software prior to Stop entry unless it is required.
IRC48MCLK is not forced disabled in VLPR and should be
disabled by software prior to VLPR entry.
IRC48MCLK is enabled via any of the following control settings while operating in these
modes:
• USB Control register enables — enabled when
USB_CLK_RECOVER_IRC_EN[IRC_EN]=1
• MCG Control register selects IRC48 MHz clock (enabled when
MCG_C7[OSCSEL]=10) and either MCG is configured in an external clocking
mode (PBE, BLPE, PEE, FBE or FEE) or MCG_C5[PLLCLKEN0] = 1.
• SIM Control register selects IRC48 MHz clock — enabled when
SIM_SOPT2[PLLFLLSEL]=11
Module clocks
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
160 NXP Semiconductors