NXP Semiconductors K22F series, Reference Manual, Page: 119 / 1407

Signal
multiplexing
Register
access
Peripheral
bridge
Module signals
Low-power timer
Figure 3-43. LPTMR configuration
Table 3-58. Reference links to related information
Topic Related module Reference
Full description Low-power timer Low-power timer
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
3.8.4.1 LPTMR prescaler/glitch filter clocking options
The prescaler and glitch filter of the LPTMR module can be clocked from one of four
sources determined by the LPTMR0_PSR[PCS] bitfield. The following table shows the
chip-specific clock assignments for this bitfield.
NOTE
The chosen clock must remain enabled if the LPTMR is to
continue operating in all required low-power modes.
LPTMR0_PSR[PCS] Prescaler/glitch filter clock
number
Chip clock
00 0 MCGIRCLK — internal reference clock
(not available in VLPS/LLS/VLLS
modes)
01 1 LPO — 1 kHz clock (not available in
VLLS0 mode)
10 2 ERCLK32K — secondary external
reference clock
11 3 OSCERCLK_UNDIV — Undivided
external reference clock (not available in
VLLS0 mode)
See Clock Distribution for more details on these clocks.
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 119