NXP Semiconductors K22F series, Reference Manual, Page: 822 / 1407

• If enabled, the Filter block will incur up to one bus clock additional latency penalty
on COUT due to the fact that COUT, which is crossing clock domain boundaries,
must be resynchronized to the bus clock.
• CR1[WE] and CR1[SE] are mutually exclusive.
35.2 Memory map/register definitions
CMP memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_3000 CMP Control Register 0 (CMP0_CR0) 8 R/W 00h 35.2.1/822
4007_3001 CMP Control Register 1 (CMP0_CR1) 8 R/W 00h 35.2.2/823
4007_3002 CMP Filter Period Register (CMP0_FPR) 8 R/W 00h 35.2.3/825
4007_3003 CMP Status and Control Register (CMP0_SCR) 8 R/W 00h 35.2.4/825
4007_3004 DAC Control Register (CMP0_DACCR) 8 R/W 00h 35.2.5/826
4007_3005 MUX Control Register (CMP0_MUXCR) 8 R/W 00h 35.2.6/827
4007_3008 CMP Control Register 0 (CMP1_CR0) 8 R/W 00h 35.2.1/822
4007_3009 CMP Control Register 1 (CMP1_CR1) 8 R/W 00h 35.2.2/823
4007_300A CMP Filter Period Register (CMP1_FPR) 8 R/W 00h 35.2.3/825
4007_300B CMP Status and Control Register (CMP1_SCR) 8 R/W 00h 35.2.4/825
4007_300C DAC Control Register (CMP1_DACCR) 8 R/W 00h 35.2.5/826
4007_300D MUX Control Register (CMP1_MUXCR) 8 R/W 00h 35.2.6/827
35.2.1 CMP Control Register 0 (CMPx_CR0)
Address: Base a 0h offset
Bit 7 6 5 4 3 2 1 0
Read 0
FILTER_CNT
0 0
HYSTCTR
Write
Reset 0 0 0 0 0 0 0 0
CMPx_CR0 field descriptions
Field Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6–4
FILTER_CNT
Filter Sample Count
Table continues on the next page...
Memory map/register definitions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
822 NXP Semiconductors