NXP Semiconductors K22F series, Reference Manual, Page: 562 / 1407

25.4.3.1 MCG Internal Reference Clock
The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other on-
chip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is
driven by either the fast internal reference clock (4 MHz IRC which can be divided down
by the FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS
clock frequency can be re-targeted by trimming the period of its IRCS selected internal
reference clock. This can be done by writing a new trim value to the
C3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is selected or by writing a
new trim value to C4[FCTRIM]:C2[FCFTRIM] when the fast IRC clock is selected. The
internal reference clock period is proportional to the trim value written.
C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM]:C2[FCFTRIM] (if
C2[IRCS]=1) bits affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI
modes. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the
MCGOUTCLK frequency if the MCG is in FEI mode.
Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and
C1[IREFSTEN], otherwise this clock is disabled in Stop mode.
25.4.4 External Reference Clock
The MCG module can support an external reference clock in all modes. See the device
datasheet for external reference frequency range. When C1[IREFS] is set, the external
reference clock will not be used by the FLL or PLL. In these modes, the frequency can be
equal to the maximum frequency the chip-level timing specifications will support.
If any of the CME bits are asserted the slow internal reference clock is enabled along
with the enabled external clock monitor. For the case when C6[CME0]=1, a loss of clock
is detected if the OSC0 external reference falls below a minimum frequency (f
loc_high
or
f
loc_low
depending on C2[RANGE0]). For the case when C8[CME1]=1, a loss of clock is
detected if the RTC external reference falls below a minimum frequency (f
loc_low
).
NOTE
All clock monitors must be disabled before entering these low-
power modes: Stop, VLPS, VLPR, VLPW, LLS, and VLLSx.
On detecting a loss-of-clock event, the MCU generates a system reset if the respective
LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG
generates a LOCS interrupt request. In the case where a OSC loss of clock is detected, the
PLL LOCK status bit is cleared.
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
562 NXP Semiconductors