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loading point. If the trigger event was a hardware trigger, then the trigger enable bit
(TRIGn) is cleared according to 

Hardware trigger

. Examples with software and hardware

triggers follow.

system clock

selected loading point

MOD register is updated

write 1 to SWSYNC bit

SWSYNC bit

software trigger event

Figure 39-47. MOD synchronization with (SYNCMODE = 0), (PWMSYNC = 0), (REINIT =

0), and software trigger was used

system clock

selected loading point

MOD register is updated

write 1 to TRIG0 bit

TRIG0 bit

trigger 0 event

Figure 39-48. MOD synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0),

(PWMSYNC = 0), (REINIT = 0), and a hardware trigger was used

If (SYNCMODE = 0), (PWMSYNC = 0), and (REINIT = 1), then this synchronization is
made on the next enabled trigger event. If the trigger event was a software trigger, then
the SWSYNC bit is cleared according to the following example. If the trigger event was a
hardware trigger, then the TRIGn bit is cleared according to 

Hardware trigger

. Examples

with software and hardware triggers follow.

Functional description

K22F Sub-Family Reference Manual, Rev. 4, 08/2016

978

NXP Semiconductors

Summary of Contents for K22F series

Page 1: ...ub Family Reference Manual Supports MK22FN512VDC12 MK22FN512VLL12 MK22FN512VLH12 MK22FN512VMP12 MK22FN512VFX12 MK22FN512CAP12R MK22FN512CBP12R MK22FN256CAP12R Document Number K22P121M120SF7RM Rev 4 08...

Page 2: ...K22F Sub Family Reference Manual Rev 4 08 2016 2 NXP Semiconductors...

Page 3: ...s 49 2 2 1 ARM Cortex M4 Core Modules 50 2 2 2 System Modules 51 2 2 3 Memories and Memory Interfaces 52 2 2 4 Clocks 52 2 2 5 Security and Integrity modules 53 2 2 6 Analog modules 53 2 2 7 Timer mod...

Page 4: ...pheral Bridge Configuration 73 3 3 8 DMA request multiplexer configuration 74 3 3 9 DMA Controller Configuration 77 3 3 10 External Watchdog Monitor EWM Configuration 78 3 3 11 Watchdog Configuration...

Page 5: ...n 118 3 8 5 RTC configuration 120 3 9 Communication interfaces 121 3 9 1 Universal Serial Bus USB FS Subsystem 121 3 9 2 SPI configuration 126 3 9 3 I2C Configuration 130 3 9 4 UART Configuration 131...

Page 6: ...clocking diagram 151 5 4 Clock definitions 152 5 4 1 Device clock summary 153 5 5 Internal clocking requirements 156 5 5 1 Clock divider values after reset 157 5 5 2 VLPR mode clocking 157 5 6 Clock G...

Page 7: ...Boot sequence 179 Chapter 7 Power Management 7 1 Introduction 181 7 2 Clocking modes 181 7 2 1 Partial Stop 181 7 2 2 DMA Wakeup 182 7 2 3 Compute Operation 183 7 2 4 Peripheral Doze 184 7 2 5 Clock...

Page 8: ...g Port 201 9 2 1 JTAG to SWD change sequence 202 9 2 2 JTAG to cJTAG change sequence 202 9 3 Debug Port Pin Descriptions 203 9 4 System TAP connection 203 9 4 1 IR Codes 203 9 5 JTAG status and contro...

Page 9: ...dule Signal Description Tables 228 10 4 1 Core Modules 228 10 4 2 System Modules 229 10 4 3 Clock Modules 229 10 4 4 Memories and Memory Interfaces 230 10 4 5 Analog 233 10 4 6 Timer Modules 234 10 4...

Page 10: ...roduction 259 12 1 1 Features 259 12 2 Memory map and register definition 260 12 2 1 System Options Register 1 SIM_SOPT1 261 12 2 2 SOPT1 Configuration Register SIM_SOPT1CFG 263 12 2 3 System Options...

Page 11: ...1 12 3 Functional description 291 Chapter 13 Kinetis Flashloader 13 1 Chip Specific Information 293 13 2 Introduction 293 13 3 Functional Description 295 13 3 1 Memory Maps 295 13 3 2 Start up Process...

Page 12: ...r 15 System Mode Controller SMC 15 1 Introduction 351 15 2 Modes of operation 351 15 3 Memory map and register descriptions 353 15 3 1 Power Mode Protection register SMC_PMPROT 354 15 3 2 Power Mode C...

Page 13: ...1 1 Features 379 17 1 2 Modes of operation 380 17 1 3 Block diagram 381 17 2 LLWU signal descriptions 382 17 3 Memory map register definition 382 17 3 1 LLWU Pin Enable 1 register LLWU_PE1 383 17 3 2...

Page 14: ...r MCM_ISCR 401 18 2 5 Compute Operation Control Register MCM_CPO 404 18 3 Functional description 405 18 3 1 Interrupts 405 Chapter 19 Crossbar Switch Lite AXBS Lite 19 1 Introduction 407 19 1 1 Featur...

Page 15: ...ity 417 21 4 2 DMA channels with no triggering capability 419 21 4 3 Always enabled DMA sources 420 21 5 Initialization application information 421 21 5 1 Reset 421 21 5 2 Enabling and configuring sou...

Page 16: ...HRS 463 22 3 20 Enable Asynchronous Request in Stop Register DMA_EARS 466 22 3 21 Channel n Priority Register DMA_DCHPRIn 468 22 3 22 TCD Source Address DMA_TCDn_SADDR 469 22 3 23 TCD Signed Source Ad...

Page 17: ...2 4 1 eDMA basic data flow 483 22 4 2 Fault reporting and handling 486 22 4 3 Channel preemption 489 22 4 4 Performance 489 22 5 Initialization application information 493 22 5 1 eDMA initialization 4...

Page 18: ...4 6 EWM Interrupt 518 23 4 7 Counter clock prescaler 518 Chapter 24 Watchdog Timer WDOG 24 1 Introduction 519 24 2 Features 519 24 3 Functional overview 520 24 3 1 Unlocking and updating the watchdog...

Page 19: ...og Timer Output Register Low WDOG_TMROUTL 534 24 7 11 Watchdog Reset Count register WDOG_RSTCNT 535 24 7 12 Watchdog Prescaler register WDOG_PRESC 535 24 8 Watchdog operation with 8 bit access 535 24...

Page 20: ...557 25 4 Functional description 557 25 4 1 MCG mode state diagram 557 25 4 2 Low power bit usage 561 25 4 3 MCG Internal Reference Clocks 561 25 4 4 External Reference Clock 562 25 4 5 MCG Fixed Freq...

Page 21: ...Interrupts 588 Chapter 27 RTC Oscillator OSC32K 27 1 Introduction 589 27 1 1 Features and Modes 589 27 1 2 Block Diagram 589 27 2 RTC Signal Descriptions 590 27 2 1 EXTAL32 Oscillator Input 590 27 2...

Page 22: ...word FMC_DATAW0SnL 611 28 4 10 Cache Data Storage upper word FMC_DATAW1SnU 611 28 4 11 Cache Data Storage lower word FMC_DATAW1SnL 612 28 4 12 Cache Data Storage upper word FMC_DATAW2SnU 612 28 4 13 C...

Page 23: ...1 29 4 5 Functional Modes of Operation 651 29 4 6 Flash Reads and Ignored Writes 651 29 4 7 Read While Write RWW 652 29 4 8 Flash Program and Erase 652 29 4 9 Flash Command Operations 652 29 4 10 Marg...

Page 24: ...sk Register FB_CSMRn 698 31 3 3 Chip Select Control Register FB_CSCRn 699 31 3 4 Chip Select port Multiplexing Control Register FB_CSPMCR 702 31 4 Functional description 703 31 4 1 Use cases 703 31 4...

Page 25: ...C Data register CRC_DATA 743 32 2 2 CRC Polynomial register CRC_GPOLY 744 32 2 3 CRC Control register CRC_CTRL 744 32 3 Functional description 745 32 3 1 CRC initialization reinitialization 745 32 3 2...

Page 26: ...erence Select 765 34 2 4 Analog Channel Inputs ADx 766 34 2 5 Differential Analog Channel Inputs DADx 766 34 3 Memory map and register definitions 766 34 3 1 ADC Status and Control Registers 1 ADCx_SC...

Page 27: ...4 787 34 3 21 ADC Minus Side General Calibration Value Register ADCx_CLM3 787 34 3 22 ADC Minus Side General Calibration Value Register ADCx_CLM2 788 34 3 23 ADC Minus Side General Calibration Value R...

Page 28: ...35 2 3 CMP Filter Period Register CMPx_FPR 825 35 2 4 CMP Status and Control Register CMPx_SCR 825 35 2 5 DAC Control Register CMPx_DACCR 826 35 2 6 MUX Control Register CMPx_MUXCR 827 35 3 Functional...

Page 29: ...4 5 DAC Control Register 1 DACx_C1 852 36 4 6 DAC Control Register 2 DACx_C2 853 36 5 Functional description 853 36 5 1 DAC data buffer operation 853 36 5 2 DMA operation 855 36 5 3 Resets 855 36 5 4...

Page 30: ...ns 871 38 3 Memory map and register definition 871 38 3 1 Status and Control register PDBx_SC 873 38 3 2 Modulus register PDBx_MOD 876 38 3 3 Counter register PDBx_CNT 876 38 3 4 Interrupt Delay regis...

Page 31: ...of operation 893 39 1 4 Block diagram 894 39 2 FTM signal descriptions 896 39 3 Memory map and register definition 896 39 3 1 Memory map 896 39 3 2 Register descriptions 897 39 3 3 Status And Control...

Page 32: ...arity FTMx_FLTPOL 938 39 3 24 Synchronization Configuration FTMx_SYNCONF 939 39 3 25 FTM Inverting Control FTMx_INVCTRL 941 39 3 26 FTM Software Output Control FTMx_SWOCTRL 942 39 3 27 FTM PWM Load FT...

Page 33: ...mode 1014 39 4 26 BDM mode 1019 39 4 27 Intermediate load 1020 39 4 28 Global time base GTB 1022 39 5 Reset overview 1024 39 6 FTM Interrupts 1025 39 6 1 Timer Overflow Interrupt 1026 39 6 2 Channel...

Page 34: ...1 Features 1041 41 1 2 Modes of operation 1041 41 2 LPTMR signal descriptions 1042 41 2 1 Detailed signal descriptions 1042 41 3 Memory map and register definition 1042 41 3 1 Low Power Timer Control...

Page 35: ...Control Register RTC_CR 1056 42 2 6 RTC Status Register RTC_SR 1058 42 2 7 RTC Lock Register RTC_LR 1059 42 2 8 RTC Interrupt Enable Register RTC_IER 1060 42 2 9 RTC Write Access Register RTC_WAR 106...

Page 36: ...egister USBx_PERID 1084 43 4 2 Peripheral ID Complement register USBx_IDCOMP 1085 43 4 3 Peripheral Revision register USBx_REV 1085 43 4 4 Peripheral Additional Info register USBx_ADDINFO 1086 43 4 5...

Page 37: ...USB Transceiver Control register 0 USBx_USBTRC0 1105 43 4 28 Frame Adjust Register USBx_USBFRMADJUST 1106 43 4 29 USB Clock recovery control USBx_CLK_RECOVER_CTRL 1107 43 4 30 IRC48M oscillator enabl...

Page 38: ...2 6 SIN Serial Input 1129 45 2 7 SOUT Serial Output 1130 45 3 Memory Map Register Definition 1130 45 3 1 Module Configuration Register SPIx_MCR 1132 45 3 2 Transfer Count Register SPIx_TCR 1135 45 3 3...

Page 39: ...2 Switching Master and Slave mode 1175 45 5 3 Initializing Module in Master Slave Modes 1176 45 5 4 Baud rate settings 1176 45 5 5 Delay settings 1177 45 5 6 Calculation of FIFO pointer addresses 1178...

Page 40: ...03 46 4 4 System management bus specification 1204 46 4 5 Resets 1206 46 4 6 Interrupts 1206 46 4 7 Programmable input glitch filter 1209 46 4 8 Address matching wake up 1209 46 4 9 DMA support 1210 4...

Page 41: ...egister UARTx_SFIFO 1244 47 3 19 UART FIFO Transmit Watermark UARTx_TWFIFO 1245 47 3 20 UART FIFO Transmit Count UARTx_TCFIFO 1246 47 3 21 UART FIFO Receive Watermark UARTx_RWFIFO 1246 47 3 22 UART FI...

Page 42: ...ormat non ISO 7816 1281 47 4 5 Single wire operation 1284 47 4 6 Loop operation 1285 47 4 7 ISO 7816 smartcard support 1285 47 4 8 Infrared interface 1290 47 5 Reset 1292 47 6 System level interrupt s...

Page 43: ...T Data Register LPUARTx_DATA 1318 48 2 5 LPUART Match Address Register LPUARTx_MATCH 1320 48 2 6 LPUART Modem IrDA Register LPUARTx_MODIR 1320 48 3 Functional description 1322 48 3 1 Baud rate generat...

Page 44: ...eive Configuration 1 Register I2Sx_RCR1 1355 49 3 12 SAI Receive Configuration 2 Register I2Sx_RCR2 1355 49 3 13 SAI Receive Configuration 3 Register I2Sx_RCR3 1357 49 3 14 SAI Receive Configuration 4...

Page 45: ...Port Data Input Register GPIOx_PDIR 1381 50 2 6 Port Data Direction Register GPIOx_PDDR 1381 50 3 Functional description 1382 50 3 1 General purpose input 1382 50 3 2 General purpose output 1382 Chap...

Page 46: ...unctional description 1389 51 4 1 JTAGC reset configuration 1389 51 4 2 IEEE 1149 1 2001 JTAG Test Access Port 1389 51 4 3 TAP controller state machine 1389 51 4 4 JTAGC block instructions 1391 51 4 5...

Page 47: ...ntify different numbering systems This suffix Identifies a b Binary number For example the binary equivalent of the number 5 is written 101b In some cases binary numbers are shown with the prefix 0b d...

Page 48: ...ated by a colon represent either A subset of a register s named field For example REVNO 6 4 refers to bits 6 4 that are part of the COREREV field that occupies bits 6 0 of the REVNO register A continu...

Page 49: ...v7 architecture System System integration module Power management and mode controllers Multiple power modes available based on high speed run run wait stop and power down modes Low leakage wakeup unit...

Page 50: ...driven environments The Cortex M4 processor is based on the ARMv7 Architecture and Thumb 2 ISA and is upward compatible with the Cortex M3 Cortex M1 and Cortex M0 architectures Cortex M4 improvements...

Page 51: ...le LVD trip points Low leakage wakeup unit LLWU The LLWU module allows the device to wake from low leakage power modes LLS and VLLS through various internal peripheral and external pin sources Miscell...

Page 52: ...32 bit port sizes Configurations include multiplexed or non multiplexed address and data buses using 8 bit 16 bit 32 bit and 16 byte line sized transfers 2 2 4 Clocks The following clock modules are...

Page 53: ...nverters DAC 64 tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed 12 bit digital to analog converters DAC Low power general p...

Page 54: ...puts Up to 4 fault inputs for global fault control Configurable channel polarity Programmable interrupt on input capture reference compare overflowed counter or detected fault condition Quadrature dec...

Page 55: ...nicate with a variety of serial devices such as standard codecs digital signal processors DSPs microprocessors peripherals and audio codecs that implement the inter IC sound bus I2S and the Intel AC97...

Page 56: ...flash SRAM GPIO MK22FN512VFX12 120 MHz 88 QFN 512 KB 128 KB 60 MK22FN512CAP12R 120 MHz 80 WLCSP 512 KB 128 KB 52 MK22FN512CBP12R 120 MHz 80 WLCSP 512 KB 128 KB 52 MK22FN256CAP12R 120 MHz 80 WLCSP 256...

Page 57: ...specific module to module interactions not necessarily discussed in the individual module chapters and links for more information 3 2 Core modules 3 2 1 ARM Cortex M4 Core Configuration This section s...

Page 58: ...terrupts Nested Vectored Interrupt Controller NVIC NVIC Private Peripheral Bus PPB module Miscellaneous Control Module MCM MCM Private Peripheral Bus PPB module Single precision floating point unit FP...

Page 59: ...only available source of reference timing 3 2 1 3 Debug facilities This device has extensive debug capabilities including run control and tracing capabilities The standard ARM debug port that support...

Page 60: ...ports 16 priority levels for interrupts Therefore in the NVIC each source in the IPR registers contains 4 bits For example IPR0 is shown below 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 61: ...core Debug Monitor 0x0000_0034 13 0x0000_0038 14 ARM core Pendable request for system service PendableSrvReq 0x0000_003C 15 ARM core System tick timer SysTick Non Core Vectors 0x0000_0040 16 0 0 0 DM...

Page 62: ...an LLS recovery 0x0000_0098 38 22 0 5 WDOG or EWM Both watchdog modules share this interrupt 0x0000_009C 39 23 0 5 RNG Randon Number Generator 0x0000_00A0 40 24 0 6 I2C0 0x0000_00A4 41 25 0 6 I2C1 0x0...

Page 63: ...x0000_0114 69 53 1 13 USB OTG 0x0000_0118 70 54 1 13 0x0000_011C 71 55 1 13 0x0000_0120 72 56 1 14 DAC0 0x0000_0124 73 57 1 14 MCG 0x0000_0128 74 58 1 14 Low Power Timer 0x0000_012C 75 59 1 14 Port co...

Page 64: ...the NVIC s interrupt source number 2 Indicates the NVIC s ISER ICER ISPR ICPR and IABR register number used for this IRQ The equation to calculate this value is IRQ div 32 3 Indicates the NVIC s IPR r...

Page 65: ...tion Power management Power management Nested Vectored Interrupt Controller NVIC NVIC Wake up requests AWIC wake up sources 3 2 3 1 Wake up sources The device uses the following internal and external...

Page 66: ...sing an external bit clock or external master clock NMI Non maskable interrupt 3 2 4 FPU Configuration This section summarizes how the module has been configured in the chip For a comprehensive descri...

Page 67: ...exing Port control Signal multiplexing 3 3 System modules 3 3 1 SIM Configuration This section summarizes how the module has been configured in the chip For a comprehensive description of the module i...

Page 68: ...cated chapter Power Management Controller PMC Register access Peripheral bridge System Mode Controller SMC Resets Figure 3 7 System Mode Controller configuration Table 3 11 Reference links to related...

Page 69: ...gured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Low Leakage Wake up Unit LLWU Power Management Controller PMC Peripheral bridge 0 Register acc...

Page 70: ...LWU_P10 PTC6 LLWU_P10 pin LLWU_P11 PTC11 LLWU_P11 pin LLWU_P12 PTD0 LLWU_P12 pin LLWU_P13 PTD2 LLWU_P13 pin LLWU_P14 PTD4 LLWU_P14 pin LLWU_P15 PTD6 LLWU_P15 pin LLWU_M0IF LPTMR2 LLWU_M1IF CMP02 LLWU_...

Page 71: ...module Reference Full description Miscellaneous control module MCM MCM System memory map System memory map Clocking Clock distribution Power management Power management Transfers Private Peripheral Bu...

Page 72: ...ription Crossbar switch Crossbar Switch System memory map System memory map Clocking Clock Distribution Crossbar switch master ARM Cortex M4 core ARM Cortex M4 core Crossbar switch master DMA controll...

Page 73: ...3 6 2 Crossbar Light Switch Slave Assignments The slaves connected to the crossbar switch are assigned as follows Slave module Slave port number Flash memory controller 0 SRAM controllers 1 2 Peripher...

Page 74: ...ch Crossbar switch 3 3 7 1 Number of peripheral bridges This device contains one peripheral bridge 3 3 7 2 Memory maps The peripheral bridges are used to access the registers of most of the modules on...

Page 75: ...s a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 16 DMA channels Because of the mux there is not a hard correlation between any of the DMA request sources and a...

Page 76: ...l 1 22 FTM0 Channel 2 23 FTM0 Channel 3 24 FTM0 Channel 4 25 FTM0 Channel 5 26 FTM0 Channel 6 27 FTM0 Channel 7 28 FTM1 Channel 0 29 FTM1 Channel 1 30 FTM2 Channel 0 31 FTM2 Channel 1 32 FTM3 Channel...

Page 77: ...s enabled 62 DMA MUX Always enabled 63 DMA MUX Always enabled 1 Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel 3 3 8 2 DMA transfers via PIT trig...

Page 78: ...ory map System memory map Register access Peripheral bridge AIPS Lite 0 AIPS Lite 0 Clocking Clock distribution Power management Power management Transfers Crossbar switch Crossbar switch 3 3 10 Exter...

Page 79: ...agement Power management Signal multiplexing Port Control Module Signal multiplexing 3 3 10 1 EWM clocks This table shows the EWM clocks and the corresponding chip clocks Table 3 22 EWM clock connecti...

Page 80: ...chapter WDOG Mode Controller Peripheral bridge 0 Register access Figure 3 15 Watchdog configuration Table 3 24 Reference links to related information Topic Related module Reference Full description Wa...

Page 81: ...ding chip low power modes Table 3 26 WDOG low power modes Module mode Chip mode Wait Wait VLPW Stop Stop VLPS Power Down LLS VLLSx 3 4 Clock modules 3 4 1 MCG Configuration This section summarizes how...

Page 82: ...all referred to as the external reference clock and selection is determined by MCG_C7 OSCSEL bitfield The following table shows the chip specific clock assignments for this bitfield Table 3 28 MCG Os...

Page 83: ...stem memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing Full description MCG MCG 3 4 2 1 OSC modes of opera...

Page 84: ...red in the chip For a comprehensive description of the module itself see the module s dedicated chapter Register access Flash memory Transfers Flash memory controller Peripheral bridge 0 Figure 3 19 F...

Page 85: ..._FFFF MK22FN512CAP12R 512 0x0000_0000 0x0003_FFFF 0x0004_0000 0x0007_FFFF MK22FN512CBP12R 512 0x0000_0000 0x0003_FFFF 0x0004_0000 0x0007_FFFF MK22FN256CAP12R 256 0x0000_0000 0x0003_FFFF MK22FN512VFX12...

Page 86: ...emory operates in NVM normal mode 3 5 1 7 Erase All Flash Contents The flash of the MCU is protected from erasing all of the flash contents by the FTFA_FSEC MEEN bits If the bits are set to b10 mass e...

Page 87: ...ontroller Flash memory controller System memory map System memory map Clocking Clock Distribution Transfers Flash memory Flash memory Transfers Crossbar switch Crossbar Switch Register access Peripher...

Page 88: ...us block in the memory map anchored at address 0x2000_0000 As such SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address SRAM_U is anchored to 0x2000_0000 and occupies th...

Page 89: ..._U from 0x2000_0000 is powered In VLLS1 and VLLS0 no SRAM is retained however the 32 byte register file is available 3 5 4 System Register File Configuration This section summarizes how the module has...

Page 90: ...ster access Figure 3 24 VBAT Register file configuration Table 3 35 Reference links to related information Topic Related module Reference Full description VBAT register file VBAT register file System...

Page 91: ...troller resets the core logic and asserts the EzPort chip select signal to force the processor into EzPort mode 3 5 6 2 Flash Option Register FOPT The FOPT EZPORT_DIS bit can be used to prevent entry...

Page 92: ...management Signal multiplexing Port control Signal multiplexing NOTE FlexBus module is not available in 88 QFN package 3 5 7 1 FlexBus clocking The system provides a dedicated clock source to the Flex...

Page 93: ...the external pin while the FlexBus s CSPMCR register configures which FlexBus signals are available from the modules The control signals are grouped as illustrated Chapter 3 Chip Configuration K22F S...

Page 94: ...her modules External Pins FB_ALE Reserved FB_TSIZ0 Reserved FB_TSIZ1 Reserved Reserved Reserved FB_CS1 FB_TS FB_CS4 FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 FB_CS5 FB_TBST FB_CS2 FB_TA FB_CS3 Figu...

Page 95: ...orming any FlexBus access 3 5 7 4 FlexBus Security When security is enabled on the device FlexBus accesses may be restricted by configuring SIM_SOPT2 See System Integration Module SIM for details 3 5...

Page 96: ...module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Register access Peripheral bridge Random number generator RNG Figure 3 29...

Page 97: ...ence Full description 16 bit SAR ADC 16 bit SAR ADC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexi...

Page 98: ...ADC Channel SC1n ADCH Channel Input signal SC1n DIFF 1 Input signal SC1n DIFF 0 00000 DAD0 ADC0_DP0 and ADC0_DM0 ADC0_DP0 00001 DAD1 ADC0_DP1 and ADC0_DM1 ADC0_DP1 00010 DAD2 ADC0_DP2 and ADC0_DM2 ADC...

Page 99: ...andgap 1V reference voltage and not the VREF module 1 2 V reference voltage Prior to reading from this ADC channel ensure that you enable the bandgap buffer by setting the PMC_REGSC BGBE bit Refer to...

Page 100: ...sor S E 11011 AD27 Bandgap Diff 2 Bandgap S E 2 11100 AD28 Reserved Reserved 11101 AD29 VREFH Diff VREFH S E 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled 1 ADCx_CFG2 MUXSEL bit...

Page 101: ...owing configuration ADC0 AD8 AD9 ADC1 AD8 AD9 ADC0_SE8 ADC1_SE8 ADC0_SE9 ADC1_SE9 Figure 3 32 ADC hardware interleaved channels integration There are other pins on this device that have a similar inte...

Page 102: ...mechanism for triggering the ADC is the PDB The PDB itself can be triggered by other peripherals For example RTC Alarm Seconds signal is connected to the PDB The PDB input trigger can receive the RTC...

Page 103: ...this bitfield NOTE The ALTCLK option is only usable when OSCERCLK is in the MHz range A system with OSCERCLK in the kHz range has the optional clock source below minimum ADC clock operating frequency...

Page 104: ...module s dedicated chapter Signal multiplexing Module signals Register access CMP Peripheral bridge 0 Other peripherals Figure 3 33 CMP configuration Table 3 46 Reference links to related information...

Page 105: ...that must first enable the CMP and DAC prior to performing a CMP operation and capturing the output In this device control for this two staged sequencing is provided from the LPTMR The LPTMR provides...

Page 106: ...34 12 bit DAC configuration Table 3 48 Reference links to related information Topic Related module Reference Full description 12 bit DAC 12 bit DAC System memory map System memory map Clocking Clock d...

Page 107: ...or a comprehensive description of the module itself see the module s dedicated chapter Signal multiplexing Module signals Register access VREF Peripheral bus controller 0 Other peripherals Transfers F...

Page 108: ...3 8 1 PDB Configuration This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Signal multiplexi...

Page 109: ...PIT Ch 3 Output 1000 FTM0 initialization trigger and channel triggers as programmed in the FTM external trigger register EXTTRIG 1001 FTM1 initialization trigger and channel triggers as programmed in...

Page 110: ...igger pre trigger 0 acknowledgement input ADC1SC1B_COCO PDB channel 0 trigger pre trigger 1 acknowledgement input ADC0SC1A_COCO PDB channel 1 trigger pre trigger 0 acknowledgement input ADC0SC1B_COCO...

Page 111: ...t Connection Individual PDB Pulse Out signals are connected to each CMP block and used for sample window 3 8 1 7 Pulse Out Enable Register Implementation The following table shows the comparison of pu...

Page 112: ...ultiplexing Port control Signal multiplexing 3 8 2 1 Instantiation Information This device contains four FlexTimer modules The following table shows how these modules are configured Table 3 55 FTM Ins...

Page 113: ...en an FTM interrupt occurs read the FTM status registers FMS SC and STATUS to determine the exact interrupt source 3 8 2 5 FTM Fault Detection Inputs The following fault detection input options for th...

Page 114: ...ields in the same SOPTx register allows the user to synchronise all FTM timers via their respective TRIG0 input For the triggers with more than one additional option the SIM_SOPT4 register implements...

Page 115: ...the user utilizes FTM1_CH1 to be an input to FTM2_CH1 FTM1_CH0 can still be utilized for other functions X OR FTM2_CH1 FTM2_CH0 FTM1_CH1 Ch0 Ch1 FTM2 Ch0 Ch1 FTM1 SIM_SOPT4 FTM2CH1SRC Figure 3 39 FTM...

Page 116: ...FTM3 channel FTM0 FTM0_CH7 SIM_SOPT8 FTM0CH7SRC CH7 FTM0_CH0 SIM_SOPT8 FTM0CH0SRC CH0 FTM1_CH1 Figure 3 40 FTM Output Modulation 3 8 2 10 FTM output triggers for other modules FTM output triggers can...

Page 117: ...lobal Time Base Configuration 3 8 2 12 FTM BDM and debug halt mode In the FTM chapter references to the chip being in BDM are the same as the chip being in debug halt mode 3 8 3 PIT Configuration This...

Page 118: ...le 3 57 PIT channel assignments for periodic DMA triggering DMA Channel Number PIT Channel DMA Channel 0 PIT Channel 0 DMA Channel 1 PIT Channel 1 DMA Channel 2 PIT Channel 2 DMA Channel 3 PIT Channel...

Page 119: ...e of four sources determined by the LPTMR0_PSR PCS bitfield The following table shows the chip specific clock assignments for this bitfield NOTE The chosen clock must remain enabled if the LPTMR is to...

Page 120: ...is section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Signal multiplexing Register access Periphe...

Page 121: ...Dual role USB OTG capable On The Go controller that supports a full speed FS device or FS LS host The module complies with the USB 2 0 specification USB transceiver that includes internal 15 k pulldo...

Page 122: ...esistive voltage divider to keep the input voltage within the valid range if a GPIO pin is used for VBUS detection This device does not have a dedicated OTG ID detect pin For OTG ID pin detection if n...

Page 123: ...gulator is enabled to power the USB transceiver USB Regulator USB XCVR USB Controller USB0_DP USB0_DM VDD VOUT33 VREGIN TYPE A D D VBUS 2 AA Cells Cstab To PMC and Pads Chip Figure 3 47 USB regulator...

Page 124: ...be powered by the USB bus directly In this case VOUT33 is connected to VDD The USB regulator must be enabled by default to power the MCU then to power USB transceiver or external sensor USB Regulator...

Page 125: ...iguration Table 3 60 Reference links to related information Topic Related module Reference Full description USB controller USB controller System memory map System memory map Clocking Clock Distributio...

Page 126: ...commended that the USB regulator VREGIN and VOUT33 pins are tied to ground through 10k leaving these pin s floating is not recommended 3 9 2 SPI configuration This section summarizes how the module ha...

Page 127: ...uency of bus clock 2 3 9 2 3 Number of CTARs SPI CTAR registers define different transfer attribute configurations The SPI module supports up to eight CTAR registers This device supports two CTARs on...

Page 128: ...wer Modes In VLPR and VLPW modes the SPI is functional however the reduced system frequency also reduces the max frequency of operation for the SPI In VLPR and VLPW modes the max SPI_CLK frequency is...

Page 129: ...e OR d together to generate a single interrupt request per SPI module to the interrupt controller When an SPI interrupt occurs read the SPI_SR to determine the exact interrupt source 3 9 2 10 SPI cloc...

Page 130: ...TX FIFO with the new command word 3 9 3 I2C Configuration This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s...

Page 131: ...uration Table 3 68 Reference links to related information Topic Related module Reference Full description UART UART System memory map System memory map Clocking Clock Distribution Power management Pow...

Page 132: ...es are OR d together to generate a single interrupt request See below for the mapping of the individual interrupt sources to the interrupt request The status interrupt combines the following interrupt...

Page 133: ...e description of the module itself see the module s dedicated chapter Register access Peripheral bridge LPUART Signal multiplexing Module signals Figure 3 55 LPUART configuration Table 3 69 Reference...

Page 134: ...ule s dedicated chapter Signal multiplexing Register access Peripheral bridge Module signals 2 I S Figure 3 56 I2S configuration Table 3 70 Reference links to related information Topic Related module...

Page 135: ...ts the option for synchronous operation between the receiver and transmitter product 3 9 6 2 3 Bus Clock The bus clock is used by the control registers and to generate synchronous interrupts and DMA r...

Page 136: ...lock gating and I2S SAI initialization The clock to the I2S SAI module can be gated using a bit in the SIM To minimize power consumption these bits are cleared after any reset which disables the clock...

Page 137: ...ed after completing the current receive frame Entry into Stop mode is prevented not acknowledged while waiting for the transmitter and receiver to be disabled at the end of the current frame 3 9 6 3 2...

Page 138: ...bution Signal Multiplexing Port control Signal Multiplexing 3 10 1 1 Number of GPIO signals The number of GPIO signals available on the devices covered by this document are detailed in Orderable part...

Page 139: ...FlexBus space allow code to be executed with maximum performance There is an aliased region that maps a system address space to the Program flash section Flash region aliasing is specifically intende...

Page 140: ...0000 0x41FF_FFFF Reserved 0x4200_0000 0x42FF_FFFF Aliased to peripheral bridge AIPS Lite bitband Cortex M4 core only 0x4300_0000 0x43FD_FFFF Reserved 0x43FE_0000 0x43FF_FFFF Aliased to general purpose...

Page 141: ...on has the same effect as a read modify write operation on the targeted bit in the bit band region Bit 0 of the value written to the alias region determines what value is written to the target bit Wri...

Page 142: ...privileged secure aligns to the execute only and supervisor only access control The unsecure state of user non secure aligns to no access control states set and the mid level state where user secure a...

Page 143: ...ates a bus error response 4 3 1 Alternate Non Volatile IRC User Trim Description The following non volatile locations 4 bytes are reserved for custom IRC user trim supported by some development tools...

Page 144: ...ory operations In some situations a write to a peripheral must be completed fully before a subsequent action can occur Examples of such situations include Exiting an interrupt service routine ISR Chan...

Page 145: ...1 0x4000_C000 12 FlexBus 0x4000_D000 13 0x4000_E000 14 0x4000_F000 15 0x4001_0000 16 0x4001_1000 17 0x4001_2000 18 0x4001_3000 19 0x4001_4000 20 0x4001_5000 21 0x4001_6000 22 0x4001_7000 23 0x4001_800...

Page 146: ...ers PIT 0x4003_8000 56 FlexTimer FTM 0 0x4003_9000 57 FlexTimer FTM 1 0x4003_A000 58 FlexTimer FTM 2 0x4003_B000 59 Analog to digital converter ADC 0 0x4003_C000 60 0x4003_D000 61 Real time clock RTC...

Page 147: ...00 91 0x4005_C000 92 0x4005_D000 93 0x4005_E000 94 0x4005_F000 95 0x4006_0000 96 0x4006_1000 97 External watchdog 0x4006_2000 98 0x4006_3000 99 0x4006_4000 100 Multi purpose Clock Generator MCG 0x4006...

Page 148: ...s These resources are only accessible from the core other system masters do not have access to them Table 4 3 PPB memory map System 32 bit Address Range Resource 0xE000_0000 0xE000_0FFF Instrumentatio...

Page 149: ...ystem 32 bit Address Range Resource 0xE008_2000 0xE00F_EFFF Reserved 0xE00F_F000 0xE00F_FFFF ROM Table allows auto detection of debug components Chapter 4 Memory Map K22F Sub Family Reference Manual R...

Page 150: ...Private Peripheral Bus PPB memory map K22F Sub Family Reference Manual Rev 4 08 2016 150 NXP Semiconductors...

Page 151: ...r dissipation Various modules such as the USB OTG Controller have module specific clocks that can be generated from the IRC48MCLK or MCGPLLCLK or MCGFLLCLK clock In addition there are various other mo...

Page 152: ...c Clock options for some peripherals see note MCGFLLCLK IRC48MCLK MCGPLLCLK Note See subsequent sections for details on where these clocks are used PMC logic PMC LPO OSCCLK DIV CG CG CG CG CG Clock ga...

Page 153: ...he FLL MCGFLLCLK may clock some modules MCGPLLCLK MCG output of the PLL MCGFLLCLK or MCGPLLCLK may clock some modules IRC48MCLK Internal 48 MHz oscillator that can be used as a reference to the MCG an...

Page 154: ...MHz Up to 4 MHz MCGOUTCLK clock divider In all stop modes except for partial STOP2 mode and Compute Operation FlexBus clock FB_CLK Up to 30 MHz Up to 30 MHz Up to 4 MHz MCGOUTCLK clock divider In all...

Page 155: ..._SOPT1 OSC3 2KOUT to drive CLKOUT32K out in all low power modes CLKOUT32K 32 kHz 32 kHz 32 kHz ERCLK32K which is system OSC or LPO or RTC OSC depending on SIM_SOPT1 OSC3 2KSEL SIM_SOPT1 OSC3 2KOUT not...

Page 156: ...clock to bus clock ratio is limited to a max value of 8 3 The flash clock frequency must be programmed to 26 67 MHz or less less than or equal to the bus clock and an integer divide of the core clock...

Page 157: ...16 0xF divide by 16 Low power boot 1 0x0 divide by 1 0x0 divide by 1 0x1 divide by 2 0x1 divide by 2 Fast clock boot This gives the user flexibility for a lower frequency low power boot option The fla...

Page 158: ...ed after any reset which disables the clock to the corresponding module to conserve power Prior to initializing a module set the corresponding bit in SCGCx register to enable the clock Before turning...

Page 159: ...ry interfaces Flash Controller System clock Flash clock Flash memory Flash clock FlexBus System clock CLKOUT EzPort System clock EZP_CLK Security CRC Bus clock RNGA Bus clock Analog ADC Bus clock OSCE...

Page 160: ...OP2 and PSTOP1 modes of operation when entered from Run mode IRC48MCLK is forced disabled when the MCU transitions into VLPS LLSx and VLLSx low power modes NOTE IRC48MCLK is not forced disabled in Sto...

Page 161: ...rom the USB Host If the IRC48M clock is selected as the source of the PLL with MCG_C7 OSCSEL 10 then the clock frequency of the system clocks can shift as the USB device connects to the USB Host start...

Page 162: ...configured to run from the 1 kHz LPO clock source PORTx_DFCR CS PORTx digital input filter clock Bus clock LPO Figure 5 4 PORTx digital input filter clock generation 5 7 6 LPTMR clocking The prescale...

Page 163: ...C_CLKOUT is disabled in LLSx and VLLSx modes CLKOUT32K controlled by SIM_SOPT1 OSC32KOUT can also be driven on the pins where the RTC_CLKOUT signal is an option overriding the existing pin mux configu...

Page 164: ...5 6 RTC_CLKOUT and CLKOUT32K generation 5 7 8 USB FS OTG Controller clocking The USB FS OTG controller is a bus master attached to the crossbar switch As such it uses the system clock NOTE For the USB...

Page 165: ...Recover function enabled 5 7 9 UART clocking UART0 and UART1 modules operate from the core system clock which provides higher performance level for these modules All other UART modules operate from th...

Page 166: ...I peripheral can control the input clock selection pin direction and divide ratio of one audio master clock The I2S SAI transmitter and receiver support asynchronous bit clocks BCLKs that can be gener...

Page 167: ...S SAI BCLK_OUT BCD BCLK I2Sx_MDR FRACT DIVIDE I2Sx_MCR MICS Clock Generation DIV I2Sx_TCR2 RCR2 SIM_SOPT2 PLLFLLSEL 01 00 MCGFLLCLK Direction Control Pad Interface Logic Fractional Clock Divider 11 IR...

Page 168: ...Module clocks K22F Sub Family Reference Manual Rev 4 08 2016 168 NXP Semiconductors...

Page 169: ...k generator loss of lock LOL reset Stop mode acknowledge error SACKERR Software reset SW Lockup reset LOCKUP EzPort reset MDM DAP system reset Debug reset JTAG reset nTRST reset Each of the system res...

Page 170: ...to start processing from a known set of initial conditions System reset begins with the on chip regulator in full regulation and system clocking generation from an internal reference When the process...

Page 171: ...as continued filtering operation depending on the filtering mode selected When entering VLLS0 the RESET pin filter is disabled and bypassed The LPO filter has a fixed filter value of 3 Due to a synchr...

Page 172: ...leakage power modes The LLWU module is functional only in low leakage power modes In LLS mode only the RESET pin via the LLWU can generate a system reset In VLLSx modes all enabled inputs to the LLWU...

Page 173: ...knowledge the entry to stop mode if an error condition occurs The error can be caused by a failure of an external clock input to a module 6 2 2 8 Software reset SW The SYSRESETREQ bit in the NVIC appl...

Page 174: ...a system reset This is the primary method for resets via the JTAG SWD interface The system reset is held until this bit is cleared Set the core hold reset bit in the MDM AP control register to hold th...

Page 175: ...set sources except a VLLS Wakeup that does not occur via the RESET_b pin It resets parts of the SMC LLWU and other modules that remain powered during VLLS mode The Chip Reset not VLLS reset also cause...

Page 176: ...ort EXTEST HIGHZ and CLAMP instructions are active The reset source from the JTAG module is released when any other IR code is selected A JTAG reset causes the RCM s SRS1 JTAG bit to set 6 2 5 2 nTRST...

Page 177: ...6 3 2 Boot options The device s functional mode is controlled by the state of the EzPort chip select EZP_CS pin during reset The device can be in single chip default or serial flash programming mode...

Page 178: ...rrent during this time The duration of the recovery will be controlled by the clock divider selection determined by the LPBOOT setting 1 Fast Initialization The Flash has faster recoveries at the expe...

Page 179: ...em reset is held on internal logic the RESET pin is driven out low and the MCG is enabled in its default clocking mode 2 Required clocks are enabled Core Clock System Clock Flash Clock and any Bus Clo...

Page 180: ...the NMI input and the FOPT NMI_DIS field in the Flash Memory module If the NMI input is high or the NMI function is disabled in the NMI_DIS field the CPU begins execution at the PC location If the NMI...

Page 181: ...un mode When configured for PSTOP2 only the core and system clocks are gated and the bus clock remains active The bus masters and bus slaves clocked by the system clock enter Stop mode but the bus sla...

Page 182: ...nd internal power switches enabling the clock generators in the MCG enabling the system and bus clocks but not the core clock and negating the stop mode signal to the bus masters and bus slaves The on...

Page 183: ...n asynchronous DMA request 7 2 3 Compute Operation Compute Operation is an execution or compute only mode of operation that keeps the CPU enabled with full access to the SRAM and Flash read port but p...

Page 184: ...CK status bit indicates when entry has completed When exiting Compute Operation in Run mode the CPOACK status bit negates immediately When exiting Compute Operation in VLP Run mode the exit is delayed...

Page 185: ...set the corresponding bit in the SCGCx register to enable the clock Before turning off the clock make sure to disable the module For more details refer to the clock distribution and SIM chapters 7 3...

Page 186: ...ency Sleep Interrupt VLPS Very Low Power Stop via WFI Places chip in static state with LVD operation off Lowest power mode with ADC and pin interrupts functional Peripheral clocks are stopped but LPTi...

Page 187: ...ister file remain powered for customer critical data The POR detect circuit can be optionally powered off Sleep Deep Wakeup Reset2 BAT backup battery only The chip is powered down except for the VBAT...

Page 188: ...f the oscillator was configured to continue running during VLLSx modes it must be re configured before the ACKISO bit is cleared The oscillator configuration within the MCG is cleared after VLLSx reco...

Page 189: ...argeted low power state All low power entry sequences are initiated by the core executing an WFI instruction The ARM core s outputs SLEEPDEEP and SLEEPING trigger entry to the various low power modes...

Page 190: ...ntrol register As part of this transition system clocking is re established and is equivalent to normal run VLPR mode clocking configuration 7 7 Flash Program Restrictions The flash memory on this dev...

Page 191: ...FF FF FF FF static OFF EWM FF static in CPO static static FF in PSTOP2 static static OFF Clocks 1kHz LPO ON ON ON ON ON ON in VLLS1 2 3 OFF in VLLS0 System oscillator OSC OSCERCLK max of 16 MHz cryst...

Page 192: ...n resume static wakeup on resume static OFF USB Voltage Regulator optional optional optional optional optional optional UART0 UART1 250 kbit s static wakeup on edge in CPO 250 kbit s static wakeup on...

Page 193: ...MP9 FF HS or LS compare in CPO FF HS or LS compare FF in PSTOP2 HS or LS compare LS compare LS compare in VLLS1 2 3 OFF in VLLS0 6 bit DAC FF static in CPO FF static FF in PSTOP2 static static static...

Page 194: ...LLS0 Pulse counting is available in all modes 8 RTC_CLKOUT is not available CLKOUT32K can be configured as an alternate path of supplying 32 kHz 9 CMP in stop or VLPS supports high speed or low speed...

Page 195: ...the security byte of the flash configuration field NOTE The security features apply only to external accesses via debug and EzPort CPU accesses to the flash are not affected by the status of FSEC In...

Page 196: ...limited to the mass erase Erase All Blocks and verify all 1s Read 1s All Blocks commands Read accesses to internal memories via the EzPort are blocked when security is enabled The mass erase can be us...

Page 197: ...When mass erase is disabled mass erase via the debugger is blocked Chapter 8 Security K22F Sub Family Reference Manual Rev 4 08 2016 NXP Semiconductors 197...

Page 198: ...Security Interactions with other Modules K22F Sub Family Reference Manual Rev 4 08 2016 198 NXP Semiconductors...

Page 199: ...ut and other available resources Four debug interfaces are supported IEEE 1149 1 JTAG IEEE 1149 7 JTAG cJTAG Serial Wire Debug SWD ARM Real Time Trace Interface 1 pin asynchronous mode only The basic...

Page 200: ...ule and SOC system memory maps MDM AP Provides centralized control and status registers for an external debugger to control the device ROM Table Identifies which debug IP is available Core Debug Singl...

Page 201: ...the processor core on a match so providing hardware breakpoint capability TPIU Trace Port Inteface Unit Asynchronous Mode 1 pin TRACE_SWO available on JTAG_TDO 9 1 1 References For more information o...

Page 202: ...Port The debug port comes out of reset in standard JTAG mode and is switched into either cJTAG or SWD mode by the following sequences Once the mode has been changed unused debug pins can be reassigne...

Page 203: ...Wire Data Pull up JTAG_TCLK SWD_CLK I JTAG Test Clock I cJTAG Clock I Serial Wire Clock Pull down JTAG_TDI I JTAG Test Data Input Pull up JTAG_TDO TRACE_SWO O JTAG Test Data Output O Trace output ove...

Page 204: ...JTAG DP documentation for more information on these instructions Reserved 3 All other opcodes Decoded to select bypass register 3 The manufacturer reserves the right to change the decoding of reserve...

Page 205: ...the MDM AP SELECT 7 4 0x0 selects the bank with Status and Ctrl A 3 2 2 b00 selects the Status Register A 3 2 2 b01 selects the Control Register SELECT 7 4 0xF selects the bank with IDR A 3 2 2 b11 se...

Page 206: ...GREQ N Set to configure the system to be held in reset after the next recovery from a VLLSx mode This bit holds the in reset when VLLSx modes are exited to allow the debugger time to re initialize deb...

Page 207: ...erase request due to seting of Flash Mass Erase in Progress bit is not acknowledged 1 Flash Ready Indicate Flash has been initialized and debugger can be configured even if system is continuing to be...

Page 208: ...bit indicates an exit from VLLSx mode has occurred The debugger will lose communication while the system is in VLLSx including access to this register Once communication is reestablished this bit ind...

Page 209: ...core AHB AP transactions are little endian For a short period at the start of a system reset event the system security status is being determined and debugger access to all AHB AP transactions is bloc...

Page 210: ...bridge between the on chip trace data from the Instrumentation Trace Macrocell ITM to a data stream encapsulating IDs where required that is then captured by a Trace Port Analyzer TPA The TPIU is spec...

Page 211: ...s In these modes in which FCLK is left active the debug modules have access to core registers but not to system memory resources accessed via the crossbar With debug enabled transitions from Run direc...

Page 212: ...F FF OFF static OFF 9 13 Debug Security When security is enabled FSEC SEC 10 the debug port capabilities are limited in order to prevent exploitation of secure data In the secure state the debugger st...

Page 213: ...c pin 10 2 Signal Multiplexing Integration This section summarizes how the module is integrated into the device For a comprehensive description of the module itself see the module s dedicated chapter...

Page 214: ...trol Yes Yes Yes Yes Yes Pull enable at reset PTA0 PTA1 PTA2 PTA3 PTA4 Enabled Others Disabled Disabled Disabled Disabled Disabled Slew rate enable control Yes Yes Yes Yes Yes Slew rate enable at rese...

Page 215: ...ake sure to disable the module For more details refer to the clock distribution chapter 10 2 3 Signal multiplexing constraints 1 A given peripheral function must be assigned to a maximum of one packag...

Page 216: ...DISABLE D PTE6 SPI1_ PCS3 LPUART0 _CTS_b I2S0_ MCLK FTM3_ CH1 USB_ SOF_OUT C5 3 B9 8 8 E6 VDD VDD VDD C4 4 B10 9 9 G7 VSS VSS VSS D8 9 L6 VSS VSS VSS E1 5 C10 10 10 F1 USB0_DP USB0_DP USB0_DP D1 6 D1...

Page 217: ...T CMP1_ IN5 CMP0_ IN5 ADC1_ SE18 VREF_ OUT CMP1_ IN5 CMP0_ IN5 ADC1_ SE18 VREF_ OUT CMP1_ IN5 CMP0_ IN5 ADC1_ SE18 H2 18 F8 23 27 K5 DAC0_ OUT CMP1_ IN3 ADC0_ SE23 DAC0_ OUT CMP1_ IN3 ADC0_ SE23 DAC0_...

Page 218: ...TM0_ CH2 I2S0_TX_ BCLK JTAG_ TRST_b 33 40 E5 VDD VDD VDD 34 41 G3 VSS VSS VSS J9 PTA10 DISABLE D PTA10 FTM2_ CH0 FTM2_ QD_PHA J4 PTA11 DISABLE D PTA11 FTM2_ CH1 FTM2_ QD_PHB H6 28 H6 35 42 K8 PTA12 DI...

Page 219: ...T0 _CTS_b FB_AD20 E2 54 58 D10 PTB10 ADC1_ SE14 ADC1_ SE14 PTB10 SPI1_ PCS0 LPUART0 _RX FB_AD19 FTM0_ FLT1 E1 55 59 C10 PTB11 ADC1_ SE15 ADC1_ SE15 PTB11 SPI1_SCK LPUART0 _TX FB_AD18 FTM0_ FLT2 E4 60...

Page 220: ...8 78 C7 PTC6 LLWU_ P10 CMP0_IN0 CMP0_IN0 PTC6 LLWU_ P10 SPI0_ SOUT PDB0_ EXTRG I2S0_RX_ BCLK FB_AD9 I2S0_ MCLK B6 52 B3 69 79 B7 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_ SOF_OUT I2S0_RX_ FS FB_AD8 A6...

Page 221: ...D PTD3 SPI0_SIN UART2_ TX FTM3_ CH3 FB_AD3 LPUART0 _TX I2C0_SDA A3 61 B7 83 97 A3 PTD4 LLWU_ P14 DISABLE D PTD4 LLWU_ P14 SPI0_ PCS1 UART0_ RTS_b FTM0_ CH4 FB_AD2 EWM_IN SPI1_ PCS0 C1 62 A7 84 98 A2 P...

Page 222: ...ISABLE D PTD15 FB_A23 A11 NC NC NC K3 NC NC NC H4 NC NC NC B11 NC NC NC C11 NC NC NC 10 3 2 K22 Pinouts The following figure shows the pinout diagram for the devices supported by this document Many si...

Page 223: ...17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 PTD7 PTD6 LLWU_P15 PTD5 PTD4 LLWU_P14 PTD3 PTD2 LLWU_P13 PTD1 PTD0 LLWU_P12 PTC11 LLWU_P11 PTC10 PTC9 PTC8 PTC7 PTC6 LLWU_P10 PTC5 LLWU_P9 PTC4 L...

Page 224: ...D3 VDD VDD PTA1 PTA4 LLWU_P3 PTA12 7 PTD5 PTD4 LLWU_P14 PTD6 LLWU_P15 PTD7 PTE0 CLKOUT32K PTA0 RTC_ VBAT 8 PTE1 LLWU_P0 PTE4 LLWU_P2 PTE5 VSS DAC0_OUT XTAL32 EXTAL32 9 PTE2 LLWU_P1 VDD VOUT33 VREGIN A...

Page 225: ...TAL32 4 PTD1 PTC10 VSS PTA1 VDD VDDA VREFH 4 EXTAL32 5 PTC11 LLWU_P11 PTC9 VDD PTA3 PTA2 PTA5 PTA4 LLWU_P3 5 VBAT 6 PTC8 PTC7 PTC1 LLWU_P6 PTB18 PTB16 PTB1 PTA13 LLWU_P4 6 PTA12 7 PTC6 LLWU_P10 PTC2 P...

Page 226: ...45 RESET_b 46 PTB0 LLWU_P5 47 PTB1 48 PTB2 49 PTB3 50 PTB6 51 PTB7 52 PTB8 53 PTB9 54 PTB10 55 PTB11 56 PTB16 57 PTB17 58 PTB18 59 PTB19 60 PTC0 61 PTC1 LLWU_P6 62 PTC2 63 PTC3 LLWU_P7 64 VSS 65 VDD...

Page 227: ..._DM3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 PTD6 LLWU_P15 PTC7 PTC6 LLWU_P10 PTC5 LLWU_P9 PTC4 LLWU_P8 50 49 48 47 46 45 44 43 42 41 PTA18 VSS VDD PTA17 PTA16 PTA15 PTA14 PTA13 LL...

Page 228: ...C9 VDD VSSA VREFL PTE26 CLKOUT32K PTA0 VBAT 6 VSS 7 PTC8 PTC7 PTC6 LLWU_P10 PTC5 LLWU_P9 VDD VSS VSS PTE4 LLWU_P2 PTA2 PTA5 7 RTC_ WAKEUP_B 8 PTC4 LLWU_P8 PTC3 LLWU_P7 PTC2 PTC1 LLWU_P6 PTB23 PTB22 PT...

Page 229: ...TAG_TCLK SWD_CLK Serial Wire Clock I Table 10 5 TPIU Signal Descriptions Chip signal name Module signal name Description I O TRACE_SWO JTAG_TDO TRACE_SWO Trace output data from the ARM CoreSight debug...

Page 230: ...Serial Data Out Output Table 10 10 FlexBus Signal Descriptions Chip signal name Module signal name Description I O CLKOUT FB_CLK FlexBus Clock Output O FB_AD 31 0 1 FB_AD31 FB_AD0 This is the address...

Page 231: ...E FB_TS Transfer Start Indicates that the chip has begun a bus transaction and that the address and attributes are valid An inverted FB_TS is available as an address latch enable FB_ALE which indicate...

Page 232: ...cified number of wait states or the external memory or peripheral may assert external FB_TA before the wait state countdown to terminate the transfer early The chip deasserts FB_CS one cycle after the...

Page 233: ...gnal name Description I O ADC1_DP3 ADC1_DP 1 0 DADP3 DADP0 Differential Analog Channel Inputs I ADC1_DM3 ADC1_DM 1 0 DADM3 DADM0 Differential Analog Channel Inputs I ADC1_SEn ADn Single Ended Analog C...

Page 234: ...e selected to drive the FTM counter I FTM0_CH 7 0 CHn FTM channel n where n can be 7 0 I O FTM0_FLT 3 0 FAULTj Fault input j where j can be 3 0 I Table 10 19 FTM 1 Signal Descriptions Chip signal name...

Page 235: ...the FTM counter I FTM3_CH 7 0 CHn FTM channel n where n can be 7 0 I O FTM3_FLT0 FAULTj Fault input j where j can be 3 0 I Table 10 22 PDB 0 Signal Descriptions Chip signal name Module signal name Des...

Page 236: ...le 10 27 SPI 0 Signal Descriptions Chip signal name Module signal name Description I O SPI0_PCS0 PCS0 SS Peripheral Chip Select 0 O I O SPI0_PCS 3 1 PCS 1 3 Peripheral Chip Selects 1 3 O SPI0_PCS4 PCS...

Page 237: ...TxD Transmit Data O UART0_RX RxD Receive Data I Table 10 32 UART 0 Signal Descriptions Chip signal name Module signal name Description I O UART0_CTS CTS Clear to send I UART0_RTS RTS Request to send O...

Page 238: ...t clock is an input when externally generated and an output when internally generated I O I2S0_TX_FS SAI_TX_SYNC Transmit Frame Sync The frame sync is an input sampled synchronously by the bit clock w...

Page 239: ...s of its pin muxing state There is one instance of the PORT module for each port Not all pins within each port are implemented on a specific device 11 2 1 Features The PORT module has the following fe...

Page 240: ...n drain output Individual mux control field supporting analog or pin disabled GPIO and up to six chip specific digital functions Pad configuration fields are functional in all digital pin muxing modes...

Page 241: ...nterface detailed signal description Signal I O Description PORTx 31 0 I O External interrupt State meaning Asserted pin is logic 1 Negated pin is logic 0 Timing Assertion may occur at any time and ca...

Page 242: ...n 11 5 1 248 4004_9044 Pin Control Register n PORTA_PCR17 32 R W See section 11 5 1 248 4004_9048 Pin Control Register n PORTA_PCR18 32 R W See section 11 5 1 248 4004_904C Pin Control Register n PORT...

Page 243: ...04_A038 Pin Control Register n PORTB_PCR14 32 R W See section 11 5 1 248 4004_A03C Pin Control Register n PORTB_PCR15 32 R W See section 11 5 1 248 4004_A040 Pin Control Register n PORTB_PCR16 32 R W...

Page 244: ...R W See section 11 5 1 248 4004_B030 Pin Control Register n PORTC_PCR12 32 R W See section 11 5 1 248 4004_B034 Pin Control Register n PORTC_PCR13 32 R W See section 11 5 1 248 4004_B038 Pin Control R...

Page 245: ..._C024 Pin Control Register n PORTD_PCR9 32 R W See section 11 5 1 248 4004_C028 Pin Control Register n PORTD_PCR10 32 R W See section 11 5 1 248 4004_C02C Pin Control Register n PORTD_PCR11 32 R W See...

Page 246: ...248 4004_D018 Pin Control Register n PORTE_PCR6 32 R W See section 11 5 1 248 4004_D01C Pin Control Register n PORTE_PCR7 32 R W See section 11 5 1 248 4004_D020 Pin Control Register n PORTE_PCR8 32 R...

Page 247: ...R W See section 11 5 1 248 4004_D07C Pin Control Register n PORTE_PCR31 32 R W See section 11 5 1 248 4004_D080 Global Pin Control Low Register PORTE_GPCLR 32 W always reads 0 0000_0000h 11 5 2 251 40...

Page 248: ...nal Descriptions chapter for reset values per port DSE field Varies by port See the Signal Multiplexing and Signal Descriptions chapter for reset values per port PFE field Varies by port See Signal Mu...

Page 249: ...d 0110 Reserved 0111 Reserved 1000 ISF flag and Interrupt when logic 0 1001 ISF flag and Interrupt on rising edge 1010 ISF flag and Interrupt on falling edge 1011 ISF flag and Interrupt on either edge...

Page 250: ...es 0 Passive input filter is disabled on the corresponding pin 1 Passive input filter is enabled on the corresponding pin if the pin is configured as a digital input Refer to the device data sheet for...

Page 251: ...sters bits 15 0 that are selected by GPWE 11 5 3 Global Pin Control High Register PORTx_GPCHR Only 32 bit writes are supported to this register Address Base address 84h offset Bit 31 30 29 28 27 26 25...

Page 252: ...ding flag will be cleared automatically at the completion of the requested DMA transfer Otherwise the flag remains set until a logic 1 is written to the flag If the pin is configured for a level sensi...

Page 253: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_DFCR field descript...

Page 254: ...ctional description 11 6 1 Pin control Each port pin has a corresponding Pin Control register PORT_PCRn associated with it The upper half of the Pin Control register configures the pin s capability to...

Page 255: ...er is disabled Enabling the internal pull resistor or implementing an external pull resistor will ensure a pin does not float when its input buffer is enabled note that the internal pull resistor is a...

Page 256: ...riting a logic 1 to the ISF flag in either the PORT_ISFR or PORT_PCRn registers The PORT module generates a single DMA request that asserts when the interrupt status flag is set for any enabled DMA re...

Page 257: ...er a digital filter is disabled After a digital filter is enabled the input is synchronized to the filter clock either the bus clock or the LPO clock If the synchronized input and the output of the di...

Page 258: ...Functional description K22F Sub Family Reference Manual Rev 4 08 2016 258 NXP Semiconductors...

Page 259: ...registers 12 1 1 Features Features of the SIM include System clocking configuration System clock divide values Architectural clock gating control USB clock selection and divide values Flash and syste...

Page 260: ...tem Device Identification Register SIM_SDID 32 R See section 12 2 8 275 4004_8034 System Clock Gating Control Register 4 SIM_SCGC4 32 R W F010_0030h 12 2 9 277 4004_8038 System Clock Gating Control Re...

Page 261: ...iption 31 USBREGEN USB voltage regulator enable Controls whether the USB voltage regulator is enabled 0 USB voltage regulator is disabled 1 USB voltage regulator is enabled 30 USBSSTBY USB voltage reg...

Page 262: ...RTC 32 768kHz oscillator 11 LPO 1 kHz 17 16 OSC32KOUT 32K Oscillator Clock Output Outputs the ERCLK32K on the selected pin in all modes of operation including LLS VLLS and System Reset overriding the...

Page 263: ...allows the SOPT1 USBSSTBY bit to be written This register bit clears after a write to USBSSTBY 0 SOPT1 USBSSTBY cannot be written 1 SOPT1 USBSSTBY can be written 25 UVSWE USB voltage regulator VLP st...

Page 264: ...004_7000h base 1004h offset 4004_8004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 LPUARTSRC 0 0 0 USBSRC PLLFLLSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6...

Page 265: ...served This read only field is reserved and always has the value 0 12 TRACECLKSEL Debug trace clock select Selects the core system clock or MCG output clock MCGOUTCLK as the trace clock source 0 MCGOU...

Page 266: ..._7000h base 100Ch offset 4004_800Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R FTM3TRG1SR C FTM3TRG0SR C FTM0TRG1SR C FTM0TRG0SR C FTM3CLKSEL FTM2CLKSEL FTM1CLKSEL FTM0CLKSEL 0 FTM2CH1SRC F...

Page 267: ...pin 1 FTM3 external clock driven by FTM_CLK1 pin 26 FTM2CLKSEL FlexTimer 2 External Clock Pin Select Selects the external pin used to drive the clock to the FTM2 module NOTE The selected pin must also...

Page 268: ...SB start of frame pulse 17 13 Reserved This field is reserved This read only field is reserved and always has the value 0 12 FTM3FLT0 FTM3 Fault 0 Select Selects the source of FTM3 fault 0 NOTE The pi...

Page 269: ...0 FTM0FLT0 FTM0 Fault 0 Select Selects the source of FTM0 fault 0 NOTE The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in...

Page 270: ...4 UART1TXSRC UART 1 transmit data source select Selects the source for the UART 1 transmit data 00 UART1_TX pin 01 UART1_TX pin modulated with FTM1 channel 0 output 10 UART1_TX pin modulated with FTM2...

Page 271: ...r ADC1 1 Alternate trigger selected for ADC1 as defined by ADC1TRGSEL 14 13 Reserved This field is reserved This read only field is reserved and always has the value 0 12 ADC1PRETRGSEL ADC1 pre trigge...

Page 272: ...igger select Selects the ADC0 pre trigger source when alternative triggers are enabled through ADC0ALTTRGEN 0 Pre trigger A 1 Pre trigger B ADC0TRGSEL ADC0 trigger select Selects the ADC0 trigger sour...

Page 273: ...put of FTM3 channel 6 output 1 FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 channel 1 output 29 FTM3OCH5SRC FTM3 channel 5 output source 0 FTM3_CH5 pin is output of FTM3 channel 5...

Page 274: ...output modulated by FTM1 channel 1 output 19 FTM0OCH3SRC FTM0 channel 3 output source 0 FTM0_CH3 pin is output of FTM0 channel 3 output 1 FTM0_CH3 pin is output of FTM0 channel 3 output modulated by F...

Page 275: ...ress 4004_7000h base 1024h offset 4004_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FAMILYID SUBFAMID SERIESID 0 REVID DIEID FAMID PINID W Reset x...

Page 276: ...e set identication number for the device 6 4 FAMID Kinetis family identification This field is maintained for compatibility only but has been superceded by the SERIESID FAMILYID and SUBFAMID fields in...

Page 277: ...descriptions Field Description 31 28 Reserved This field is reserved This read only field is reserved and always has the value 1 27 21 Reserved This field is reserved This read only field is reserved...

Page 278: ...This field is reserved This read only field is reserved and always has the value 0 7 I2C1 I2C1 Clock Gate Control This bit controls the clock gate to the I 2 C1 module 0 Clock disabled 1 Clock enable...

Page 279: ...This field is reserved This read only field is reserved and always has the value 0 18 Reserved This field is reserved This read only field is reserved and always has the value 1 17 14 Reserved This fi...

Page 280: ...only field is reserved and always has the value 0 5 Reserved This field is reserved This read only field is reserved and always has the value 0 4 Reserved This field is reserved This read only field...

Page 281: ...d 1 Clock enabled 30 Reserved This field is reserved This read only field is reserved and always has the value 1 29 RTC RTC Access Control This bit controls software access and interrupts to the RTC m...

Page 282: ...ys has the value 0 20 19 Reserved This field is reserved This read only field is reserved and always has the value 0 18 CRC CRC Clock Gate Control This bit controls the clock gate to the CRC module 0...

Page 283: ...ock enabled 6 FTM3 FTM3 Clock Gate Control This bit controls the clock gate to the FTM3 module 0 Clock disabled 1 Clock enabled 5 Reserved This field is reserved This read only field is reserved and a...

Page 284: ...ption 31 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 R...

Page 285: ...0 0 SIM_CLKDIV1 field descriptions Field Description 31 28 OUTDIV1 Clock 1 output divider value This field sets the divide value for the core system clock from MCGOUTCLK At the end of reset it is load...

Page 286: ...of the system clock frequency 0000 Divide by 1 0001 Divide by 2 0010 Divide by 3 0011 Divide by 4 0100 Divide by 5 0101 Divide by 6 0110 Divide by 7 0111 Divide by 8 1000 Divide by 9 1001 Divide by 10...

Page 287: ...eset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_CLKDIV2 field descriptions Field Description 31 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 1 USBDIV USB cl...

Page 288: ...ved This read only field is reserved and always has the value 0 27 24 PFSIZE Program flash size This field specifies the amount of program flash memory available on the device Undefined values are res...

Page 289: ...lash will be automatically enabled again at the end of Wait mode so interrupt vectors do not need to be relocated out of Flash memory The wakeup time from Wait mode is extended when this bit is set 0...

Page 290: ...1 is 0x4_0000 0x4_0000 This would be the MAXADDR1 value for a device with 512 KB program flash memory across two flash blocks and no FlexNVM Reserved This field is reserved This read only field is re...

Page 291: ...entification Unique identification for the device 12 2 20 Unique Identification Register Low SIM_UIDL Address 4004_7000h base 1060h offset 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 292: ...Functional description K22F Sub Family Reference Manual Rev 4 08 2016 292 NXP Semiconductors...

Page 293: ...n on chip ROM are shipped with the pre programmed Kinetis Flashloader in the on chip flash memory for one time in system factory programming The Kinetis Flashloader s main task is to load a customer f...

Page 294: ...le it is running Provides command to read properties of the device such as flash and RAM size Table 13 2 Commands supported by the Kinetis Flashloader Command Description When flash security is enable...

Page 295: ...ble 13 3 2 Start up Process As the Kinetis Flashloader begins executing flashloader operations begin 1 The flashloader s temporary working area in RAM is initialized 2 All supported peripherals are in...

Page 296: ...n Start byte 0x5A received on I2Cn Was Start byte 0x5A received on SPIn Was Figure 13 1 Kinetis Flashloader Start up Flowchart 13 3 3 Clock Configuration The core runs on the default reset clock 20 9...

Page 297: ...host to flashloader then the data phase is part of the original command If the data phase is outgoing from flashloader to host then the data phase is part of the response command NOTE In all protocol...

Page 298: ...to host Incoming data packets from host Generic response command packet to host Command Host Target ACK Process command Initial Response ACK Data packet ACK Process data Final data packet ACK Final R...

Page 299: ...rtDataPhase The host may abort the data phase early by sending a zero length data packet The final Generic Response packet sent after the data phase includes the status for the entire operation 13 3 4...

Page 300: ...e above the data phase is really considered part of the response command The host may not send any further packets while it the host is waiting for the response to a command If the ReadMemory Response...

Page 301: ...t is packetized NOTE The term target refers to the Kinetis Flashloader device There are 6 types of packets used in the device Ping packet Ping Response packet Framing packet Command packet Data packet...

Page 302: ...es the incoming Ping packet to determine the baud rate before replying with the Ping Response packet Once the Ping Response packet is received by the host the connection is established and the host st...

Page 303: ...RC16 algorithm after this table 5 crc16_high 6 n Command or Data packet payload A special framing packet that contains only a start byte and a packet type is used for synchronization between the host...

Page 304: ...yte 2 byte 3 Table 13 9 Command Header Format Byte Command Header Field 0 Command or Response tag The command header is 4 bytes long with these fields 1 Flags 2 Reserved Should be 0x00 3 ParameterCoun...

Page 305: ...es to FlashReadOnce command only 0xB0 FlashReadResourceResponse used for sending responses to FlashReadResource command only Flags Each command packet contains a Flag byte Only bit 0 of the flag byte...

Page 306: ...processed a command the flashloader will send a generic response with status and command tag information to the host The generic response is the last packet in the command protocol sequence The gener...

Page 307: ...command response tag set to a ReadMemoryResponse tag value 0xA3 the flags field set to kCommandFlag_HasDataPhase 1 The parameter count set to 2 for the status code and the data byte count parameters...

Page 308: ...et as explained in previous sections For a list of commands supported by the Flashloader see Table 13 2 Commands supported For a list of status codes returned by the Kinetis Flashloader see Table 13 4...

Page 309: ...acket with a status code either set to the return value of the function called or set to kStatus_InvalidArgument 105 13 3 6 2 GetProperty command The GetProperty command is used to query the flashload...

Page 310: ...00 07 7a a7 00 00 02 00 00 00 00 00 00 01 4b ACK 0x5a a1 ACK 0x5a a1 Generic Response Figure 13 7 Protocol Sequence for GetProperty Command Table 13 19 GetProperty Command Packet Format Example GetPro...

Page 311: ...flags 0x00 reserved 0x00 parameterCount 0x02 status 0x00000000 propertyValue 0x0000014b CurrentVersion 13 3 6 3 SetProperty command The SetProperty command is used to change or alter the values of the...

Page 312: ...ngPacketType_Command length 0x0C 0x00 crc16 0x67 0x8D Command packet commandTag 0x0C SetProperty with property tag 10 flags 0x00 reserved 0x00 parameterCount 0x02 propertyTag 0x0000000A VerifyWrites p...

Page 313: ...g field of the command packet The FlashEraseAll command requires no parameters Process command Host Target FlashEraseAll 0x5a a4 04 00c4 2e 01 00 00 00 0x5a a4 0c 00 53 63 a0 00 04 02 00 00 00 00 01 0...

Page 314: ...nd will fail and return kStatus_FlashAlignmentError 0x101 If the region specified does not fit in the flash memory space the FlashEraseRegion command will fail and return kStatus_FlashAddressError 0x1...

Page 315: ...le 13 27 FlashEraseRegion Response Status Codes Status Code kStatus_Success 0x0 kStatus_MemoryRangeInvalid 0x10200 kStatus_FlashAlignmentError 0x101 kStatus_FlashAddressError 0x102 kStatus_FlashAccess...

Page 316: ...t be taken when writing to flash First any flash sector written to must have been previously erased with a FlashEraseAll or FlashEraseRegion command Writing to flash requires the start address to be 3...

Page 317: ...7 FlashProgramOnce command The FlashProgramOnce command writes data that is provided in a command packet to a specified range of bytes in the program once field Special care must be taken when writin...

Page 318: ...and length 0x10 0x00 crc16 0x7E4 0x89 Command packet commandTag 0x0E FlashProgramOnce flags 0 reserved 0 parameterCount 3 index 0x0000_0000 byteCount 0x0000_0004 data 0x1234_5678 Response upon success...

Page 319: ...Figure 13 13 Protocol Sequence for FlashReadOnce Command Table 13 33 FlashReadOnce Command Packet Format Example FlashReadOnce Parameter Value Framing packet start byte 0x5A packetType 0xA4 length 0x0...

Page 320: ...on successful execution of the command or will return with a status code set to an appropriate error status code and a byte count set to 0 13 3 6 9 FlashReadResource command The FlashReadResource comm...

Page 321: ...00 06 5a a4 0c 00 75 a3 a0 00 00 02 00 00 00 00 10 00 00 00 Figure 13 14 Protocol Sequence for FlashReadResource Command Table 13 36 FlashReadResource Command Packet Format Example FlashReadResource...

Page 322: ...e data phase to a specified range of bytes in memory flash or RAM However if flash protection is enabled then writes to protected sectors will fail Special care must be taken when writing to flash Fir...

Page 323: ...02 00 00 00 00 04 00 00 00 ACK 0x5a a1 0x5a a4 0c 00 a0 0e 04 01 00 02 00 04 00 20 40 00 00 00 Figure 13 15 Protocol Sequence for WriteMemory Command Table 13 39 WriteMemory Command Packet Format Exa...

Page 324: ...ssful execution of the command or to an appropriate error status code 13 3 6 11 Read memory command The ReadMemory command returns the contents of memory at the given address for a specified number of...

Page 325: ...bytes data 0x5a a5 length 16 CRC 16 32 bytes data ACK 0x5a a1 ACK 0x5a a1 ACK 0x5a a1 ACK 0x5a a1 ACK 0x5a a1 0x5a a4 0c 00 0e 23 a0 00 00 02 00 00 00 00 03 00 00 00 Figure 13 16 Command sequence for...

Page 326: ...nd a Stack pointer to the provided stack pointer address Prior to the jump the system is returned to the reset state The Jump address function argument pointer and stack pointer are the parameters req...

Page 327: ...4 kFramingPacketType_Command length 0x04 0x00 crc16 0x6F 0x46 Command packet commandTag 0x0B reset flags 0x00 reserved 0x00 parameterCount 0x00 The Reset command has no data phase Response The target...

Page 328: ...I2C slave address and the direction bit is set as write An outgoing packet is read by the host with a selected I2C slave address and the direction bit is set as read 0x00 will be sent as the response...

Page 329: ...than supported length Yes payload data from target No Set payload length to maximum supported length No No Reached maximum Report a timeout Yes End No 2 bytes Read 1 byte from target 0x5A received 0xA...

Page 330: ...eived invalid data The SPI bus configuration is Phase 1 data is sampled on rising edges Polarity 1 idle is high MSB is transmitted first For any transfer where the target does not have actual data to...

Page 331: ...out payload data from target No Set payload length to maximum supported length No No maximum Report a timeout error End Yes End No 2 bytes 0x5A received 0xA4 received Reached retries Send 0x00 to shi...

Page 332: ...data bytes of the ping packet must be sent continuously with no more than 80 ms between bytes in a fixed UART transmission mode 8 bit data no parity bit and 1 stop bit If the bytes of the ping packet...

Page 333: ...retries Figure 13 24 Host reads an ACK from target via UART Wait for ping response Yes Yes End Report Error No No Wait for 1 byte from target Wait for 1 byte from target 0x5A received 0xA7 received W...

Page 334: ...ass USB HID does not use framing packets instead the packetization inherent in the USB protocol itself is used The ability for the device to NAK Out transfers until they can be received provides the r...

Page 335: ...ere the firmware can NAK send requests from the USB host 13 4 4 4 HID reports There are 4 HID reports defined and used by the flashloader USB HID peripheral The report ID determines the direction and...

Page 336: ...ngth of 35 bytes The Packet Length header is written in little endian format and it is set to the size in bytes of the packet sent in the report This size does not include the Report ID or the Packet...

Page 337: ...bytes in the data phase RAMStartAddress No 0Eh 4 Start address of RAM segment The first parameter to GetProperty command identifies the segment See the device specific memory map for number of RAM seg...

Page 338: ...eserved USB HID Reserved SPI Slave I2C Slave UART If the peripheral is available then the corresponding bit will be set in the property value All reserved bits must be set to 0 13 5 1 3 AvailableComma...

Page 339: ..._InvalidArgument 4 The requested command s argument is undefined kStatus_Timeout 5 A timeout occurred kStatus_FlashSizeError 100 Not used kStatus_FlashAlignmentError 101 Address or length does not mee...

Page 340: ...tatus_AbortDataPhase 10002 Abort the data phase early kStatusMemoryRangeInvalid 10200 Memory range conflicts with a protected region kStatus_UnknownProperty 10300 The requested property value is undef...

Page 341: ...ovide reset status information and reset filter control NOTE The RCM registers can be written only in supervisor mode Write accesses in user mode are blocked and will result in a bus error RCM memory...

Page 342: ...0x01 Other reset a bit is set if its corresponding reset source caused the reset Address 4007_F000h base 0h offset 4007_F000h Bit 7 6 5 4 3 2 1 0 Read POR PIN WDOG 0 LOL LOC LVD WAKEUP Write Reset 1...

Page 343: ...lock 1 Reset caused by a loss of external clock 1 LVD Low Voltage Detect Reset If PMC_LVDSC1 LVDRE is set and the supply drops below the LVD trip voltage an LVD reset occurs This field is also set by...

Page 344: ...he RESET command while the device is in EzPort mode 0 Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode 1 Reset caused by EzPort receiving the RESET command whi...

Page 345: ...0 0 0 0 0 RCM_RPFC field descriptions Field Description 7 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 RSTFLTSS Reset Pin Filter Select in Stop Mode...

Page 346: ...filter count is 5 00101 Bus clock filter count is 6 00110 Bus clock filter count is 7 00111 Bus clock filter count is 8 01000 Bus clock filter count is 9 01001 Bus clock filter count is 10 01010 Bus...

Page 347: ...uring the last Chip Reset Address 4007_F000h base 7h offset 4007_F007h Bit 7 6 5 4 3 2 1 0 Read 0 EZP_MS 0 Write Reset 0 0 0 0 0 0 0 0 RCM_MR field descriptions Field Description 7 2 Reserved This fie...

Page 348: ...t caused by POR 1 Reset caused by POR 6 SPIN Sticky External Reset Pin Indicates a reset has been caused by an active low level on the external RESET pin 0 Reset not caused by external reset pin 1 Res...

Page 349: ...se this reset Any enabled wakeup source in a VLLSx mode causes a reset 0 Reset not caused by LLWU module wakeup source 1 Reset caused by LLWU module wakeup source 14 2 7 Sticky System Reset Status Reg...

Page 350: ...ebugger system setting of the System Reset Request bit in the MDM AP Control Register 0 Reset not caused by host debugger system setting of the System Reset Request bit 1 Reset caused by host debugger...

Page 351: ...onality of that mode This chapter describes all the available low power modes the sequence followed to enter exit each mode and the functionality available while in each of the modes The SMC is able t...

Page 352: ...variety of stop modes are available that allow the state retention partial power down or full power down of certain logic and or memory I O states are held in all modes of operation Several registers...

Page 353: ...locks are gated off after all stop acknowledge signals from supporting peripherals are valid The MCU is placed in a low leakage mode by powering down the internal logic and the system RAM2 partition T...

Page 354: ...entry into any low power run or stop mode The enabling of the low power run or stop mode occurs by configuring the Power Mode Control register PMCTRL The PMPROT register can be written only once afte...

Page 355: ...eld allows the MCU to enter any low leakage stop mode LLS 0 Any LLSx mode is not allowed 1 Any LLSx mode is allowed 2 Reserved This field is reserved This read only field is reserved and always has th...

Page 356: ...ield is reserved This read only field is reserved and always has the value 0 3 STOPA Stop Aborted When set this read only status bit indicates an interrupt occured during the previous stop mode entry...

Page 357: ...0 0 1 1 SMC_STOPCTRL field descriptions Field Description 7 6 PSTOPO Partial Stop Option These bits control whether a Partial Stop mode is entered when STOPM STOP When entering a Partial Stop mode fr...

Page 358: ...if PMCTRL STOPM LLSx 011 VLLS3 if PMCTRL STOPM VLLSx LLS3 if PMCTRL STOPM LLSx 100 Reserved 101 Reserved 110 Reserved 111 Reserved 15 3 4 Power Mode Status register SMC_PMSTAT PMSTAT is a read only on...

Page 359: ...mode is VLPW 0001_0000 Current power mode is VLPS 0010_0000 Current power mode is LLS 0100_0000 Current power mode is VLLS 1000_0000 Current power mode is HSRUN 15 4 Functional description 15 4 1 Powe...

Page 360: ...re Table 15 2 Power mode transition triggers Transition From To Trigger conditions 1 RUN WAIT Sleep now or sleep on exit modes entered with SLEEPDEEP clear controlled in System Control Register in ARM...

Page 361: ...d in System Control Register in ARM core See note 1 VLPS VLPR Interrupt NOTE If VLPS was entered directly from RUN transition 7 hardware forces exit back to RUN and does not allow a transition to VLPR...

Page 362: ...t debug 2 If PMCTRL STOPM 000 and STOPCTRL PSTOPO 01 or 10 then only a Partial Stop mode is entered instead of STOP 3 If PMCTRL STOPM 000 and STOPCTRL PSTOPO 00 then VLPS mode is entered instead of ST...

Page 363: ...s are enabled to all masters and slaves 4 The CPU clock is enabled and the CPU begins servicing the reset or interrupt that initiated the exit from the low power stop mode 15 4 2 3 Aborted stop mode e...

Page 364: ...e offset 0x004 LR is set to 0xFFFF_FFFF To reduce power in this mode disable the clocks to unused modules 15 4 3 2 Very Low Power Run VLPR mode In VLPR mode the on chip voltage regulator is put into a...

Page 365: ...n chip voltage regulator remains in a run regulation state but with a slightly elevated voltage output In this state the MCU is able to operate at a faster frequency compared to normal RUN mode For th...

Page 366: ...4 2 Very Low Power Wait VLPW mode VLPW mode is entered by entering the Sleep Now or Sleep On Exit mode while SLEEPDEEP is cleared and the device is in VLPR mode In VLPW the on chip voltage regulator...

Page 367: ...akage Stop LLS Very Low Leakage Stop VLLSx 15 4 5 1 STOP mode STOP mode is entered via the sleep now or sleep on exit with the SLEEPDEEP bit set in the System Control Register in the ARM core The MCG...

Page 368: ...des All LLS modes can be entered from normal RUN or VLPR modes The MCU enters LLS mode if In Sleep Now or Sleep On Exit mode SLEEPDEEP is set in the System Control Register in the ARM core and The dev...

Page 369: ...ode the user should configure the Low Leakage Wake up LLWU module to enable the desired wakeup sources The available wake up sources in VLLS are detailed in the chip configuration details for this dev...

Page 370: ...ll debug operation can continue after waking from LLS even in cases where system wakeup is due to a system reset event Entering into a VLLS mode causes all of the debug controls and settings to be pow...

Page 371: ...voltage regulator Active POR providing brown out detect Low voltage detect supporting two low voltage trip points with four warning levels per trip point 16 3 Low voltage detect LVD system This devic...

Page 372: ...low voltage condition The low voltage detection threshold is determined by LVDSC1 LVDV After an LVD reset occurs the LVD system holds the MCU in reset until the supply voltage rises above this thresho...

Page 373: ...ET pin the I O are released and default to their reset state In this case no write to REGSC ACKISO is needed 16 5 Memory map and register descriptions Details about the PMC registers can be found here...

Page 374: ...ect systems that must have LVD always on configure the Power Mode Protection PMPROT register of the SMC module SMC_PMPROT to disallow any very low power or low leakage modes from being enabled See the...

Page 375: ...e value 0 LVDV Low Voltage Detect Voltage Select Selects the LVD trip point voltage V LVD 00 Low trip point selected V LVD V LVDL 01 High trip point selected V LVD V LVDH 10 Reserved 11 Reserved 16 5...

Page 376: ...Enable Enables hardware interrupt requests for LVWF 0 Hardware interrupt disabled use polling 1 Request a hardware interrupt when LVWF 1 4 2 Reserved This field is reserved This read only field is res...

Page 377: ...led in VLPx LLS and VLLSx modes 1 Bandgap voltage reference is enabled in VLPx LLS and VLLSx modes 3 ACKISO Acknowledge Isolation Reading this field indicates whether certain peripherals and the I O p...

Page 378: ...d Field Description 0 BGBE Bandgap Buffer Enable Enables the bandgap buffer 0 Bandgap buffer not enabled 1 Bandgap buffer enabled Memory map and register descriptions K22F Sub Family Reference Manual...

Page 379: ...the MCU to exit both LLS and VLLS through a reset flow The LLWU module also includes two optional digital pin filters for the external wakeup pins See AN4503 Power Management for Kinetis MCUs for fur...

Page 380: ...n an interrupt flow when exiting LLS NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery 17 1 2...

Page 381: ...low leakge mode interrupt flow reset flow LLWU_P0 LLWU_P15 Pin filter 1 wakeup occurred Interrupt module flag detect WUPE15 2 Edge detect enter low leakge mode WUPE0 Edge detect Module7 interrupt flag...

Page 382: ...rce that caused exit from a low leakage power mode includes external pin or internal module interrupt Wake up pin filter enable registers NOTE The LLWU registers can be written only in supervisor mode...

Page 383: ...select the edge detect type for the external wakeup input pins LLWU_P3 LLWU_P0 NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS It is unaffected b...

Page 384: ...nal input pin enabled with falling edge detection 11 External input pin enabled with any change detection 17 3 2 LLWU Pin Enable 2 register LLWU_PE2 LLWU_PE2 contains the field to enable and select th...

Page 385: ...enabled with any change detection WUPE4 Wakeup Pin Enable For LLWU_P4 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin...

Page 386: ...pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection...

Page 387: ...E13 Wakeup Pin Enable For LLWU_P13 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection...

Page 388: ...module flag not used as wakeup source 1 Internal module flag used as wakeup source 4 WUME4 Wakeup Module Enable For Module 4 Enables an internal module as a wakeup source input 0 Internal module flag...

Page 389: ...et not VLLS and by reset types that trigger Chip Reset not VLLS It is unaffected by reset types that do not trigger Chip Reset not VLLS See the Introduction details for more information Address 4007_C...

Page 390: ...e To clear the flag write a 1 to WUF3 0 LLWU_P3 input was not a wake up source 1 LLWU_P3 input was a wake up source 2 WUF2 Wakeup Flag For LLWU_P2 Indicates that an enabled external wakeup pin was a s...

Page 391: ...10 WUF9 WUF8 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F2 field descriptions Field Description 7 WUF15 Wakeup Flag For LLWU_P15 Indicates that an enabled external wakeup pin was...

Page 392: ...pin was a source of exiting a low leakage power mode To clear the flag write a 1 to WUF9 0 LLWU_P9 input was not a wakeup source 1 LLWU_P9 input was a wakeup source 0 WUF8 Wakeup Flag For LLWU_P8 Indi...

Page 393: ...sm 0 Module 6 input was not a wakeup source 1 Module 6 input was a wakeup source 5 MWUF5 Wakeup flag For module 5 Indicates that an enabled internal peripheral was a source of exiting a low leakage po...

Page 394: ...mechanism 0 Module 0 input was not a wakeup source 1 Module 0 input was a wakeup source 17 3 9 LLWU Pin Filter 1 register LLWU_FILT1 LLWU_FILT1 is a control and status register that is used to enable...

Page 395: ...LLWU_FILT2 is a control and status register that is used to enable disable the digital filter 2 features for an external pin NOTE This register is reset on Chip Reset not VLLS and by reset types that...

Page 396: ...s operational only in LLS and VLLSx modes The LLWU module contains pin enables for each external pin and internal module For each external pin the user can disable or select the edge type for the wake...

Page 397: ...with a reset vector fetch 17 4 3 Initialization For an enabled peripheral wakeup input the peripheral flag must be cleared by software before entering LLS or VLLSx mode to avoid an immediate exit from...

Page 398: ...Functional description K22F Sub Family Reference Manual Rev 4 08 2016 398 NXP Semiconductors...

Page 399: ...vision 18 2 Memory map register descriptions The memory map and register descriptions below describe the registers using byte addresses MCM memory map Absolute address hex Register name Width in bits...

Page 400: ...C field descriptions Field Description 15 8 Reserved This field is reserved This read only field is reserved and always has the value 0 ASC Each bit in the ASC field indicates whether there is a corre...

Page 401: ...Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 ARB Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_PLACR field descriptions Field Description 31 10 Reserved This field is reserved This read only f...

Page 402: ...9 8 7 6 5 4 3 2 1 0 R FIDC 0 FIXC FUFC FOFC FDZC FIOC 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_ISCR field descriptions Field Description 31 FIDCE FPU input denormal interrupt enable 0 Disable in...

Page 403: ...rocessor s FPU Once set this bit remains set until software clears the FPSCR IXC bit 0 No interrupt 1 Interrupt occurred 11 FUFC FPU underflow interrupt status This read only bit is a copy of the core...

Page 404: ...Reserved This field is reserved This read only field is reserved and always has the value 0 18 2 5 Compute Operation Control Register MCM_CPO This register controls the Compute Operation Address E008_...

Page 405: ...nctional description of MCM module 18 3 1 Interrupts The MCM s interrupt is generated if any of the following is true FPU input denormal interrupt is enabled FIDCE and an input is denormalized FIDC FP...

Page 406: ...2 Search the result for asserted flags which indicate the exact interrupt sources Functional description K22F Sub Family Reference Manual Rev 4 08 2016 406 NXP Semiconductors...

Page 407: ...ture This structure allows up to four bus masters to access different bus slaves simultaneously while providing arbitration among the bus masters when they access the same slave 19 1 1 Features The cr...

Page 408: ...the master device has no knowledge of whether it actually owns the slave port it is targeting While the master does not have control of the slave port it is targeting it simply waits After the master...

Page 409: ...port When a master makes a request to a slave port the slave port checks whether the new requesting master s priority level is higher than that of the master that currently has control over the slave...

Page 410: ...er is to the ID of the last master After granted access to a slave port a master may perform as many transfers as desired to that port until another master makes a request to the same slave port The n...

Page 411: ...that all the peripheral slots are not used See the memory map chapter for details on slot assignments The bridge includes separate clock enable inputs for each of the slots to accommodate slower peri...

Page 412: ...the attached slave devices and generates select signals for modules on the peripheral bus by decoding accesses within the attached address space 20 3 1 Access support Aligned and misaligned 32 bit 16...

Page 413: ...ails of this module s instances see the chip configuration information 21 1 1 Overview The Direct Memory Access Multiplexer DMAMUX routes DMA sources called slots to any of the 16 DMA channels This pr...

Page 414: ...to four always on slots can be routed to 16 channels 16 independently selectable DMA channel routers The first four channels additionally provide a trigger functionality Each channel router can be ass...

Page 415: ...MAMUX has no external pins 21 3 Memory map register definition This section provides a detailed description of all memory mapped registers in the DMAMUX DMAMUX memory map Absolute address hex Register...

Page 416: ...MA slots peripheral slots or always on slots in the system NOTE Setting multiple CHCFG registers with the same source value will result in unpredictable behavior This is true even if a channel is disa...

Page 417: ...ing sources is followed the configuration of the DMAMUX may be changed during the normal operation of the system Functionally the DMAMUX channels may be divided into two classes Channels that implemen...

Page 418: ...MUX triggered channels The DMA channel triggering capability allows the system to schedule regular DMA transfers usually on the transmit side of certain peripherals without the intervention of the pro...

Page 419: ...rs can be automatically performed every 5 s as an example On the receive side of the SPI the SPI and DMA can be configured to transfer receive data into memory effectively implementing a method to per...

Page 420: ...where software should initiate the start of a DMA transfer an always enabled DMA source can be used to provide maximum flexibility When activating a DMA channel via software subsequent executions of t...

Page 421: ...abled before use 21 5 2 Enabling and configuring sources To enable a source with periodic triggering 1 Determine with which DMA channel the source will be associated Note that only the first 4 DMA cha...

Page 422: ...he channel 3 Write 0x85 to CHCFG1 The following code example illustrates steps 1 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8 bit...

Page 423: ...steps 2 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8 bits volatile unsigned char CHCFG0 volatile unsigned char DMAMUX_BASE_ADDR...

Page 424: ...In File main c include registers h CHCFG8 0x00 CHCFG8 0x87 Initialization application information K22F Sub Family Reference Manual Rev 4 08 2016 424 NXP Semiconductors...

Page 425: ...lex data transfers with minimal intervention from a host processor The hardware microarchitecture includes A DMA engine that performs Source address and destination address calculations Data movement...

Page 426: ...the channels provide the same functionality This structure allows data transfers associated with one channel to be preempted after the completion of a read write sequence if a higher priority channel...

Page 427: ...re equal the eDMA engine performs a series of source read destination write operations until the number of bytes specified in the minor loop byte count has moved For descriptors where the sizes are no...

Page 428: ...re initiation Initiation via a channel to channel linking mechanism for continuous transfers Peripheral paced hardware requests one per channel Fixed priority and round robin channel arbitration Chann...

Page 429: ...e eDMA continues operation until the channel retires Wait Before entering Wait mode the DMA attempts to complete its current transfer After the transfer completes the device enters Wait mode 22 3 Memo...

Page 430: ...rns the value of zero Writes to reserved bits in a register are ignored Reading or writing a reserved memory location generates a bus error DMA memory map Absolute address hex Register name Width in b...

Page 431: ...DCHPRI0 8 R W See section 22 3 21 468 4000_8104 Channel n Priority Register DMA_DCHPRI7 8 R W See section 22 3 21 468 4000_8105 Channel n Priority Register DMA_DCHPRI6 8 R W See section 22 3 21 468 40...

Page 432: ...5 481 4000_901E TCD Beginning Minor Loop Link Major Loop Count Channel Linking Disabled DMA_TCD0_BITER_ELINKNO 16 R W Undefined 22 3 36 482 4000_9020 TCD Source Address DMA_TCD1_SADDR 32 R W Undefined...

Page 433: ...Offset DMA_TCD2_DOFF 16 R W Undefined 22 3 30 475 4000_9056 TCD Current Minor Loop Link Major Loop Count Channel Linking Enabled DMA_TCD2_CITER_ELINKYES 16 R W Undefined 22 3 31 476 4000_9056 DMA_TCD...

Page 434: ...te Count Minor Loop Mapping Disabled DMA_TCD4_NBYTES_MLNO 32 R W Undefined 22 3 25 471 4000_9088 TCD Signed Minor Loop Offset Minor Loop Mapping Enabled and Offset Disabled DMA_TCD4_NBYTES_MLOFFNO 32...

Page 435: ...4 479 4000_90BE TCD Beginning Minor Loop Link Major Loop Count Channel Linking Enabled DMA_TCD5_BITER_ELINKYES 16 R W Undefined 22 3 35 481 4000_90BE TCD Beginning Minor Loop Link Major Loop Count Cha...

Page 436: ...ed 22 3 28 474 4000_90F0 TCD Destination Address DMA_TCD7_DADDR 32 R W Undefined 22 3 29 475 4000_90F4 TCD Signed Destination Address Offset DMA_TCD7_DOFF 16 R W Undefined 22 3 30 475 4000_90F6 TCD Cu...

Page 437: ...urce Address Offset DMA_TCD9_SOFF 16 R W Undefined 22 3 23 469 4000_9126 TCD Transfer Attributes DMA_TCD9_ATTR 16 R W Undefined 22 3 24 470 4000_9128 TCD Minor Byte Count Minor Loop Mapping Disabled D...

Page 438: ...4000_9156 DMA_TCD10_CITER_ELINKNO 16 R W Undefined 22 3 32 477 4000_9158 TCD Last Destination Address Adjustment Scatter Gather Address DMA_TCD10_DLASTSGA 32 R W Undefined 22 3 33 478 4000_915C TCD C...

Page 439: ...p Mapping Enabled and Offset Disabled DMA_TCD12_NBYTES_MLOFFNO 32 R W Undefined 22 3 26 472 4000_9188 TCD Signed Minor Loop Offset Minor Loop Mapping and Offset Enabled DMA_TCD12_NBYTES_MLOFFYES 32 R...

Page 440: ...oop Link Major Loop Count Channel Linking Enabled DMA_TCD13_BITER_ELINKYES 16 R W Undefined 22 3 35 481 4000_91BE TCD Beginning Minor Loop Link Major Loop Count Channel Linking Disabled DMA_TCD13_BITE...

Page 441: ...4000_91E8 TCD Signed Minor Loop Offset Minor Loop Mapping and Offset Enabled DMA_TCD15_NBYTES_MLOFFYES 32 R W Undefined 22 3 27 473 4000_91EC TCD Last Source Address Adjustment DMA_TCD15_SLAST 32 R W...

Page 442: ...op address offsets TCDn_SLAST and TCDn_DLAST_SGA are used to compute the next TCDn_SADDR and TCDn_DADDR values When minor loop mapping is enabled EMLM is 1 TCDn word2 is redefined A portion of TCDn wo...

Page 443: ...is defined as a 32 bit NBYTES field 1 Enabled TCDn word2 is redefined to include individual enable fields an offset field and the NBYTES field The individual enable fields allow the minor loop offset...

Page 444: ...Reserved 22 3 6 Error Status Register DMA_ES The ES provides information concerning the last recorded channel error Channel errors can be caused by A configuration error that is An illegal setting in...

Page 445: ...0 No source address configuration error 1 The last recorded error was a configuration error detected in the TCDn_SADDR field TCDn_SADDR is inconsistent with TCDn_ATTR SSIZE 6 SOE Source Offset Error...

Page 446: ...signal for each channel The state of any given channel enable is directly affected by writes to this register it is also affected by writes to the SERQ and CERQ registers These registers are provided...

Page 447: ...enabled 10 ERQ10 Enable DMA Request 10 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 9 ERQ9 Enable DMA Request 9...

Page 448: ...DMA request signal for the corresponding channel is enabled 22 3 8 Enable Error Interrupt Register DMA_EEI The EEI register provides a bit map for the 16 channels to enable the error interrupt signal...

Page 449: ...for corresponding channel generates an error interrupt request 11 EEI11 Enable Error Interrupt 11 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of t...

Page 450: ...annel generates an error interrupt request 1 EEI1 Enable Error Interrupt 1 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for cor...

Page 451: ...EEI to be set Setting the SAEE bit provides a global set function forcing the entire EEI contents to be set If the NOP bit is set the command is ignored This allows you to write multiple byte register...

Page 452: ...inputs If NOP is set the command is ignored This allows you to write multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Ah offset 4000_801Ah Bi...

Page 453: ...egisters as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Bh offset 4000_801Bh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAER 0 SERQ Reset 0 0 0 0 0 0 0 0 DMA_SERQ fie...

Page 454: ...ers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Ch offset 4000_801Ch Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CADN 0 CDNE Reset 0 0 0 0 0 0 0 0 DMA_CDNE field de...

Page 455: ...ads of this register return all zeroes Address 4000_8000h base 1Dh offset 4000_801Dh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAST 0 SSRT Reset 0 0 0 0 0 0 0 0 DMA_SSRT field descriptions Field Descri...

Page 456: ...o write multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Eh offset 4000_801Eh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEI 0 CERR Reset 0 0 0...

Page 457: ...to write multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Fh offset 4000_801Fh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAIR 0 CINT Reset 0 0...

Page 458: ...to INT a 1 in any bit position clears the corresponding channel s interrupt request A zero in any bit position has no affect on the corresponding channel s current interrupt status The CINT register i...

Page 459: ...d 1 The interrupt request for corresponding channel is active 9 INT9 Interrupt Request 9 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel...

Page 460: ...then routed to the interrupt controller During the execution of the interrupt service routine associated with any DMA errors it is software s responsibility to clear the appropriate bit negating the e...

Page 461: ...l has not occurred 1 An error in this channel has occurred 14 ERR14 Error In Channel 14 0 An error in this channel has not occurred 1 An error in this channel has occurred 13 ERR13 Error In Channel 13...

Page 462: ...ror in this channel has not occurred 1 An error in this channel has occurred 4 ERR4 Error In Channel 4 0 An error in this channel has not occurred 1 An error in this channel has occurred 3 ERR3 Error...

Page 463: ...refore this status is affected by the ERQ bits Address 4000_8000h base 34h offset 4000_8034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 1...

Page 464: ...sserted for the period when a Hardware Request is Present on the Channel After the Request is completed and Channel is free the HRS bit is automatically cleared by hardware 0 A hardware service reques...

Page 465: ...quest for channel 6 is not present 1 A hardware service request for channel 6 is present 5 HRS5 Hardware Request Status Channel 5 The HRS bit for its respective channel remains asserted for the period...

Page 466: ...its respective channel remains asserted for the period when a Hardware Request is Present on the Channel After the Request is completed and Channel is free the HRS bit is automatically cleared by har...

Page 467: ...uest for channel 10 1 Enable asynchronous DMA request for channel 10 9 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 0 Disable asynchronous DMA request for channel 9 1 Enable asyn...

Page 468: ...nel arbitration is enabled CR ERCA 0 the contents of these registers define the unique priorities associated with each channel The channel priorities are evaluated by numeric value for example 0 is th...

Page 469: ...TCD Source Address DMA_TCDn_SADDR Address 4000_8000h base 1000h offset 32d i where i 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SADDR W Rese...

Page 470: ...nt a circular data queue easily For data queues requiring power of 2 size bytes the queue should start at a 0 modulo size address and the SMOD field should be set to the appropriate value for the queu...

Page 471: ...W Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined at reset DMA_TCDn_NBYTES_MLNO field descriptions Field Description NBYTES Minor Byte Transfer Count Number of...

Page 472: ...ddress 4000_8000h base 1008h offset 32d i where i 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SMLOE DMLOE NBYTES W Reset x x x x x x x x x x x x x x x x Bit 15 14 13 12 11 10 9 8 7...

Page 473: ...oop Offset Minor Loop Mapping and Offset Enabled DMA_TCDn_NBYTES_MLOFFYES One of three registers this register TCD_NBYTES_MLNO or TCD_NBYTES_MLOFFNO defines the number of bytes to transfer per request...

Page 474: ...r count has transferred This is an indivisible operation and cannot be halted It can however be stalled by using the bandwidth control field or via preemption After the minor count is exhausted the SA...

Page 475: ...to the destination data 22 3 30 TCD Signed Destination Address Offset DMA_TCDn_DOFF Address 4000_8000h base 1014h offset 32d i where i 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read DOFF Wr...

Page 476: ...K channel linking NOTE This bit must be equal to the BITER ELINK bit otherwise a configuration error is reported 0 The channel to channel linking is disabled 1 The channel to channel linking is enable...

Page 477: ...ag enables linking to another channel defined by the LINKCH field The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR START bit of the specifie...

Page 478: ...x x x x x x x x x x x Notes x Undefined at reset DMA_TCDn_DLASTSGA field descriptions Field Description DLASTSGA Destination last address adjustment or the memory address for the next transfer contro...

Page 479: ...d after the last write of each minor loop This behavior is a side effect of reducing start up latency 00 No eDMA engine stalls 01 Reserved 10 eDMA engine stalls for 4 cycles after each R W 11 eDMA eng...

Page 480: ...s TCD specifies a scatter gather format The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution 3 DREQ Disable Request...

Page 481: ...inking on minor loop complete As the channel completes the minor loop this flag enables the linking to another channel defined by BITER LINKCH The link target channel initiates a channel service reque...

Page 482: ...CITER field If the channel is configured to execute a single service request the initial values of BITER and CITER should be 0x0001 22 3 36 TCD Beginning Minor Loop Link Major Loop Count Channel Link...

Page 483: ...austed the contents of this field are reloaded into the CITER field NOTE When the software loads the TCD this field must be set equal to the corresponding CITER field otherwise a configuration error i...

Page 484: ...gh the control module then into the program model and channel arbitration In the next cycle the channel arbitration performs using the fixed priority or round robin algorithm After arbitration is comp...

Page 485: ...ssing continues until the minor byte count has transferred After the minor byte count has moved the final phase of the basic data flow is performed In this segment the address path logic performs the...

Page 486: ...l setting in the transfer control descriptor or an illegal priority register setting in Fixed Arbitration mode or An error termination to a bus master read or write cycle A configuration error is repo...

Page 487: ...d if the scatter gather address DLAST_SGA is not aligned on a 32 byte boundary If minor loop channel linking is enabled upon channel completion a configuration error is reported when the link is attem...

Page 488: ...ta transfer in the event the full data transfer is no longer needed The cancel transfer bit does not abort the channel It simply stops the transferring of data and then retires the channel through its...

Page 489: ...his allows for a pool of low priority large data moving channels to be defined These low priority channels can be configured to not preempt each other thus preventing a low priority channel from consu...

Page 490: ...AM transfers occur at the core s datapath width For all transfers involving the internal peripheral bus 32 bit transfer sizes are used In all cases the transfer rate includes the time to read the sour...

Page 491: ...ation write 12 13 This cycle represents the data phase of the last destination write 13 14 The eDMA engine completes the execution of the inner minor loop and prepares to write back the required TCDn...

Page 492: ...em bus read data phase write_ws Wait states seen during the system bus write data phase exit Channel shutdown 3 cycles 22 4 4 3 eDMA performance example Consider a system with the following characteri...

Page 493: ...gistering is absorbed in or overlaps the previous executing channel Note When channel linking or scatter gather is enabled a two cycle delay is imposed on the next channel selection and startup This a...

Page 494: ...es such as interrupts major loop channel linking and scatter gather operations if enabled Table 22 8 TCD Control and Status fields TCDn_CSR field name Description START Control bit to start channel ex...

Page 495: ...bytes added to current address after each transfer often the same value as xSIZE Each DMA source S and destination D has its own Address xADDR Size xSIZE Offset xOFF Modulo xMOD Last Address Adjustmen...

Page 496: ...considerations for the eDMA 22 5 3 1 Fixed channel arbitration In this mode the channel service request from the highest priority channel is selected to execute 22 5 3 2 Round robin channel arbitrati...

Page 497: ...to the TCDn_CSR START bit requests channel service 2 The channel is selected by arbitration for servicing 3 eDMA engine writes TCDn_CSR DONE 0 TCDn_CSR START 0 TCDn_CSR ACTIVE 1 4 eDMA engine reads ch...

Page 498: ...Dn_SLAST 32 TCDn_DLAST_SGA 32 This would generate the following sequence of events 1 First hardware that is eDMA peripheral request for channel service 2 The channel is selected by arbitration for ser...

Page 499: ...n transfers are executed as follows a Read byte from location 0x1010 read byte from location 0x1011 read byte from 0x1012 read byte from 0x1013 b Write 32 bits to location 0x2010 first iteration of th...

Page 500: ...re a circular buffer is created where the address wraps to the original value while the 28 upper address bits 0x1234567x retain their original value In this example the source address is set to 0x1234...

Page 501: ...mer s model The TCD status bits execute the following sequence for a hardware activated channel Stage TCDn_CSR bits State START ACTIVE DONE 1 0 0 0 Channel service request via hardware peripheral requ...

Page 502: ...set simultaneously in the global TCD map a higher priority channel is actively preempting a lower priority channel 22 5 6 Channel Linking Channel linking or chaining is a mechanism where one channel s...

Page 503: ...ng table summarizes how a DMA channel can link to another DMA channel i e use another channel s TCD at the end of a loop Table 22 10 Channel Linking Parameters Desired Link Behavior TCD Control Field...

Page 504: ...he TCD major e_link would be set in the programmer s model but it would be unclear whether the actual link was made before the channel retired The following coherency model is recommended when executi...

Page 505: ...ing the major linkch field and the e_sg bit with a single read For both dynamic channel linking and scatter gather requests the TCD local memory controller forces the TCD major e_link and TCD e_sg bit...

Page 506: ...ng major loop channel linking For a channel using major loop channel linking the coherency model described here may be used for a dynamic scatter gather request This method uses the TCD dlast_sga fiel...

Page 507: ...ecker RCCU Checker Lake Alarms delay_element delay_element delay_element delay_element DMA Inputs DMA Outputs DMA Outputs Signal Compression Signal Compression DMA 22 5 8 1 Initialization To prevent t...

Page 508: ...in a normal fashion NOTE Error Status Register DMA_ES is read only the bits cannot be cleared It saves the last recorded error The VLD bit shows the user whether any error bits in the Error Register a...

Page 509: ...rals and optionally assert the RESET pin to reset external devices circuits The overflow of the watchdog counter must not occur if the software code works well and services the watchdog to re start th...

Page 510: ...to stop mode the EWM s counter freezes There are two possible ways to exit from Stop mode On exit from stop mode through a reset the EWM remains disabled On exit from stop mode by an interrupt the EW...

Page 511: ...disabled 23 1 3 Block Diagram This figure shows the EWM block diagram Clock Divider Logic LPO_CLK Low Power Clock Clock Gating Cell AND Enable EWM_CTRL EWMEN EWM_CLKPRESCALER CLK_DIV 8 bit Counter OR...

Page 512: ...1000 Control Register EWM_CTRL 8 R W 00h 23 3 1 512 4006_1001 Service Register EWM_SERV 8 W always reads 0 00h 23 3 2 513 4006_1002 Compare Low Register EWM_CMPL 8 R W 00h 23 3 3 513 4006_1003 Compare...

Page 513: ...ervice Register EWM_SERV The SERV register provides the interface from the CPU to the EWM module It is write only and reads of this register return zero Address 4006_1000h base 1h offset 4006_1001h Bi...

Page 514: ...256 clocks time for the CPU to refresh the EWM counter NOTE This register can be written only once after a CPU reset Writing this register more than once generates a bus transfer error NOTE The valid...

Page 515: ...lected low power clock source for running the EWM counter can be prescaled as below Prescaled clock frequency low power clock source frequency 1 CLK_DIV 23 4 Functional Description The following secti...

Page 516: ...ed by the EWM_out signal only after the EWM is enabled by the EWMEN bit in the CTRL register Note EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset 23 4...

Page 517: ...is not accessible to the CPU 23 4 4 EWM Compare Registers The compare registers CMPL and CMPH are write once after a CPU reset and cannot be modified until another CPU reset occurs The EWM compare reg...

Page 518: ...d the EWM The EWM counter is reset to zero and the EWM_out output signal is asserted irrespective of the input EWM_in 23 4 6 EWM Interrupt When EWM_out is asserted an interrupt request is generated to...

Page 519: ...ation The watchdog monitors the operation of the system by expecting periodic communication from the software generally known as servicing or refreshing the watchdog If this periodic refreshing does n...

Page 520: ...is operational NOTE Reading the watchdog timer counter while running the watchdog on the bus clock might not give the accurate counter value Windowed refresh option Provides robust check that program...

Page 521: ...esh Seq No config after unlocking No unlock after reset 0xB480 0xA602 System Bus Clock 32 bit Modulus Reg Time out Value DebugEN Window_begin WDOGTEST STOPEN WAITEN WDOGT WDOG CLKSRC WINEN WDOGEN WDOG...

Page 522: ...gister WDOG_UNLOCK 2 Wait one bus clock cycle You cannot update registers on the bus clock cycle immediately following the write of the unlock sequence 3 An update window equal in length to the watchd...

Page 523: ...r words you must write at least the first word of the unlocking sequence within the WCT after reset After this is done you have a further 20 bus clock cycles the maximum allowed gap between the words...

Page 524: ...ents beyond a certain count as specified by the watchdog window register This is known as refreshing the watchdog within a window of the total time out period If a refresh is attempted before the time...

Page 525: ...unlock and configure it within WCT You must not try to refresh or unlock the WDOG in this state or unknown behavior may result Upon exit from mode the WDOG timer restarts and the WDOG has to be unloc...

Page 526: ...tomatically disabled in the test mode 24 4 1 Quick test In this test the time out value of watchdog timer is programmed to a very low value to achieve quick time out The only difference between the qu...

Page 527: ...compares with the Nth byte of the time out value register In this way the byte N is also tested along with the link between it and the preceding stage No other stages N 2 N 3 and N 1 N 2 are enabled...

Page 528: ...tes of two values of the refresh sequence The watchdog can also generate an interrupt If IRQ_RST_EN is set then on the above mentioned events WDOG_ST_CTRL_L INT_FLG is set generating an interrupt A wa...

Page 529: ...et Count register WDOG_RSTCNT 16 R W 0000h 24 7 11 535 4005_2016 Watchdog Prescaler register WDOG_PRESC 16 R W 0400h 24 7 12 535 24 7 1 Watchdog Status and Control Register High WDOG_STCTRLH Address 4...

Page 530: ...N Enables or disables WDOG in Wait mode 0 WDOG is disabled in CPU Wait mode 1 WDOG is enabled in CPU Wait mode 6 STOPEN Enables or disables WDOG in Stop mode 0 WDOG is disabled in CPU Stop mode 1 WDOG...

Page 531: ...escriptions Field Description 15 INTFLG Interrupt flag It is set when an exception occurs IRQRSTEN 1 is a precondition to set this flag INTFLG 1 results in an interrupt being issued followed by a rese...

Page 532: ...Register High WDOG_WINH NOTE You must set the Window Register value lower than the Time out Value Register Address 4005_2000h base 8h offset 4005_2008h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read...

Page 533: ...the system 24 7 7 Watchdog Refresh register WDOG_REFRESH Address 4005_2000h base Ch offset 4005_200Ch Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WDOGREFRESH Write Reset 1 0 1 1 0 1 0 0 1 0 0 0 0 0...

Page 534: ...0h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TIMEROUTHIGH Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG_TMROUTH field descriptions Field Description TIMEROUTHIGH Shows the value of the upper 1...

Page 535: ...0 0 0 0 0 0 0 0 WDOG_PRESC field descriptions Field Description 15 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 8 PRESCVAL 3 bit prescaler for the...

Page 536: ...ue for the lower byte of the refresh or unlock register Take the refresh operation that expects a write of 0xA602 followed by 0xB480 to the refresh register as an example Table 24 1 Refresh for 8 bit...

Page 537: ...ut for watchdog functional test A maximum time period of 2 clock A cycles plus 2 clock B cycles elapses from the time a switch is requested to the occurrence of the actual clock switch where clock A a...

Page 538: ...ctional test mode and therefore you should pull the watchdog out of the functional test mode within WCT time of reset After emerging from a reset due to a watchdog functional test you still need to go...

Page 539: ...nce clock internal or external as a source for the MCU system clock The MCG operates in conjuction with a crystal oscillator which allows an external crystal ceramic resonator or another external cloc...

Page 540: ...slow or the fast clock can be selected as the clock source for the MCU Can be used as a clock source for other on chip peripherals Control signals for the MCG external reference low power oscillator c...

Page 541: ...ce for other on chip peripherals MCG FLL Clock MCGFLLCLK is provided as a clock source for other on chip peripherals MCG Fixed Frequency Clock MCGFFCLK is provided as a clock source for other on chip...

Page 542: ...PLLCLKEN IREFS MCG Crystal Oscillator Enable Detect n 0 7 n Oscillator OSC0 Oscillator OSC2 OSCSEL OSCINIT EREFS HGO RANGE PLLS Phase Detector Charge Pump Internal Filter VCO VCOOUT PLL VDIV 24 25 26...

Page 543: ...8 R W See section 25 3 2 545 4006_4002 MCG Control 3 Register MCG_C3 8 R W Undefined 25 3 3 546 4006_4003 MCG Control 4 Register MCG_C4 8 R W See section 25 3 4 547 4006_4004 MCG Control 5 Register MC...

Page 544: ...e clock source for MCGOUTCLK In FBE mode it is not required to meet this range but it is recommended in the cases when trying to enter a FLL mode from FBE 000 If RANGE 0 or OSCSEL 1 Divide Factor is 1...

Page 545: ...nable Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference clock The LOCRE0 only has an affect when CME0 is set 0 Interrupt request is generated on a...

Page 546: ...o 1 will transition the MCG into BLPI mode In any other MCG mode LP bit has no affect 0 FLL or PLL is not disabled in bypass modes 1 FLL or PLL is disabled in bypass modes lower power 0 IRCS Internal...

Page 547: ...o its maximum frequency with a 32 768 kHz reference The following table identifies settings for the DCO frequency range NOTE The system clocks derived from this source should not exceed their specifie...

Page 548: ...RIM value stored in nonvolatile memory is to be used it is your responsibility to copy that value from the nonvolatile memory location to this bit 1 A value for FCTRIM is loaded during reset from a fa...

Page 549: ...g either PLLCLKEN 0 or PLLS the PRDIV 0 value must not be changed when LOCK0 is zero Table 25 1 PLL External Reference Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor P...

Page 550: ...ock FEE FBE PEE PBE or BLPE Whenever the CME0 bit is set to a logic 1 the value of the RANGE0 bits in the C2 register should not be changed CME0 bit should be set to a logic 0 before the MCG enters an...

Page 551: ...he C5 register or the VDIV0 4 0 bits in the C6 register causes the lock status bit to clear and stay cleared until the PLL has reacquired lock Loss of PLL reference clock will also cause the LOCK0 bit...

Page 552: ...t due to internal synchronization between clock domains The IRCST bit will only be updated if the internal reference clock is enabled either by the MCG being in a mode that uses the IRC or by setting...

Page 553: ...ior to the new clock mode switch Otherwise FLL filter and frequency values will change 0 FLL filter and FLL frequency will reset on changes to currect clock mode 1 Fll filter and FLL frequency retain...

Page 554: ...ompare Value Low Register MCG_ATCVL Address 4006_4000h base Bh offset 4006_400Bh Bit 7 6 5 4 3 2 1 0 Read ATCVL Write Reset 0 0 0 0 0 0 0 0 MCG_ATCVL field descriptions Field Description ATCVL ATM Com...

Page 555: ...s if a interrupt or a reset request is made following a loss of RTC external reference clock The LOCRE1 only has an affect when CME1 is set 0 Interrupt request is generated on a loss of RTC external r...

Page 556: ...TC Loss of Clock Status This bit indicates when a loss of clock has occurred This bit is cleared by writing a logic 1 to it when set 0 Loss of RTC has not occur 1 Loss of RTC has occur 25 3 13 MCG Con...

Page 557: ...ate diagram The nine states of the MCG are shown in the following figure and are described in Table 25 3 The arrows indicate the permitted MCG mode transitions FEE FEI Reset BLPI FBI FBE BLPE PBE PEE...

Page 558: ...ccur 00 is written to C1 CLKS 1 is written to C1 IREFS 0 is written to C6 PLLS In FEI mode MCGOUTCLK is derived from the FLL clock DCOCLK that is controlled by the 32 kHz Internal Reference Clock IRC...

Page 559: ...n to C1 CLKS 0 is written to C1 IREFS C1 FRDIV must be written to divide external reference clock to be within the range of 31 25 kHz to 39 0625 kHz 0 is written to C6 PLLS 0 is written to C2 LP In FB...

Page 560: ...following conditions occur 10 is written to C1 CLKS 0 is written to C1 IREFS 1 is written to C2 LP In BLPE mode MCGOUTCLK is derived from the OSCSEL external reference clock The FLL is disabled and P...

Page 561: ...te bits are changed while in FLL engaged internal FEI or FLL engaged external FEE mode the MCGOUTCLK switches to the new selected DCO range within three clocks of the selected DCO clock After switchin...

Page 562: ...is disabled in Stop mode 25 4 4 External Reference Clock The MCG module can support an external reference clock in all modes See the device datasheet for external reference frequency range When C1 IR...

Page 563: ...ATM The MCG Auto Trim ATM is a MCG feature that when enabled it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference The selection...

Page 564: ...abled the ATM expected count needs to be derived and stored into the ATCV register The ATCV expected count is derived based on the required target Internal Reference Clock IRC frequency and the freque...

Page 565: ...ource If entering FBE clear C1 IREFS to switch to the external reference and change C1 CLKS to 2 b10 so that the external reference clock is selected as the system clock source The C1 FRDIV bits shoul...

Page 566: ...t to 1 The resulting DCO output MCGOUTCLK frequency with the new multiplier of 732 will be 24 MHz When using a 32 768 kHz external reference if the maximum mid range DCO frequency that can be achieved...

Page 567: ...4 MHz at mid low range If C4 DRST_DRS bits are set to 2 b10 the multiplication factor is set to 1920 and the resulting DCO output frequency is 62 91 MHz at mid high range If C4 DRST_DRS bits are set t...

Page 568: ...LL_R F fext FLL_R must be in the range of 31 25 kHz to 39 0625 kHz FBE FLL bypassed external OSCCLK OSCCLK FLL_R must be in the range of 31 25 kHz to 39 0625 kHz FBI FLL bypassed internal MCGIRCLK Sel...

Page 569: ...t to 3 b010 or divide by 128 because 4 MHz 128 31 25 kHz which is in the 31 25 kHz to 39 0625 kHz range required by the FLL C1 IREFS cleared to 0 selecting the external reference clock and enabling th...

Page 570: ...only sets up the multiply value for PLL usage in PBE mode c BLPE If transitioning through BLPE mode clear C2 LP to 0 here to switch to PBE mode d PBE Loop until S PLLST is set indicating that the curr...

Page 571: ...BLPE MODE C2 0x1E C2 LP 1 CHECK CHECK C1 0x10 CHECK CONTINUE IN PEE MODE S PLLST 1 S LOCK 1 S CLKST 10 S CLKST 11 S LP 1 S IREFST 0 S OSCINIT 1 C5 0x01 C5 VDIV 1 Figure 25 3 Flowchart of FEI to PEE mo...

Page 572: ...is desired first set C2 LP to 1 b BLPE FBE C6 0x00 C6 PLLS clear to 0 to select the FLL At this time with C1 FRDIV value of 3 b010 the FLL divider is set to 128 resulting in a reference frequency of 4...

Page 573: ...ected as the reference clock source c Loop until S CLKST are 2 b01 indicating that the internal reference clock is selected to feed MCGOUTCLK 4 Lastly FBI transitions into BLPI mode a C2 0x02 C2 LP is...

Page 574: ...CK S IREFST 0 CHECK S CLKST 01 YES NO YES C2 LP 1 C6 0x00 IN BLPE MODE IN BLPE MODE NO YES C2 0x1C C2 LP 0 C2 0x1E ENTER BLPE MODE C2 LP 1 Figure 25 4 Flowchart of PEE to BLPI mode transition using an...

Page 575: ...set to 2 b00 to select the output of the FLL as system clock source C1 FRDIV remain at 3 b010 or divide by 128 for a reference of 4 MHz 128 31 25 kHz C1 IREFS cleared to 0 selecting the external refe...

Page 576: ...tor will switch back to 640 C1 0x10 C2 0x00 C2 0x1C CHECK CHECK CHECK S OSCINIT 1 CONTINUE IN FEE MODE NO NO NO YES YES YES START IN BLPI MODE S IREFST 0 S CLKST 00 Figure 25 5 Flowchart of BLPI to FE...

Page 577: ...3 8 MHz 8 32 MHz crystals and resonators High Range mode Automatic Gain Control AGC to optimize power consumption in high frequency ranges 3 8 MHz 8 32 MHz using low power mode High gain option in fr...

Page 578: ...n details for the external reference clock source in this MCU The figure found here shows the block diagram of the OSC module XTAL EXTAL XTL_CLK Mux 4096 Counter OSC Clock Enable STOP OSCERCLK_UNDIV E...

Page 579: ...s all possible connections Table 26 2 External Caystal Resonator Connections Oscillator Mode Connections Low frequency 32 kHz low power Connection 1 Low frequency 32 kHz high gain Connection 2 Connect...

Page 580: ...R SCxP bits OSC VSS Cx Cy RF Crystal or Resonator XTAL EXTAL Figure 26 4 Crystal Ceramic Resonator Connections Connection 3 26 6 External Clock Connections In external clock mode the pins can be conne...

Page 581: ...ion page 4006_5000 OSC Control Register OSC_CR 8 R W 00h 26 7 1 1 581 4006_5002 OSC_DIV OSC_OSC_DIV 8 R W 00h 26 7 1 2 583 26 7 1 1 OSC Control Register OSC_CR NOTE After OSC is enabled and starts gen...

Page 582: ...4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 SC2P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load 0 Disable the selection 1 A...

Page 583: ...rved This read only field is reserved and always has the value 0 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 Reserved This field is reserved This re...

Page 584: ...ircuits 26 8 1 1 Off The OSC enters the Off state when the system does not require OSC clocks Upon entering this state XTL_CLK is static unless OSC is configured to select the clock from the EXTAL pad...

Page 585: ...OSC_CLK_OUT Its frequency is determined by the external components being used 26 8 1 4 External Clock mode The OSC enters external clock state when it is enabled and external reference clock selectio...

Page 586: ...ternal capacitors could be used 26 8 2 2 Low Frequency Low Power Mode In low frequency low power mode the oscillator uses a gain control loop to minimize power consumption As the oscillation amplitude...

Page 587: ...l It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels 26 8 3 Counter The oscillator output clock OSC_CLK_OUT is gated off until...

Page 588: ...l register settings If CR ERCLKEN and CR EREFSTEN are set before entry to Low Leakage Stop modes the OSC is still functional in these modes After waking up from Very Low Leakage Stop VLLSx modes all O...

Page 589: ...e RTC 27 1 1 Features and Modes The key features of the RTC oscillator are as follows Supports 32 kHz crystals with very low power Consists of internal feed back resistor Consists of internal programm...

Page 590: ...ation to find out which signals are actually connected to the external pins Table 27 1 RTC Signal Descriptions Signal Description I O EXTAL32 Oscillator Input I XTAL32 Oscillator Output O 27 2 1 EXTAL...

Page 591: ...e module includes an amplifier which supplies the negative resistor for the RTC oscillator The gain of the amplifier is controlled by the amplitude detector which optimizes the power consumption A sch...

Page 592: ...iew There is no reset state associated with the RTC oscillator 27 7 Interrupts The RTC oscillator does not generate any interrupts Reset Overview K22F Sub Family Reference Manual Rev 4 08 2016 592 NXP...

Page 593: ...iguration of the memory and uses this information to ensure a proper interface The following table shows the supported read write operations Flash memory type Read Write Program flash memory 8 bit 16...

Page 594: ...8 set 64 bit line size cache for a total of thirty two 64 bit entries with controls for replacement algorithm and lock per way for each bank Single entry buffer per bank Invalidation control for the s...

Page 595: ...gram visible writes must occur after a programming or erase event is completed and before the new memory image is accessed The cache is a 4 way set associative cache with 8 sets The ways are numbered...

Page 596: ...608 4001_F13C Cache Tag Storage FMC_TAGVDW1S7 32 R W 0000_0000h 28 4 5 608 4001_F140 Cache Tag Storage FMC_TAGVDW2S0 32 R W 0000_0000h 28 4 6 609 4001_F144 Cache Tag Storage FMC_TAGVDW2S1 32 R W 0000_...

Page 597: ...0S7L 32 R W 0000_0000h 28 4 9 611 4001_F240 Cache Data Storage upper word FMC_DATAW1S0U 32 R W 0000_0000h 28 4 10 611 4001_F244 Cache Data Storage lower word FMC_DATAW1S0L 32 R W 0000_0000h 28 4 11 61...

Page 598: ...001_F2A0 Cache Data Storage upper word FMC_DATAW2S4U 32 R W 0000_0000h 28 4 12 612 4001_F2A4 Cache Data Storage lower word FMC_DATAW2S4L 32 R W 0000_0000h 28 4 13 613 4001_F2A8 Cache Data Storage uppe...

Page 599: ...0h 28 4 14 613 4001_F2E4 Cache Data Storage lower word FMC_DATAW3S4L 32 R W 0000_0000h 28 4 15 614 4001_F2E8 Cache Data Storage upper word FMC_DATAW3S5U 32 R W 0000_0000h 28 4 14 613 4001_F2EC Cache D...

Page 600: ...will occur 19 Reserved This field is reserved 18 M2PFD Master 2 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master...

Page 601: ...rmed by this master 10 Only write accesses may be performed by this master 11 Both read and write accesses may be performed by this master 3 2 M1AP 1 0 Master 1 Access Protection This field controls w...

Page 602: ...access time of the flash array expressed in system clock cycles and RWSC is defined as Access time of flash array system clocks RWSC 1 The FMC automatically calculates this value based on the ratio of...

Page 603: ...ion buffer and single entry buffer are immediately cleared This bit always reads as zero 0 Speculation buffer and single entry buffer are not affected 1 Invalidate clear speculation buffer and single...

Page 604: ...etches or speculative accesses are initiated in response to instruction fetches 0 Do not prefetch in response to instruction fetches 1 Enable prefetches in response to instruction fetches 0 B0SEBE Ban...

Page 605: ...This read only field defines the number of wait states required to access the bank 1 flash memory The relationship between the read access time of the flash array expressed in system clock cycles and...

Page 606: ...k 1 Data Prefetch Enable This bit controls whether prefetches or speculative accesses are initiated in response to data references 0 Do not prefetch in response to data references 1 Enable prefetches...

Page 607: ...16 R 0 tag 18 5 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R tag 18 5 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW0Sn field descriptions Field Desc...

Page 608: ...16 R 0 tag 18 5 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R tag 18 5 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW1Sn field descriptions Field Des...

Page 609: ...16 R 0 tag 18 5 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R tag 18 5 0 valid W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW2Sn field descriptions Field Desc...

Page 610: ...tag 18 5 14 bit tag for cache entry 4 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 valid 1 bit valid for cache entry 28 4 8 Cache Data Storage upper...

Page 611: ...0 FMC_DATAW0SnL field descriptions Field Description data 31 0 Bits 31 0 of data entry 28 4 10 Cache Data Storage upper word FMC_DATAW1SnU The cache of 64 bit entries is a 4 way set associative cache...

Page 612: ...escription data 31 0 Bits 31 0 of data entry 28 4 12 Cache Data Storage upper word FMC_DATAW2SnU The cache of 64 bit entries is a 4 way set associative cache with 8 sets The ways are numbered 0 3 and...

Page 613: ...scription data 31 0 Bits 31 0 of data entry 28 4 14 Cache Data Storage upper word FMC_DATAW3SnU The cache of 64 bit entries is a 4 way set associative cache with 8 sets The ways are numbered 0 3 and t...

Page 614: ...figuration Besides managing the interface between the device and the flash memory the FMC can be used to restrict access from crossbar switch masters and for program flash only to customize the cache...

Page 615: ...rences or both to the cache or the single entry buffer Likewise speculation can be enabled or disabled for either type of access If both instruction fetches and data references are cached then the cac...

Page 616: ...the fourth longword like the second longword takes only 1 clock due to the 64 bit flash memory data bus 28 5 4 Flash Access Control FAC Function The Flash Access Control FAC is a configurable memory p...

Page 617: ...ister is implemented Writes to any read only or reserved registers are ignored attempts to access flash register space above offset 2B will generate a transfer error The terms supervisor and user mode...

Page 618: ...9 8 7 6 5 4 3 2 1 0 R XA 63 32 W Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes Pre programmed flash valuex Undefined at reset x_XACCH field descriptions Field Descriptio...

Page 619: ...31 0 are contained in x_SACCL The x_SACC H L registers provide a bit map for the flash segments to allow supervisor only or user and supervisor access to the associated segment During the reset sequen...

Page 620: ...he values is signified by x in the reset value Address 0h base 24h offset 24h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SA 31 0 W Reset x x x x x x x...

Page 621: ...able flash size rounded up to nearest power of 2 divided by 32 or 64 depending on the amount of available program flash This field determines which bits in the address are used to index into the x_SAC...

Page 622: ...the 2 NVXACCx fields are ANDed the access protection can only be increased A segment s access controls can be changed from data read and execute XAn 1 to execute only XAn 0 or from supervisor and user...

Page 623: ...l bits within the x_SACC and x_XACC registers as shown in the next figure Program flash size 64 Program flash size 64 Program flash size 64 Program flash size 64 Program flash size 64 Program flash si...

Page 624: ...protected segment when not open to program commands causes a Protection Violation flag PGMCHK The FMU will not execute the PGMCHK command on a segment that has been configured as execute only The Fla...

Page 625: ...isor data which poses issues if the reset vector is located in a segment marked execute only Additional logic has been implemented to allow supervisor data fetches to execute only spaces after reset u...

Page 626: ...signed int i segment index i addr 8 seg_size 0x0f 0x3f form 6 bit segment index sacc_flag sacc i 1 extract sacc bit for this segment xacc_flag xacc i 1 extract xacc bit for this segment create a 4 tup...

Page 627: ...to the remaining available on chip flash The device continues to support the end user with standard security features that further limit external access to flash resources 28 6 Initialization and appl...

Page 628: ...Initialization and application information K22F Sub Family Reference Manual Rev 4 08 2016 628 NXP Semiconductors...

Page 629: ...move bits from the 1 state erased to the 0 state programmed Only the erase operation restores bits from 0 to 1 bits cannot be programmed from a 0 to a 1 CAUTION A flash memory location must be in the...

Page 630: ...t in program and erase algorithms with verify Read access to one program flash block is possible while programming or erasing data in the other program flash block 29 1 1 2 Other Flash Memory Module F...

Page 631: ...ommon Command Object A group of flash registers that are used to pass command address data and any associated parameters to the memory controller in the flash memory module Flash block A macro within...

Page 632: ...address 2 0 000 Program flash The program flash memory provides nonvolatile storage for vectors and code store Program flash Sector The smallest portion of the program flash memory consecutive address...

Page 633: ...g the Chip Using Backdoor Key Access 0x0_0408 0x0_040B 4 Program flash protection bytes Refer to the description of the Program Flash Protection Registers FPROT0 3 0x0_040F 1 Reserved 0x0_040E 1 Reser...

Page 634: ...Field The Program Once Field in the program flash IFR provides 96 bytes of user data storage separate from the program flash main array The user can program the Program Once Field one time only as th...

Page 635: ...FTFA_FCCOB1 8 R W 00h 29 3 3 5 641 4002_0007 Flash Common Command Object Registers FTFA_FCCOB0 8 R W 00h 29 3 3 5 641 4002_0008 Flash Common Command Object Registers FTFA_FCCOB7 8 R W 00h 29 3 3 5 64...

Page 636: ...A_XACCL0 8 R Undefined 29 3 3 7 644 4002_0020 Supervisor only Access Registers FTFA_SACCH3 8 R Undefined 29 3 3 8 645 4002_0021 Supervisor only Access Registers FTFA_SACCH2 8 R Undefined 29 3 3 8 645...

Page 637: ...pted a read from a flash memory resource that was being manipulated by a flash command CCIF 0 Any simultaneous access is detected as a collision error by the block arbitration logic The read data in t...

Page 638: ...unctional state of the flash memory module The erase control bits ERSAREQ and ERSSUSP have write restrictions The unassigned bits read as noted and are not writable Address 4002_0000h base 1h offset 4...

Page 639: ...is executing 0 No suspend requested 1 Suspend the current Erase Flash Sector command execution 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 Reserved...

Page 640: ...ility of the current flash contents The state of the FSLACC bits is only relevant when SEC is set to secure When SEC is set to unsecure the FSLACC setting does not matter 00 NXP factory access granted...

Page 641: ...0 FCCOB1 FCCOBB Address 4002_0000h base 4h offset 1d i where i 0d to 11d Bit 7 6 5 4 3 2 1 0 Read CCOBn Write Reset 0 0 0 0 0 0 0 0 FTFA_FCCOBn field descriptions Field Description CCOBn The FCCOB reg...

Page 642: ...on For all command parameter fields larger than 1 byte the most significant data resides in the lowest FCCOB register number 29 3 3 6 Program Flash Protection Registers FTFA_FPROTn The FPROT registers...

Page 643: ...be protected from program and erase operations by setting the associated PROT bit In NVM Normal mode The protection can only be increased meaning that currently unprotected memory can be protected but...

Page 644: ...ry size Execute only access register Program flash execute only access bits XACCH0 XA 63 56 XACCH1 XA 55 48 XACCH2 XA 47 40 XACCH3 XA 39 32 XACCL0 XA 31 24 XACCL1 XA 23 16 XACCL2 XA 15 8 XACCL3 XA 7 0...

Page 645: ...ss The eight SACC registers allow up to 64 restricted segments of equal memory size Supervisor only access register Program flash supervisor only access bits SACCH0 SA 63 56 SACCH1 SA 55 48 SACCH2 SA...

Page 646: ...ccess control 0 Associated segment is accessible in supervisor mode only 1 Associated segment is accessible in user or supervisor mode 29 3 3 9 Flash Access Segment Size Register FTFA_FACSS The flash...

Page 647: ...s All bits in the register are read only The contents of this register are loaded during the reset sequence Address 4002_0000h base 2Bh offset 4002_002Bh Bit 7 6 5 4 3 2 1 0 Read NUMSG Write Reset x x...

Page 648: ...ram flash size 32 Program flash size 32 Program flash size 32 Program flash size 32 Program flash size 32 Program flash size 32 Program flash size 32 FPROT3 PROT0 0x0_0000 FPROT3 PROT1 FPROT3 PROT2 FP...

Page 649: ...g figure Program flash size 64 XACCL3 XA0 0x0_0000 Program flash Last program flash address Program flash size 64 XACCL3 XA1 Program flash size 64 XACCL3 XA2 Program flash size 64 XACCL3 XA3 Program f...

Page 650: ...memory module can generate interrupt requests to the MCU upon the occurrence of various flash events These interrupt events and their associated status and control bits are shown in the following tab...

Page 651: ...any flash command is running CCIF 0 NOTE While the MCU is in very low power modes VLPR VLPW VLPS the flash memory module does not accept flash commands 29 4 5 Functional Modes of Operation The flash m...

Page 652: ...tions are further discussed in Allowed Simultaneous Flash Operations 29 4 8 Flash Program and Erase All flash functions except read require the user to setup and launch a flash command through a serie...

Page 653: ...desired flash command The individual registers that make up the FCCOB data set can be written in any order 29 4 9 1 2 Launch the Command by Clearing CCIF Once all relevant command parameters have bee...

Page 654: ...inated after setting FSTAT CCIF 2 If the parameter and protection checks pass the command proceeds to execution Run time errors such as failure to erase verify may occur during the execution phase Run...

Page 655: ...no yes no yes Previous command complete no CCIF 1 yes START CCIF 1 Read FSTAT register no yes Bit Polling for Command Completion Check Figure 29 5 Generic flash command write sequence flowchart 29 4...

Page 656: ...gram flash sector 0x40 Read 1s All Blocks Verify that all program flash blocks are erased then release MCU security 0x41 Read Once IFR Read 4 bytes of a dedicated 64 byte field in the program flash 0...

Page 657: ...cure Secure MEEN 10 0x00 Read 1s Block 0x01 Read 1s Section 0x02 Program Check 0x03 Read Resource 0x06 Program Longword 0x08 Erase Flash Block 0x09 Erase Flash Sector 0x40 Read 1s All Blocks 0x41 Read...

Page 658: ...d be employed only in special cases They can be used during special diagnostic routines to gain confidence that the device is not suffering from the end of life data loss customary of flash memory dev...

Page 659: ...the FSTAT ACCERR bit and aborts the command execution if any of the following illegal conditions occur There is an unrecognized command code in the FCCOB FCMD field There is an error in a FCCOB field...

Page 660: ...am flash block Table 29 5 Margin Level Choices for Read 1s Block Read Margin Choice Margin Level Description 0x00 Use the normal read level for 1s 0x01 Apply the User margin to the normal read 1 level...

Page 661: ...tion operation completes Table 29 8 Margin Level Choices for Read 1s Section Read Margin Choice Margin Level Description 0x00 Use the normal read level for 1s 0x01 Apply the User margin to the normal...

Page 662: ...0 is set FSTAT CCIF is set after the Program Check operation completes The supplied address must be longword aligned the lowest two bits of the byte address must be 00 Byte 3 data is written to the su...

Page 663: ...ilable include program flash IFR space and the Version ID field Each resource is assigned a select code as shown in Table 29 14 Table 29 13 Read Resource Command FCCOB Requirements FCCOB Number FCCOB...

Page 664: ...ligned FSTAT ACCERR 29 4 11 5 Program Longword Command The Program Longword command programs four previously erased bytes in the program flash memory using an embedded algorithm CAUTION A flash memory...

Page 665: ...29 17 Program Longword Command Error Handling Error Condition Error Bit Command not available in current mode security FSTAT ACCERR An invalid flash address is supplied FSTAT ACCERR Flash address is...

Page 666: ...errors have been encountered during the verify operation1 FSTAT MGSTAT0 1 User margin read may be run using the Read 1s Block command to verify all bits are erased 29 4 11 7 Erase Flash Sector Command...

Page 667: ...registers are ignored except for writes to the FSTAT and FCNFG registers If an Erase Flash Sector operation effectively completes before the flash memory module detects that a suspend request has been...

Page 668: ...by clearing the ERSSUSP bit prior to clearing CCIF for the next command launch When a suspended operation is aborted the flash memory module starts the new command using the new FCCOB contents Note Ab...

Page 669: ...USP Execute Yes DONE No ERSSUSP 1 Save Erase Algo Set CCIF No Yes Start New Resume Erase No Abort User Cmd Interrupt Suspend Set SUSPACK 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR Com...

Page 670: ...EC field to the unsecure state The security byte in the flash configuration field see Flash Configuration Field Description remains unaffected by the Read 1s All Blocks command If the read fails i e a...

Page 671: ...te 3 value 8 Program Once byte 4 value index 0x10 0x13 9 Program Once byte 5 value index 0x10 0x13 10 Program Once byte 6 value index 0x10 0x13 11 Program Once byte 7 value index 0x10 0x13 After clear...

Page 672: ...0 Program Once byte 6 value index 0x10 0x13 11 Program Once byte 7 value index 0x10 0x13 After clearing CCIF to launch the Program Once command the flash memory module first verifies that the selected...

Page 673: ...tion field see Flash Configuration Field Description are erased by the Erase All Blocks command If the erase verify fails the FSTAT MGSTAT0 bit is set The CCIF flag is set after the Erase All Blocks o...

Page 674: ...it is cleared once the operation completes and the normal FSTAT error reporting is available except FPVIOL as described in Erase All Blocks Command 29 4 11 12 Verify Backdoor Access Key Command The Ve...

Page 675: ...the Verify Backdoor Access Key command fails with an access error The CCIF flag is set after the Verify Backdoor Access Key operation completes Table 29 32 Verify Backdoor Access Key Command Error Ha...

Page 676: ...ecute only Segments Read Margin Choice Margin Level Description 0x00 Use the normal read level for 1s 0x01 Apply the User margin to the normal read 1 level 0x02 Apply the Factory margin to the normal...

Page 677: ...e impacted by the execution of the Erase All Execute only Segments command Table 29 37 Erase All Execute only Segments Command Error Handling Error Condition Error Bit Command not available in current...

Page 678: ...vailable and that the region of the program flash containing the flash configuration field is unprotected If the flash security byte is successfully programmed its new value takes affect after the nex...

Page 679: ...e been correctly matched the chip is unsecured by changing the FSEC SEC bits A successful execution of the Verify Backdoor Access Key command changes the security in the FSEC register only It does not...

Page 680: ...s marked by setting CCIF which enables flash user commands If a reset occurs while any flash command is in progress that command is immediately aborted The state of the word being programmed or the se...

Page 681: ...rface that enables In System Programming ISP of flash memory contents in a 32 bit general purpose microcontroller Memory contents can be read erased programmed from an external source in a format that...

Page 682: ...he following features Serial interface that is compatible with a subset of the SPI format Ability to read erase and program flash memory Ability to reset the microcontroller allowing it to boot from t...

Page 683: ...e contents of the flash memory The serial data out from the EzPort is tri stated unless data is being driven This allows the signal to be shared among several different EzPort or compatible devices in...

Page 684: ...EZP_D is the serial data in for data transfers EZP_D is registered on the rising edge of EZP_CK All commands addresses and data are shifted in most significant bit first When the EzPort is driving out...

Page 685: ...ction size Total number of data bytes programmed must be a multiple of 4 5 Bulk Erase is accepted when the BEDIS status field is not set 6 The flash will be in NVM Special mode restricting the type of...

Page 686: ...R 7 0 EZP_CK EZP_CS EZP_D EZP_Q Figure 30 4 Read Status Register command sequence The Read Status Register RDSR command returns the contents of the EzPort status register Table 30 3 EzPort status regi...

Page 687: ...operations associated with the command 0 Disables the following write command 1 Enables the following write command 2 BEDIS Bulk erase disable Indicates whether bulk erase BE is disabled 0 BE is enab...

Page 688: ...ata the EzPort clock EZP_CK must run at the internal system clock divided by eight or slower This command is not accepted if the WEF WIP or FS field in the EzPort status register is set 30 3 1 5 Read...

Page 689: ...moving the data into flash using the Program Longword command For this reason the number of bytes to be programmed must be a multiple of 4 and up to one flash section can be programmed at a time For...

Page 690: ...ster 30 3 1 8 Bulk Erase CMD 7 0 0xC7 EZP_CK EZP_CS EZP_D EZP_Q Figure 30 9 Bulk Erase command sequence The Bulk Erase BE command erases the entire contents of flash memory ignoring any protected sect...

Page 691: ...the user to write to the flash common command object registers and execute any command allowed by the flash NOTE When security is enabled the flash is configured in NVM Special mode restricting the c...

Page 692: ...ntroller or slower Attempts to read greater than 12 bytes of data returns unknown data This command is not accepted if the WEF WIP or FS fields in the EzPort status register are 1 30 4 Flash memory ma...

Page 693: ...ing diagrams showing the interaction of signals in supported bus operations 31 1 1 Definition The FlexBus multifunction external bus interface controller is a hardware module that Provides memory expa...

Page 694: ...2 bit address is driven on the first clock of a bus cycle address phase After the first clock the data is driven on the bus data phase During the data phase the address is driven on the pins not used...

Page 695: ...the port size FB_TSIZ1 FB_TSIZ0 behave as follows If bursting is used FB_TSIZ1 FB_TSIZ0 are driven to the transfer size If bursting is inhibited FB_TSIZ1 FB_TSIZ0 first show the entire transfer size a...

Page 696: ...y or peripheral is asserted The CSPMCR register controls muxing of FB_TA with other signals When the CSPMCR register does not allow fb_ta control auto acknowledge must be used CSCR AA 1 b1 otherwise t...

Page 697: ...defined 31 3 3 699 4000_C03C Chip Select Address Register FB_CSAR5 32 R W 0000_0000h 31 3 1 697 4000_C040 Chip Select Mask Register FB_CSMR5 32 R W 0000_0000h 31 3 2 698 4000_C044 Chip Select Control...

Page 698: ...ddress bits 0 The corresponding address bit in CSAR is used in the chip select decode 1 The corresponding address bit in CSAR is a don t care in the chip select decode 15 9 Reserved This field is rese...

Page 699: ...al chip select FB_CS0 the CSCR0 reset values differ from the other CSCRs The reset value of CSCR0 is as follows Bits 31 24 are 0b Bit 23 3 are chip dependent Bits 3 0 are 0b See the chip configuration...

Page 700: ...address is asserted 10 Assert FB_CSn on the third rising clock edge after the address is asserted 11 Assert FB_CSn on the fourth rising clock edge after the address is asserted default for FB_CS0 19 1...

Page 701: ...select and determines where data is driven during write cycles and where data is sampled during read cycles 00 32 bit port size Valid data is sampled and driven on FB_D 31 0 01 8 bit port size Valid d...

Page 702: ...hen you do any of the following Write to a reserved address Write to a reserved field in this register or Access this register using a size other than 32 bits Address 4000_C000h base 60h offset 4000_C...

Page 703: ...not 0000b you must write 1b to the CSCR AA bit Otherwise the bus hangs during a transfer 0000 FB_TA 0001 FB_CS3 You must also write 1b to CSCR AA 0010 FB_BE_7_0 You must also write 1b to CSCR AA Any o...

Page 704: ...erating a FlexBus bus cycle as defined in the appropriate CSCR If CSMR WP is set and a write access is performed FlexBus terminates the internal bus cycle with a bus error does not assert a chip selec...

Page 705: ...FB_BEn Attribute signals FB_TBST FB_TSIZ1 FB_TSIZ0 31 4 7 Signal transitions These signals change on the rising edge of the FlexBus clock FB_CLK Address Write data FB_TS FB_ALE FB_CSn All attribute si...

Page 706: ...alues Driven with address values FB_D 31 24 FB_D 23 16 FB_D 15 8 FB_D 7 0 FB_BE_7_0 FB_BE_15_8 FB_BE_23_16 FB_BE_31_24 In BLS 0 mode the byte enables always correspond to the same byte lanes regardles...

Page 707: ...ed address and data bus FB_AD31 FB_AD0 FlexBus always drives the full 32 bit address on the first clock of a bus cycle During the data phase the FB_AD31 FB_AD0 lines used for data are determined by th...

Page 708: ...ddress phase Address Data phase Address Data 8 bit Address phase Address Data phase Address Data 31 4 10 Data transfer states Basic data transfers occur in four clocks or states See Figure 31 4 and Fi...

Page 709: ...pheral negates FB_TA and FlexBus negates FB_CSn after the rising edge of FB_CLK at the end of S2 Read FlexBus latches the data on the rising clock edge entering S2 The external memory or peripheral ca...

Page 710: ...t The read cycle timing diagram is shown in the following figure Note FB_TA does not have to be driven by the external device for internally terminated bus cycles Note The processor drives the data li...

Page 711: ...indicates a 32 16 8 bit address data bus or custom size FB_AD Y 0 indicates a 32 16 8 bit address bus or custom size Figure 31 4 Basic Read Bus Cycle 31 4 11 2 Basic Write Bus Cycle During a write cy...

Page 712: ...the appropriate slave device 1 Negate transfer start 2 Assert FB_CSn 3 Drive data 1 FlexBus asserts internal FB_TA auto acknowledge internal termination FlexBus Figure 31 5 Write Cycle Flowchart The...

Page 713: ...AD Y 0 FB_AD 31 X Figure 31 6 Basic Write Bus Cycle 31 4 11 3 Bus Cycle Sizing This section shows timing diagrams for various port size scenarios 31 4 11 3 1 Bus Cycle Sizing Byte Transfer 8 bit Devic...

Page 714: ...ed asserted Address Address Data 7 0 TSIZ 01 AA 1 AA 0 AA 1 AA 0 FB_CLK FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE BWEn FB_TA FB_TSIZ 1 0 BEM 1 BEM 0 Single Byte Read Transfer TIP Read8b svg FB_AD 23 0 FB...

Page 715: ...ustrates the basic word read transfer to a 16 bit device with no wait states The address is driven on the full FB_AD 31 8 bus in the first clock The device tristates FB_AD 31 16 on the second clock an...

Page 716: ...e Word Read Transfer TIP Read16b svg Data 15 0 FB_AD 15 0 FB_AD 31 16 Figure 31 9 Single Word Read Transfer The following figure shows the similar configuration for a write transfer The data is driven...

Page 717: ...S1 S2 S3 S0 Write16b svg TIP FB_AD 15 0 FB_AD 31 16 Data 15 0 Figure 31 10 Single Word Write Transfer 31 4 11 3 3 Bus Cycle Sizing Longword Transfer 32 bit Device No Wait States The following figure...

Page 718: ...BEM 1 BEM 0 S0 S1 S2 S3 S0 Longword Read Transfer TIP S0 S1 S2 S3 S0 Read32b svg FB_AD 23 0 FB_AD 31 0 Data 31 0 Figure 31 11 Longword Read Transfer The following figure illustrates the longword write...

Page 719: ...e bus cycle to provide additional address setup address hold and time for a device to provide or latch data 31 4 11 4 1 Wait States Wait states can be inserted before each beat of a transfer by progra...

Page 720: ...EM 0 S0 S1 S2 S3 S0 TIP Basic Read Bus Cycle S0 S1 S2 S3 S0 basicRead svg FB_AD 31 X indicates a 32 16 8 bit address data bus or custom size FB_AD Y 0 indicates a 32 16 8 bit address bus or custom siz...

Page 721: ...s bus or custom size FB_AD Y 0 FB_AD 31 X Figure 31 14 Basic Write Bus Cycle No Wait States If wait states are used the S1 state repeats continuously until the chip select auto acknowledge unit assert...

Page 722: ...State Read Bus Cycle 1 Wait State S0 S1 S2 S3 S0 WS Read1WS svg FB_AD Y 0 FB_AD 31 X FB_AD 31 X indicates a 32 16 8 bit address data bus or custom size FB_AD Y 0 indicates a 32 16 8 bit address bus o...

Page 723: ...X Figure 31 16 Write Bus Cycle One Wait State 31 4 11 4 2 Address Setup and Hold The timing of the assertion and negation of the chip selects byte selects and output enable can be programmed on a chip...

Page 724: ...ycle with 2 Clock Address Setup No Wait States Read2AS svg EXTS 0 EXTS 1 FB_AD Y 0 FB_AD 31 X FB_AD 31 X indicates a 32 16 8 bit address data bus or custom size FB_AD Y 0 indicates a 32 16 8 bit addre...

Page 725: ...indicates a 32 16 8 bit address bus or custom size Figure 31 18 Write Bus Cycle with Two Clock Address Setup No Wait States In addition to address setup a programmable address hold option for each ch...

Page 726: ...n FB_TA FB_TSIZ 1 0 BEM 1 BEM 0 S0 S1 AH S3 S0 S2 Address Hold S0 S1 AH S3 S0 S2 Read Bus Cycle with RDAH 01 No Wait States Read2AH svg Figure 31 19 Read Cycle with Two Clock Address Hold No Wait Stat...

Page 727: ...S0 S1 AH S3 S0 S2 Write Bus Cycle with WRAH 01 No Wait States Write2AH svg TIP Figure 31 20 Write Cycle with Two Clock Address Hold No Wait States The following figure shows a bus cycle using address...

Page 728: ...initiate burst cycles if its transfer size exceeds the port size of the selected destination The initiation of a burst cycle is encoded on the transfer size pins FB_TSIZ 1 0 For burst transfers to sm...

Page 729: ...10b 16 bits 2 00b 32 bits 4 11b 16 bytes 16 1Xb 16 bit 00b 32 bits 2 11b 16 bytes 8 00b 32 bit 11b line 4 The FlexBus can support X 1 1 1 burst cycles to maximize system performance where X is the pr...

Page 730: ...ss during the data phase Address Address Data Data Data Data Add 1 Add 2 Add 3 FB_CLK FB_TBST TSIZ 00 AA 1 AA 0 FB_RW FB_TS FB_ALE FB_OEn FB_BE BWEn FB_TA FB_TSIZ 1 0 FB_CSn AA 1 AA 0 32 bit Read Burs...

Page 731: ...b one wait state is added Otherwise the programmed number of wait states are used Address Address Data Add 1 Add 2 Add 3 FB_CLK FB_TBST TSIZ 00 AA 1 AA 0 FB_RW FB_TS FB_ALE FB_OEn FB_BE BWEn FB_TA FB_...

Page 732: ...dd 1 Data Add 2 Data Add 3 Data FB_RW FB_TS FB_ALE FB_ALE FB_CSn FB_OE FB_BE BWEn FB_TA FB_TBST FB_TSIZ 1 0 AA 1 AA 0 AA 1 AA 0 TSIZ 00 TSIZ 01 32 bit read burst inhibited to 8 bit port no wait states...

Page 733: ...1 S0 AS S3 S2 S1 S0 AS S3 S2 S1 S0 AS S3 S0 AS Figure 31 24 32 bit write burst inhibited to 8 bit port no wait states 31 4 12 7 32 bit read burst from 8 bit port 3 2 2 2 one wait state The following f...

Page 734: ...S SWS S2 S3 S4 Wait State Read32bBurst1WS svg WS SWS WS SWS S0 Dead State AA 1 AA 0 S0 WS S2 S2 S2 S1 WS SWS S2 S3 S4 WS SWS WS SWS S0 AA 0 WS Wait State SWS Secondary Wait State Figure 31 25 32 bit r...

Page 735: ...AA 0 Write32bBurst1WS svg Figure 31 26 32 bit write burst to 8 bit port 3 2 2 2 one wait state 31 4 12 9 32 bit read burst from 8 bit port 3 1 1 1 address setup and hold If address setup and hold are...

Page 736: ...FB_CSn 32 bit Read Burst from 8 bit port 3 1 1 1 with Address Setup and Hold BEM 1 BEM 0 S0 AS S2 S2 S2 S1 S2 AH S3 Address Setup S0 Address Hold If AA 1 the address increments If AA 0 the address st...

Page 737: ...burst to 8 bit port 3 1 1 1 address setup and hold 31 4 13 Extended Transfer Start Address Latch Enable The FB_TS FB_ALE signal indicates that a bus transaction has begun and the address and attribut...

Page 738: ...e 31 4 14 Bus errors These types of accesses cause a transfer to terminate with a bus error A write to a write protected address range An access whose address is not in a range covered by a chip selec...

Page 739: ...ip select Before using any other chip select to take it out of global chip select mode you must initialize CS0 To initialize a chip select 1 Write to the associated CSAR 2 Write to the associated CSCR...

Page 740: ...Initialization Application Information K22F Sub Family Reference Manual Rev 4 08 2016 740 NXP Semiconductors...

Page 741: ...CRC module include Hardware CRC generator circuit using a 16 bit or 32 bit programmable shift register Programmable initial seed value and polynomial Option to transpose input data or output data the...

Page 742: ...op Any CRC calculation in progress stops when the MCU enters a low power mode that disables the module clock It resumes after the clock is enabled or via the system reset for exiting the low power mod...

Page 743: ...4 3 2 1 0 R HU HL LU LL W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_DATA field descriptions Field Description 31 24 HU CRC High Upper Byte In 16 bit CRC mode CTRL TCRC...

Page 744: ...ynominal Half word Writable and readable in 32 bit CRC mode CTRL TCRC is 1 This field is not writable in 16 bit CRC mode CTRL TCRC is 0 LOW Low Polynominal Half word Writable and readable in both 32 b...

Page 745: ...are transposed 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 FXOR Complement Read Of CRC Data Register Some CRC protocols require the final checksu...

Page 746: ...CRC To compute a 16 bit CRC 1 Clear CRC_CTRL TCRC to enable 16 bit CRC mode 2 Program the transpose and complement options in the CTRL register as required for the CRC calculation See Transpose featur...

Page 747: ...nd CRC result complement for details 32 3 3 Transpose feature By default the transpose feature is not enabled However some CRC standards require the input data and or the final checksum to be transpos...

Page 748: ...32 2 Transpose type 01 3 CTRL TOT or CTRL TOTR is 10 Both bits in bytes and bytes are transposed reg 31 0 becomes reg 0 7 reg 8 15 reg 16 23 reg 24 31 31 31 0 0 Figure 32 3 Transpose type 10 4 CTRL T...

Page 749: ...ter transposition resides in the CRC HU HL fields The user software must account for this situation when reading the 16 bit CRC result so reading 32 bits is preferred 32 3 4 CRC result complement When...

Page 750: ...Functional description K22F Sub Family Reference Manual Rev 4 08 2016 750 NXP Semiconductors...

Page 751: ...the means of generating the required entropy needed to create random data The random words generated by RNGA are loaded into an output register OR RNGA is designed to generate an error interrupt if n...

Page 752: ...of entropy can be used along with RNGA to generate the seed to the pseudorandom algorithm The more random sources combined to create the seed the better The following is a list of sources that can be...

Page 753: ..._9008 RNGA Entropy Register RNG_ER 32 W always reads 0 0000_0000h 33 3 3 757 4002_900C RNGA Output Register RNG_OR 32 R 0000_0000h 33 3 4 757 33 3 1 RNGA Control Register RNG_CR Controls the operation...

Page 754: ...error interrupt to the interrupt controller when an OR underflow condition occurs An OR underflow condition occurs when you read OR RANDOUT and SR OREG_LVL 0 See the Output Register OR description 0 N...

Page 755: ...ue 0 23 16 OREG_SIZE Output Register Size Indicates the size of the Output OR register in terms of the number of 32 bit random data words it can hold 1 One word this value is fixed 15 8 OREG_LVL Outpu...

Page 756: ...flow condition has occurred since you last read this register SR or RNGA was reset regardless of whether the error interrupt is masked CR INTM An OR underflow condition occurs when you read OR RANDOUT...

Page 757: ...seed its pseudorandom algorithm NOTE Specifying a value for this field is optional but recommended You can write to this field at any time during operation 33 3 4 RNGA Output Register RNG_OR Stores a...

Page 758: ...nal control signals Figure 33 1 RNGA block diagram 33 4 1 Output OR register The Output OR register provides temporary storage for random data generated by the core engine control logic The Status SR...

Page 759: ...es a new random data word If SR OREG_LVL 0 then the control block loads the new random data into OR and set SR OREG_LVL 1 else the new data is discarded 33 4 2 2 Core engine The core engine block cont...

Page 760: ...For application information see Overview Initialization application information K22F Sub Family Reference Manual Rev 4 08 2016 760 NXP Semiconductors...

Page 761: ...evice 34 1 1 Features Following are the features of the ADC module Linear successive approximation algorithm with up to 16 bit resolution Up to four pairs of differential and 24 single ended external...

Page 762: ...utput the clock Selectable hardware conversion trigger with hardware channel select Automatic compare with interrupt for less than greater than or equal to within range or out of range programmable va...

Page 763: ...TempP V REFH VALTH VREFL VALTL AIEN COCO trigger DIFF MODE CLPx PG MG PG MG CLPx Calibration OFS CALF CAL SC3 CV1 ACFGT ACREN D AVGE AVGS ADCOFS V REFSH V REFSL SC2 CFG1 CFG2 Conversion trigger contr...

Page 764: ...V1 ACFGT ACREN D AVGE AVGS ADCOFS V REFSH V REFSL SC2 CFG1 CFG2 Conversion trigger control Clock divide Control sequencer Bus clock SAR converter Compare logic Offset subtractor Averager Formatting A...

Page 765: ...External filtering may be necessary to ensure clean VDDA for good results 34 2 2 Analog Ground VSSA The ADC analog portion uses VSSA as its ground connection In some packages VSSA is connected intern...

Page 766: ...s DADPx and DADMx referenced to each other to provide the most accurate analog to digital readings A differential input is selected for conversion through SC1 ADCH when SC1n DIFF is high All DADPx inp...

Page 767: ...Side General Calibration Value Register ADC1_CLP1 32 R W 0000_0040h 34 3 16 785 4002_704C ADC Plus Side General Calibration Value Register ADC1_CLP0 32 R W 0000_0020h 34 3 17 785 4002_7054 ADC Minus...

Page 768: ...DC0_CLP3 32 R W 0000_0100h 34 3 14 784 4003_B044 ADC Plus Side General Calibration Value Register ADC0_CLP2 32 R W 0000_0080h 34 3 15 784 4003_B048 ADC Plus Side General Calibration Value Register ADC...

Page 769: ...Writing SC1A while SC1A is actively controlling a conversion aborts the current conversion In Software Trigger mode when SC2 ADTRG 0 writes to SC1A subsequently initiate a new conversion if SC1 ADCH...

Page 770: ...ut channel select Selects one of the input channels The input channel decode depends on the value of DIFF DAD0 DAD3 are associated with the input pin pairs DADPx and DADMx NOTE Some of the input chann...

Page 771: ...DIFF 0 AD19 is selected as input when DIFF 1 it is reserved 10100 When DIFF 0 AD20 is selected as input when DIFF 1 it is reserved 10101 When DIFF 0 AD21 is selected as input when DIFF 1 it is reserv...

Page 772: ...expense of maximum clock speed 6 5 ADIV Clock Divide Select Selects the divide ratio used by the ADC to generate the internal clock ADCK 00 The divide ratio is 1 and the clock rate is input clock 01 T...

Page 773: ...ot required to be active prior to conversion start When it is selected and it is not active prior to a conversion start when CFG2 ADACKEN 0 the asynchronous clock is activated at the start of a conver...

Page 774: ...Speed Configuration Configures the ADC for very high speed operation The conversion sequence is altered with 2 ADCK cycles added to the conversion time to allow higher speed conversion clocks 0 Norma...

Page 775: ...ent 12 bit single ended 0 0 0 0 D D D D D D D D D D D D Unsigned right justified 11 bit differential S S S S S S D D D D D D D D D D Sign extended 2 s complement 10 bit single ended 0 0 0 0 0 0 D D D...

Page 776: ...that are related to the ADC mode of operation The compare value 2 register CV2 is used only when the compare range function is enabled that is SC2 ACREN 1 Address Base address 18h offset 4d i where i...

Page 777: ...0 ADCx_SC2 field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 ADACT Conversion Active Indicates that a conversion...

Page 778: ...unctionality based on the values placed in CV1 and CV2 3 ACREN Compare Function Range Enable Configures the compare function to check if the conversion result of the input being monitored is either be...

Page 779: ...when the calibration sequence is completed CALF must be checked to determine the result of the calibration sequence Once started the calibration routine cannot be interrupted by writes to the ADC regi...

Page 780: ...ection Register OFS contains the user selected or calibration generated offset error correction value This register is a 2 s complement left justified 16 bit value The value in OFS is subtracted from...

Page 781: ...2 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ADCx_PG field descriptions Field Description 31 16 Reserved This field is reserved This read...

Page 782: ...P2 7 0 CLP3 8 0 CLP4 9 0 CLPS 5 0 and CLPD 5 0 CLPx are automatically set when the self calibration sequence is done that is CAL is cleared If these registers are written by the user after calibration...

Page 783: ...0 CLPS Calibration Value Calibration Value 34 3 13 ADC Plus Side General Calibration Value Register ADCx_CLP4 For more information see CLPD register description Address Base address 3Ch offset Bit 31...

Page 784: ...lue 0 CLP3 Calibration Value Calibration Value 34 3 15 ADC Plus Side General Calibration Value Register ADCx_CLP2 For more information see CLPD register description Address Base address 44h offset Bit...

Page 785: ...0 CLP1 Calibration Value Calibration Value 34 3 17 ADC Plus Side General Calibration Value Register ADCx_CLP0 For more information see CLPD register description Address Base address 4Ch offset Bit 31...

Page 786: ...9 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CLMD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 ADCx_CLMD field descriptions Field Description 31 6 Reserved This fiel...

Page 787: ...d only field is reserved and always has the value 0 CLM4 Calibration Value Calibration Value 34 3 21 ADC Minus Side General Calibration Value Register ADCx_CLM3 For more information see CLMD register...

Page 788: ...lue 0 CLM2 Calibration Value Calibration Value 34 3 23 ADC Minus Side General Calibration Value Register ADCx_CLM1 For more information see CLMD register description Address Base address 68h offset Bi...

Page 789: ...k output enable is disabled or CFG2 ADACKEN 0 the module is in its lowest power state The ADC can perform an analog to digital conversion on any of the software selectable channels All modes perform c...

Page 790: ...This clock is generated from a clock source within the ADC module When the ADACK clock source is selected it is not required to be active prior to conversion start When it is selected and it is not ac...

Page 791: ...is available and hardware trigger is enabled that is SC2 ADTRG 1 a conversion is initiated on the rising edge of ADHWT after a hardware trigger select event that is ADHWTSn has occurred If a conversi...

Page 792: ...ed by CFG1 MODE and SC1n DIFF as shown in the description of CFG1 MODE Conversions can be initiated by a software or hardware trigger In addition the ADC module can be configured for Low power operati...

Page 793: ...riggered operation conversions begin after SC1A is written In hardware triggered operation conversions begin after a hardware trigger If continuous conversions are also enabled a new set of conversion...

Page 794: ...mal Stop mode with ADACK or Alternate Clock Sources not enabled When a conversion is aborted the contents of the data registers Rn are not altered The data registers continue to be the values transfer...

Page 795: ...ed configuration that is CFG2 ADHSC The frequency of the conversion clock that is fADCK CFG2 ADHSC is used to configure a higher clock input frequency This will allow faster overall conversion times T...

Page 796: ...me adder SFCAdder 1 x 0x 10 3 ADCK cycles 5 bus clock cycles 1 1 11 3 ADCK cycles 5 bus clock cycles1 1 0 11 5 s 3 ADCK cycles 5 bus clock cycles 0 x 0x 10 5 ADCK cycles 5 bus clock cycles 0 1 11 5 AD...

Page 797: ...2 ADCK cycles Note The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications 34 4 4 6 Conversion time examples The following examples use the Equation 1 on page 796...

Page 798: ...nfiguration A configuration for long ADC conversion is 16 bit differential mode with the bus clock selected as the input clock source The input clock divide by 8 ratio selected Bus frequency of 8 MHz...

Page 799: ...ADCK cycles 5 bus clock cycles AverageNum 1 BCT 17 ADCK cycles LSTAdder 0 ADCK cycles HSCAdder 2 The resulting conversion time is generated using the parameters listed in in the preceding table There...

Page 800: ...r the input is sampled and converted the compare values in CV1 and CV2 are used as described in the following table There are six Compare modes as shown in the following table Table 34 11 Compare mode...

Page 801: ...el while the MCU is in Wait or Normal Stop modes The ADC interrupt wakes the MCU when the compare condition is met 34 4 6 Calibration function The ADC contains a self calibration function that is requ...

Page 802: ...o clear and SC3 CALF to set At the end of a calibration sequence SC1n COCO will be set SC1n AIEN can be used to allow an interrupt to occur at the end of a calibration sequence At the end of the calib...

Page 803: ...t mode of operation The formatting of the OFS is different from the data result register Rn to preserve the resolution of the calibration value regardless of the conversion mode selected Lower order b...

Page 804: ...the user defined offset For applications that may change the offset repeatedly during operation store the initial offset calibration value in flash so it can be recovered and added to any user offset...

Page 805: ...urces are available as conversion clock sources while in Wait mode The use of ALTCLK as the conversion clock source in Wait is dependent on the definition of ALTCLK for this MCU See the Chip Configura...

Page 806: ...terrupt to wake the MCU from Normal Stop mode if the respective ADC interrupt is enabled that is when SC1n AIEN 1 The result register Rn will contain the data from the first completed conversion that...

Page 807: ...to complete conversions an initialization procedure must be performed A typical sequence is 1 Calibrate the ADC by following the calibration instructions in Calibration function 2 Update CFG to selec...

Page 808: ...7 ADACT 0 Flag indicates if a conversion is in progress Bit 6 ADTRG 0 Software trigger selected Bit 5 ACFE 0 Compare function disabled Bit 4 ACFGT 0 Not used in this example Bit 3 ACREN 0 Compare rang...

Page 809: ...embedded control applications requiring an ADC For guidance on selecting optimum external component values and converter parameters see AN4373 Cookbook for SAR ADC Measurements 34 6 1 External pins a...

Page 810: ...d reference The two pairs are external VREFH and VREFL and alternate VALTH and VALTL These voltage references are selected using SC2 REFSEL The alternate voltage reference pair VALTH and VALTL may sel...

Page 811: ...ll between VREFH and VREFL If the input is equal to or exceeds VREFH the converter circuit converts the signal to 0xFFF which is full scale 12 bit representation 0x3FF which is full scale 10 bit repre...

Page 812: ...10 bit mode 12 in 12 bit mode or 16 in 16 bit mode 34 6 2 3 Noise induced errors System noise that occurs during the sample or conversion process can affect the accuracy of the conversion The ADC accu...

Page 813: ...f a 1 LSB one time error Reduce the effect of synchronous noise by operating off the asynchronous clock that is ADACK and averaging Noise that is synchronous to ADCK cannot be averaged out 34 6 2 4 Co...

Page 814: ...Differential non linearity DNL This error is defined as the worst case difference between the actual code width and the ideal code width for all conversions Integral non linearity INL This error is d...

Page 815: ...onicity occurs when except for code jitter the converter converts to a lower code for a higher input voltage Missing codes Missing codes are those values never converted for any input value In 8 bit o...

Page 816: ...Application information K22F Sub Family Reference Manual Rev 4 08 2016 816 NXP Semiconductors...

Page 817: ...he full range of the supply voltage The 6 bit DAC is 64 tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed The 64 tap resistor...

Page 818: ...unctions Two software selectable performance levels Shorter propagation delay at the expense of higher power Low power with longer propagation delay DMA transfer support A comparison event can be sele...

Page 819: ...annel mux Operational over the entire supply range 35 1 4 CMP DAC and ANMUX diagram The following figure shows the block diagram for the High Speed Comparator DAC and ANMUX modules Chapter 35 Comparat...

Page 820: ...put 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP INM Sample input Figure 35 1 CMP DAC and ANMUX block diagram 35 1 5 CMP block diag...

Page 821: ...CR1 WE 1 the comparator output will be sampled on every bus clock when WINDOW 1 to generate COUTA Sampling does NOT occur when WINDOW 0 The Filter block is bypassed when not in use The Filter block ac...

Page 822: ...7_3005 MUX Control Register CMP0_MUXCR 8 R W 00h 35 2 6 827 4007_3008 CMP Control Register 0 CMP1_CR0 8 R W 00h 35 2 1 822 4007_3009 CMP Control Register 1 CMP1_CR1 8 R W 00h 35 2 2 823 4007_300A CMP...

Page 823: ...rved This read only field is reserved and always has the value 0 HYSTCTR Comparator hard block hysteresis control Defines the programmable hysteresis level The hysteresis values associated with each l...

Page 824: ...agation delay and lower current consumption 1 High Speed HS Comparison mode selected In this mode CMP has faster output propagation delay and higher current consumption 3 INV Comparator INVERT Allows...

Page 825: ...his field has no effect when CR1 SE 1 In that case the external SAMPLE signal is used to determine the sampling period 35 2 4 CMP Status and Control Register CMPx_SCR Address Base address 3h offset Bi...

Page 826: ...Rising edge on COUT has occurred 1 CFF Analog Comparator Flag Falling Detects a falling edge on COUT when set during normal operation CFF is cleared by writing 1 to it During Stop modes CFF is edge s...

Page 827: ...ed Bit can be programmed to zero only This field is reserved 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 3 PSEL Plus Input Mux Control Determines wh...

Page 828: ...module to assert an interrupt to the processor SCR CFF is set on a falling edge and SCR CFR is set on rising edge of the comparator output The optionally filtered CMPO can be read directly through SCR...

Page 829: ...mode s 3A 3B 3B 1 0 0 0x01 0x00 4A 1 0 1 0x01 X Sampled Filtered mode See the Sampled Filtered mode s 4A 4B 4B 1 0 0 0x01 0x00 5A 1 1 0 0x00 X Windowed mode Comparator output is sampled on every risi...

Page 830: ...3 1 1 Disabled mode 1 In Disabled mode the analog comparator is non functional and consumes no power CMPO is 0 in this mode 35 3 1 2 Continuous mode s 2A 2B IRQ Internal bus INP INM FILTER_CNT INV CO...

Page 831: ...iltered mode s 3A 3B IRQ INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD COUTA 1 WE 0 SE 1 CGMUX COS FILT_PER 1 0 FILT_PER COS 0x01 IER F CFR F WINDOW SAMPLE 1 0 EN PMODE HYSTCTR 1 0 divided bus c...

Page 832: ...PO bus clock Internal bus Polarity select Window control Filter block Interrupt control To other SOC functions Clock prescaler Figure 35 5 Sampled Non Filtered 3B sampling interval internally derived...

Page 833: ...OW SAMPLE 1 0 EN PMODE HYSTCTR 1 0 divided bus clock CMPO 0x01 Internal bus Polarity select Window control Filter block Interrupt control Clock prescaler To other SOC functions Figure 35 6 Sampled Fil...

Page 834: ...is that now CR0 FILTER_CNT 1 which activates filter operation 35 3 1 5 Windowed mode s 5A 5B The following figure illustrates comparator operation in the Windowed mode ignoring latency of the analog...

Page 835: ...clock COS 0x01 IER F CFR F WINDOW SAMPLE Polarity select Window control Filter block Interrupt control divided bus clock Clock prescaler CMPO Internal bus To other SOC functions Figure 35 9 Windowed...

Page 836: ...lication Depending upon the sampling rate and window placement COUT may not see zero crossing events detected by the analog comparator Sampling period and or window placement must be carefully conside...

Page 837: ...latched value is held when WINDOW 0 IRQ EN PMODE HYSCTR 1 0 INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD COUTA 0 1 WE 1 0 SE 0 CGMUX COS FILT_PER 0 1 FILT_PER bus clock COS IER F CFR F WINDOW...

Page 838: ...d The CMP output pin is latched and does not reflect the compare output state The positive and negative input voltage can be supplied from external pins or the DAC output The MCU can be brought out of...

Page 839: ...ring and the amount of filtering is dependent on user requirements Filtering can become more useful in the absence of an external hysteresis circuit Without external hysteresis high frequency oscillat...

Page 840: ...TER_CNT The values of FPR FILT_PER or SAMPLE period and CR0 FILTER_CNT must also be traded off against the desire for minimal latency in recognizing actual comparator output transitions The probabilit...

Page 841: ...en Then SCR IER and SCR CFR are set The interrupt request is asserted SCR IEF and SCR CFF are set The interrupt request is asserted SCR IER and SCR CFR are cleared for a rising edge interrupt The inte...

Page 842: ...details 35 6 CMP Asynchronous DMA support The comparator can remain functional in STOP modes When DMA support is enabled by setting SCR DMAEN and the interrupt is enabled by setting SCR IER SCR IEF or...

Page 843: ...nd Vin2 The module can be powered down or disabled when not in use When in Disabled mode DACO is connected to the analog ground VOSEL 5 0 DACO MUX MUX DACEN Vin VRSEL Vin1 Vin2 Figure 35 12 6 bit DAC...

Page 844: ...ut corresponding to the chip wide peripheral reset 35 10 DAC clocks This module has a single clock input the bus clock 35 11 DAC interrupts This module has no interrupts DAC resets K22F Sub Family Ref...

Page 845: ...comparator op amps or ADC 36 2 Features The features of the DAC module include On chip programmable reference generator output The voltage output range is from 1 4096 Vin to Vin and the step is 1 409...

Page 846: ...N DACBFRPBF DACBBIEN OR dac_interrupt DACTRGSE LPEN DACRFS DACREF_1 Vin Vo Data Buffer Figure 36 1 DAC block diagram 36 4 Memory map register definition The DAC has registers to control analog compara...

Page 847: ...4 2 849 4002_8012 DAC Data Low Register DAC1_DAT9L 8 R W 00h 36 4 1 849 4002_8013 DAC Data High Register DAC1_DAT9H 8 R W 00h 36 4 2 849 4002_8014 DAC Data Low Register DAC1_DAT10L 8 R W 00h 36 4 1 8...

Page 848: ...egister DAC0_DAT8H 8 R W 00h 36 4 2 849 4003_F012 DAC Data Low Register DAC0_DAT9L 8 R W 00h 36 4 1 849 4003_F013 DAC Data High Register DAC0_DAT9H 8 R W 00h 36 4 2 849 4003_F014 DAC Data Low Register...

Page 849: ...ata High Register DACx_DATnH Address Base address 1h offset 2d i where i 0d to 15d Bit 7 6 5 4 3 2 1 0 Read 0 DATA1 Write Reset 0 0 0 0 0 0 0 0 DACx_DATnH field descriptions Field Description 7 4 Rese...

Page 850: ...rmark level 1 The DAC buffer read pointer has reached the watermark level 1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag In FIFO mode it is FIFO nearly empty flag It is set when only one data r...

Page 851: ...are trigger is selected and buffer is enabled writing 1 to this field will advance the buffer read pointer once 0 The DAC soft trigger is not valid 1 The DAC soft trigger is valid 3 LPEN DAC Low Power...

Page 852: ...er limit DACBUP SR DACBFWMF will be set This allows user configuration of the watermark interrupt In FIFO mode it is FIFO watermark select field 00 In normal mode 1 word In FIFO mode 2 or less than 2...

Page 853: ...ritable and user can configure it to the same address to reset FIFO as empty 36 5 Functional description The 12 bit DAC module can select one of the two reference inputs DACREF_1 and DACREF_2 as the D...

Page 854: ...ode The buffer works as a circular buffer The read pointer increases by one every time the trigger occurs When the read pointer reaches the upper limit it goes to 0 directly in the next trigger event...

Page 855: ...to DACDATx will return the DATA addressed by the access address to the data buffer and both write pointer and read pointer in FIFO mode will NOT be changed by read access FIFO write can be happened w...

Page 856: ...rmal Stop mode and the output voltage will hold the value before stop In low power stop modes the DAC is fully shut down NOTE The assignment of module modes to core modes is chip specific For module t...

Page 857: ...be trimmed in 0 5 mV steps The VREF can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC DAC or CMP T...

Page 858: ...Cs and DACs Refer to the chip configuration details for a description of these options The reference voltage signal is output on a dedicated output pin when the VREF is enabled The Voltage Reference o...

Page 859: ...ode of operation Having the VREF regulator enabled does increase current consumption In very low power modes it may be desirable to disable the VREF regulator to minimize current consumption Note howe...

Page 860: ...og offset will be minimized This bit is set during factory trimming of the VREF voltage This bit should be written to 1 to achieve the performance stated in the data sheet If the internal voltage regu...

Page 861: ...odule is disabled 1 The module is enabled 6 REGEN Regulator enable This bit is used to enable the internal 1 75 V regulator to produce a constant internal voltage supply in order to reduce the sensiti...

Page 862: ...served 37 3 Functional Description The Voltage Reference is a bandgap buffer system Unity gain amplifiers are used The VREF_OUT signal can be used by both internal and external peripherals in low and...

Page 863: ...de and there is no buffered voltage output The Voltage Reference is in standby mode If this mode is first selected and the low power or high power buffer mode is subsequently enabled there will be a d...

Page 864: ...then you must wait the longer of Tstup or until SC VREFST 1 when the chop oscillator is not enabled If the chop oscillator is being used you must wait the time specified by Tchop_osc_stup chop oscill...

Page 865: ...SC MODE_LV will not clear SC VREFST but there will be some startup time before the output voltage at the VREF_OUT pin has settled This is the buffer start up delay Tstup and the value is specified in...

Page 866: ...Initialization Application Information K22F Sub Family Reference Manual Rev 4 08 2016 866 NXP Semiconductors...

Page 867: ...he PDB can optionally provide pulse outputs Pulse Out s that are used as the sample window in the CMP block 38 1 1 Features Up to 15 trigger input sources and one software trigger source Up to 8 confi...

Page 868: ...1 2 Implementation In this section the following letters refer to the number of output triggers N Total available number of PDB channels n PDB channel number valid from 0 to N 1 M Total available pre...

Page 869: ...information 38 1 4 DAC External Trigger Input Connections The implementation of DAC external trigger inputs is chip specific See the chip configuration information for details 38 1 5 Block diagram Th...

Page 870: ...interrupt TOEx POyDLY2 POyDLY1 Pulse Generation Pulse Out y PDBPOEN y Pulse Out y DAC interval trigger x From trigger mux TOEx DAC external trigger input Control logic PDB counter DAC interval counter...

Page 871: ...in the modulus register and the counting is restarted This enables a continuous stream of pre triggers trigger outputs as a result of a single trigger input event Enabled Bypassed The pre trigger and...

Page 872: ...W 0000_0000h 38 3 5 877 4003_603C Channel n Status register PDB0_CH1S 32 R W 0000_0000h 38 3 6 878 4003_6040 Channel n Delay 0 register PDB0_CH1DLY0 32 R W 0000_0000h 38 3 7 879 4003_6044 Channel n D...

Page 873: ...their buffers immediately after 1 is written to LDOK 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to...

Page 874: ...tion factor selected by MULT 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT 110 Counting uses the peripheral clock divided by 64 times of the...

Page 875: ...s mode 0 PDB operation in One Shot mode 1 PDB operation in Continuous mode 0 LDOK Load OK Writing 1 to LDOK bit updates the MOD IDLY CHnDLYm DACINTx and POyDLY registers with the values previously wri...

Page 876: ...s reserved and always has the value 0 MOD PDB Modulus Specifies the period of the counter When the counter reaches this value it will be reset back to zero If the PDB is in Continuous mode the count b...

Page 877: ...to schedule an independent interrupt at some point in the PDB cycle If enabled a PDB interrupt is generated when the counter is equal to the IDLY Reading this field returns the value of internal regi...

Page 878: ...asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG...

Page 879: ...he internal device bus does not write directly to this register The value in this register s internal buffer is loaded into this register only after 1 is written to the SC LDOK bit Address 4003_6000h...

Page 880: ...d always has the value 0 DLY PDB Channel Delay These bits specify the delay value for the channel s corresponding pre trigger The pre trigger asserts when the counter is equal to DLY Reading these bit...

Page 881: ...instead in other words the internal device bus does not write directly to this register The value in this register s internal buffer is loaded into this register only after 1 is written to the SC LDO...

Page 882: ...egister The value in this register s internal buffer is loaded into this register only after 1 is written to the SC LDOK bit Address 4003_6000h base 194h offset 4d i where i 0d to 1d Bit 31 30 29 28 2...

Page 883: ...PDB channel n pre trigger outputs 0 to M each pre trigger output is connected to ADC hardware trigger select and hardware trigger inputs The pre triggers are used to precondition the ADC block before...

Page 884: ...lock is released by the rising edge of the corresponding ADCnSC1 COCO the ADCnSC1 COCO should be cleared after the conversion result is read so that the next rising edge of ADCnSC1 COCO can be generat...

Page 885: ...gger input sources implemented in this MCU see chip configuration information 38 4 3 Pulse Out s PDB can generate pulse outputs of configurable width When the PDB counter reaches the value set in POyD...

Page 886: ...t is generated 38 4 4 Updating the delay registers The following registers control the timing of the PDB operation and in some of the applications they may need to become effective at the same time PD...

Page 887: ...LDOK 10 A trigger input event is detected after 1 is written to SC LDOK 11 Either the PDB counter reaches the MOD register value or a trigger input event is detected after 1 is written to SC LDOK Aft...

Page 888: ...zes the interrupts Table 38 3 PDB interrupt summary Interrupt Flags Enable bit PDB Interrupt SC PDBIF SC PDBIE 1 and SC DMAEN 0 PDB Sequence Error Interrupt CHnS ERRm SC PDBEIE 1 38 4 6 DMA If SC DMAE...

Page 889: ...alues of total peripheral clocks that can be detected are even values if prescaler is set to 4 then the only values of total peripheral clocks that can be decoded as detected are mod 4 and so forth If...

Page 890: ...Application information K22F Sub Family Reference Manual Rev 4 08 2016 890 NXP Semiconductors...

Page 891: ...chip specific FTM information to see how many channels are supported for each module instance For example if a module instance supports only six channels references to channel numbers 6 and 7 do not a...

Page 892: ...one FlexTimers may be synchronized to provide a larger timer with their counters incrementing in unison assuming the initialization the input clocks the initial and final counting values are the same...

Page 893: ...r each complementary pair Generation of match triggers Initialization trigger Software control of PWM outputs Up to 4 fault inputs for global fault control The polarity of each channel is configurable...

Page 894: ...Wait mode 39 1 4 Block diagram The FTM uses one input output I O pin per channel CHn FTM channel n where n is the channel number 0 7 The following figure shows the FTM structure The central component...

Page 895: ...6V C7V CH6IE CH6F CH1IE CH0IE CH7IE CH7F CH1F CH0F channel 0 interrupt channel 1 interrupt channel 6 interrupt channel 7 interrupt channel 7 match trigger channel 6 output signal channel 6 match trigg...

Page 896: ...e that each FAULTj input may affect all channels selectively since FAULTM 1 0 and FAULTEN control bits are defined for each pair of channels Because there are several FAULTj inputs maximum of 4 for th...

Page 897: ...annel n Status And Control FTM3_C1SC 32 R W 0000_0000h 39 3 6 906 4002_6018 Channel n Value FTM3_C1V 32 R W 0000_0000h 39 3 7 909 4002_601C Channel n Status And Control FTM3_C2SC 32 R W 0000_0000h 39...

Page 898: ...607C Fault Control FTM3_FLTCTRL 32 R W 0000_0000h 39 3 20 932 4002_6080 Quadrature Decoder Control And Status FTM3_QDCTRL 32 R W 0000_0000h 39 3 21 935 4002_6084 Configuration FTM3_CONF 32 R W 0000_00...

Page 899: ...ter Initial Value FTM0_CNTIN 32 R W 0000_0000h 39 3 8 909 4003_8050 Capture And Compare Status FTM0_STATUS 32 R W 0000_0000h 39 3 9 910 4003_8054 Features Mode Selection FTM0_MODE 32 R W 0000_0004h 39...

Page 900: ...TM1_C3SC 32 R W 0000_0000h 39 3 6 906 4003_9028 Channel n Value FTM1_C3V 32 R W 0000_0000h 39 3 7 909 4003_902C Channel n Status And Control FTM1_C4SC 32 R W 0000_0000h 39 3 6 906 4003_9030 Channel n...

Page 901: ..._0000h 39 3 27 945 4003_A000 Status And Control FTM2_SC 32 R W 0000_0000h 39 3 3 903 4003_A004 Counter FTM2_CNT 32 R W 0000_0000h 39 3 4 904 4003_A008 Modulo FTM2_MOD 32 R W 0000_0000h 39 3 5 905 4003...

Page 902: ...sertion Control FTM2_DEADTIME 32 R W 0000_0000h 39 3 15 924 4003_A06C FTM External Trigger FTM2_EXTTRIG 32 R W 0000_0000h 39 3 16 925 4003_A070 Channels Polarity FTM2_POL 32 R W 0000_0000h 39 3 17 927...

Page 903: ...ed This read only field is reserved and always has the value 0 7 TOF Timer Overflow Flag Set by hardware when the FTM counter passes the value in the MOD register The TOF bit is cleared by reading the...

Page 904: ...ct disables the FTM counter 01 System clock 10 Fixed frequency clock 11 External clock PS Prescale Factor Selection Selects one of 8 division factors for the clock source selected by CLKS The new pres...

Page 905: ...to the MOD register latches the value into a buffer The MOD register is updated with the value of its write buffer according to Registers updated from write buffers If FTMEN 0 this write coherency me...

Page 906: ...on Falling Edge Only 11 Capture on Rising or Falling Edge 01 01 Output Compare Toggle Output on match 10 Clear Output on match 11 Set Output on match 1X 10 Edge Aligned PWM High true pulses clear Outp...

Page 907: ...t Enable Detected Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1 Enabled Rising and falling edges Address Base address Ch offset 8d i where i 0d to 7d Bit 31 30 29 28...

Page 908: ...tten only when MODE WPDIS 1 4 MSA Channel Mode Select Used for further selections in the channel logic Its functionality is dependent on the channel mode See Table 39 2 This field is write protected I...

Page 909: ...0 0 FTMx_CnV field descriptions Field Description 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 VAL Channel Value Captured FTM counter value of the...

Page 910: ...y one read of STATUS All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to STATUS Hardware sets the individual channel flags when an event occurs on the channel CHnF is cleared by...

Page 911: ...g See the register description 0 No channel event has occurred 1 A channel event has occurred 5 CH5F Channel 5 Flag See the register description 0 No channel event has occurred 1 A channel event has o...

Page 912: ...bal enable bit for FTM specific features and the control bits used to configure Fault control mode and interrupt Capture Test mode PWM synchronization Write protection Channel output initialization Th...

Page 913: ...ed by MOD CnV OUTMASK and FTM counter synchronization See PWM synchronization The PWMSYNC bit configures the synchronization when SYNCMODE is 0 0 No restrictions Software and hardware triggers can be...

Page 914: ...ardware or software triggers but not both at the same time otherwise unpredictable behavior is likely to happen The selection of the loading point CNTMAX and CNTMIN bits is intended to provide the upd...

Page 915: ...rigger 1 input signal 0 Trigger is disabled 1 Trigger is enabled 4 TRIG0 PWM Synchronization Hardware Trigger 0 Enables hardware trigger 0 to the PWM synchronization Hardware trigger 0 occurs when a r...

Page 916: ...loading point is enabled 39 3 12 Initial State For Channels Output FTMx_OUTINIT Address Base address 5Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0...

Page 917: ...nnel 2 Output Initialization Value Selects the value that is forced into the channel output when the initialization occurs 0 The initialization value is 0 1 The initialization value is 1 1 CH1OI Chann...

Page 918: ...mally 1 Channel output is masked It is forced to its inactive state 6 CH6OM Channel 6 Output Mask Defines if the channel output is masked or unmasked 0 Channel output is not masked It continues to ope...

Page 919: ...ed It continues to operate normally 1 Channel output is masked It is forced to its inactive state 39 3 14 Function For Linked Channels FTMx_COMBINE This register contains the control bits used to conf...

Page 920: ...the configuration of the dual edge capture bits This field applies only when DECAPEN 1 DECAP bit is cleared automatically by hardware if dual edge capture one shot mode is selected and when the captur...

Page 921: ...tten only when MODE WPDIS 1 0 The deadtime insertion in this pair of channels is disabled 1 The deadtime insertion in this pair of channels is enabled 19 DECAP2 Dual Edge Capture Mode Captures For n 4...

Page 922: ...f registers C n V and C n 1 V 0 The PWM synchronization in this pair of channels is disabled 1 The PWM synchronization in this pair of channels is enabled 12 DTEN1 Deadtime Enable For n 2 Enables the...

Page 923: ...is write protected It can be written only when MODE WPDIS 1 0 The fault control in this pair of channels is disabled 1 The fault control in this pair of channels is enabled 5 SYNCEN0 Synchronization...

Page 924: ...e combine feature for channels n and n 1 This field is write protected It can be written only when MODE WPDIS 1 0 Channels n and n 1 are independent 1 Channels n and n 1 are combined 39 3 15 Deadtime...

Page 925: ...s This field is write protected It can be written only when MODE WPDIS 1 39 3 16 FTM External Trigger FTMx_EXTTRIG This register Indicates when a channel trigger was generated Enables the generation o...

Page 926: ...erated 6 INITTRIGEN Initialization Trigger Enable Enables the generation of the trigger when the FTM counter is equal to the CNTIN register 0 The generation of initialization trigger is disabled 1 The...

Page 927: ...0 CH2TRIG Channel 2 Trigger Enable Enables the generation of the channel trigger when the FTM counter is equal to the CnV register 0 The generation of the channel trigger is disabled 1 The generation...

Page 928: ...ow 4 POL4 Channel 4 Polarity Defines the polarity of the channel output This field is write protected It can be written only when MODE WPDIS 1 0 The channel polarity is active high 1 The channel polar...

Page 929: ...low 39 3 18 Fault Mode Status FTMx_FMS This register contains the fault detection flags write protection enable bit and the logic OR of the enabled fault inputs Address Base address 74h offset Bit 31...

Page 930: ...of the enabled fault inputs is 0 1 The logic OR of the enabled fault inputs is 1 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 FAULTF3 Fault Detectio...

Page 931: ...the fault input 1 A fault condition was detected at the fault input 0 FAULTF0 Fault Detection Flag 0 Set by hardware when fault control is enabled the corresponding fault input is enabled and a fault...

Page 932: ...FVAL Channel 1 Input Filter Selects the filter value for the channel input The filter is disabled when the value is zero CH0FVAL Channel 0 Input Filter Selects the filter value for the channel input T...

Page 933: ...ly when MODE WPDIS 1 0 Fault input filter is disabled 1 Fault input filter is enabled 5 FFLTR1EN Fault Input 1 Filter Enable Enables the filter for the fault input This field is write protected It can...

Page 934: ...ten only when MODE WPDIS 1 0 Fault input is disabled 1 Fault input is enabled 0 FAULT0EN Fault Input 0 Enable Enables the fault input This field is write protected It can be written only when MODE WPD...

Page 935: ...0 0 0 0 0 0 FTMx_QDCTRL field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 PHAFLTREN Phase A Input Filter Enable E...

Page 936: ...ode used in the Quadrature Decoder mode 0 Phase A and phase B encoding mode 1 Count and direction encoding mode 2 QUADIR FTM Counter Direction In Quadrature Decoder Mode Indicates the counting directi...

Page 937: ...alue 0 10 GTBEOUT Global Time Base Output Enables the global time base signal generation to other FTMs 0 A global time base signal generation is disabled 1 A global time base signal generation is enab...

Page 938: ...16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FLT3POL FLT2POL FLT1POL FLT0POL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_FLTPOL field descriptions Fie...

Page 939: ...es a fault 1 The fault input polarity is active low A 0 at the fault input indicates a fault 39 3 24 Synchronization Configuration FTMx_SYNCONF This register selects the PWM synchronization configurat...

Page 940: ...ays has the value 0 12 SWSOC Software output control synchronization is activated by the software trigger 0 The software trigger does not activate the SWOCTRL register synchronization 1 The software t...

Page 941: ...stem clock 1 CNTIN register is updated with its buffer value by the PWM synchronization 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 HWTRIGMODE Hardw...

Page 942: ...Enable 0 Inverting is disabled 1 Inverting is enabled 0 INV0EN Pair Channels 0 Inverting Enable 0 Inverting is disabled 1 Inverting is enabled 39 3 26 FTM Software Output Control FTMx_SWOCTRL This reg...

Page 943: ...5 Software Output Control Value 0 The software output control forces 0 to the channel output 1 The software output control forces 1 to the channel output 12 CH4OCV Channel 4 Software Output Control V...

Page 944: ...Control Enable 0 The channel output is not affected by software output control 1 The channel output is affected by software output control 3 CH3OC Channel 3 Software Output Control Enable 0 The channe...

Page 945: ...reserved This read only field is reserved and always has the value 0 9 LDOK Load Enable Enables the loading of the MOD CNTIN and CV registers with the values of their write buffers 0 Loading updated v...

Page 946: ...the matching process 1 Include the channel in the matching process 1 CH1SEL Channel 1 Select 0 Do not include the channel in the matching process 1 Include the channel in the matching process 0 CH0SE...

Page 947: ...FTM counter After any chip reset CLKS 1 0 0 0 so no clock source is selected The CLKS 1 0 bits may be read or written at any time Disabling the FTM counter by writing 0 0 to the CLKS 1 0 bits does not...

Page 948: ...ws an example of the prescaler counter and FTM counter FTM counter 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 2 3 3 1 1 1 1 1 1 1 1 1 selected input clock prescaler counter FTM counting is up PS 2 0 001 CNTIN 0x...

Page 949: ...t TOF bit set TOF bit 4 4 3 2 1 4 3 2 1 0 1 2 3 4 0 1 2 3 4 4 3 CNTIN 0xFFFC in two s complement is equal to 4 period of counting MOD CNTIN 0x0001 x period of FTM counter clock Figure 39 4 Example of...

Page 950: ...et this requirement Any values of CNTIN and MOD that do not satisfy this criteria can result in unpredictable behavior MOD CNTIN is a redundant condition In this case the FTM counter is always equal t...

Page 951: ...final value of the count The value of CNTIN is loaded into the FTM counter and the counter increments until the value of MOD is reached at which point the counter is decremented until it returns to t...

Page 952: ...CnV 15 1 In this case 0 CPWM is generated 39 4 3 3 Free running counter If FTMEN 0 and MOD 0x0000 or MOD 0xFFFF the FTM counter is a free running counter In this case the FTM counter runs free from 0x...

Page 953: ...the TOF bit is set The NUMTOF 4 0 bits define the number of times that the FTM counter overflow should occur before the TOF bit to be set If NUMTOF 4 0 0x00 then the TOF bit is set at each FTM counte...

Page 954: ...ured for input capture the FTMxCHn pin is an edge sensitive input ELSnB ELSnA control bits determine which edge falling or rising triggers input capture event Note that the maximum frequency for the c...

Page 955: ...1 Filter for Input Capture mode The filter function is only available on channels 0 1 2 and 3 First the input signal is synchronized by the system clock Following synchronization the input signal ente...

Page 956: ...wo rising edges to the synchronizer one rising edge to the filter output plus one more to the edge detector In other words CHnF is set 4 4 CHnFVAL 3 0 system clock periods after a valid edge occurs on...

Page 957: ...the current value of the FTM counter is captured into the CnV register the CHnF bit is set the channel n interrupt is generated if CHnIE 1 and the FTM counter is reset to the CNTIN register value Thi...

Page 958: ...set also are reset 39 4 5 Output Compare mode The Output Compare mode is selected when DECAPEN 0 COMBINE 0 CPWMS 0 and MSnB MSnA 0 1 In Output Compare mode the FTM can generate timed pulses with progr...

Page 959: ...e mode when the match clears the channel output channel n output CHnF bit TOF bit CNT MOD 0x0005 CnV 0x0003 counter overflow channel n match counter overflow channel n match counter overflow 0 1 2 3 4...

Page 960: ...r reaches the value in the CnV register the CHnF bit is set and the channel n interrupt is generated if CHnIE 1 however the channel n output is not controlled by FTM If ELSnB ELSnA 1 0 then the channe...

Page 961: ...zero the following EPWM signals can be generated 0 EPWM signal if CnV CNTIN EPWM signal between 0 and 100 if CNTIN CnV MOD 100 EPWM signal when CNTIN CnV or CnV MOD 39 4 7 Center Aligned PWM CPWM mod...

Page 962: ...SnB ELSnA 0 0 when the FTM counter reaches the value in the CnV register the CHnF bit is set and the channel n interrupt is generated if CHnIE 1 however the channel n output is not controlled by FTM I...

Page 963: ...you do not need to generate a 100 duty cycle CPWM signal This is not a significant limitation because the resulting period is much longer than required for normal applications The CPWM mode must not b...

Page 964: ...used in the generation of the channels n and n 1 output However if ELSnB ELSnA 0 0 then the channel n output is not controlled by FTM and if ELS n 1 B ELS n 1 A 0 0 then the channel n 1 output is not...

Page 965: ...SnB ELSnA X 1 MOD C n V CNTIN Figure 39 28 Channel n output if C n V CNTIN and CNTIN C n 1 V MOD FTM counter not fully 100 duty cycle channel n output with ELSnB ELSnA 1 0 not fully 0 duty cycle chann...

Page 966: ...t if C n V CNTIN and CNTIN C n 1 V MOD and C n 1 V is Almost Equal to MOD FTM counter 0 duty cycle channel n output with ELSnB ELSnA 1 0 100 duty cycle channel n output with ELSnB ELSnA X 1 C n V MOD...

Page 967: ...TIN channel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 100 duty cycle 0 duty cycle MOD Figure 39 33 Channel n output if C n V C n 1 V CNTIN FTM counter CNTIN channel n output...

Page 968: ...5 Channel n output if CNTIN C n V MOD and CNTIN C n 1 V MOD and C n V C n 1 V FTM counter C n V channel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 0 duty cycle 100 duty cycle...

Page 969: ...f C n 1 V CNTIN and CNTIN C n V MOD FTM counter channel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 100 duty cycle 0 duty cycle MOD C n V C n 1 V CNTIN Figure 39 38 Channel n o...

Page 970: ...9 40 Channel n output if C n 1 V MOD and CNTIN C n V MOD 39 4 8 1 Asymmetrical PWM In Combine mode the control of the PWM signal first edge when the channel n match occurs that is FTM counter C n V is...

Page 971: ...1 0 channel n match Figure 39 41 Channel n 1 output in Complementary mode with ELSnB ELSnA 1 0 FTM counter channel n 1 match channel n 1 output with COMP 1 channel n 1 output with COMP 0 channel n out...

Page 972: ...ed mode is not CPWM then MOD register is updated after MOD register was written and the FTM counter changes from MOD to CNTIN If the FTM counter is at free running counter mode then this update occurs...

Page 973: ...is updated by the C n V and C n 1 V register synchronization If the selected mode is not output compare and SYNCEN 1 then CnV register is updated by the C n V and C n 1 V register synchronization 39 4...

Page 974: ...event occurs when 1 is written to the SYNC SWSYNC bit The SWSYNC bit is cleared when 0 is written to it or when the PWM synchronization initiated by the software event is completed If another softwar...

Page 975: ...al value CNTIN If in Up down counting mode then the boundary cycle is defined as when the counter turns from down to up counting and when from up to down counting The following figure shows the bounda...

Page 976: ...value This synchronization is enabled if FTMEN 1 The MOD register synchronization can be done by either the enhanced PWM synchronization SYNCMODE 1 or the legacy PWM synchronization SYNCMODE 0 Howeve...

Page 977: ...n bit wait hardware trigger n HWTRIGMODE bit clear TRIGn bit wait the next selected loading point update MOD with its buffer value update MOD with its buffer value HWRSTCNT bit Figure 39 46 MOD regist...

Page 978: ...gister is updated write 1 to TRIG0 bit TRIG0 bit trigger 0 event Figure 39 48 MOD synchronization with SYNCMODE 0 HWTRIGMODE 0 PWMSYNC 0 REINIT 0 and a hardware trigger was used If SYNCMODE 0 PWMSYNC...

Page 979: ...PWMSYNC 0 REINIT 1 and a hardware trigger was used If SYNCMODE 0 and PWMSYNC 1 then this synchronization is made on the next selected loading point after the software trigger event takes place The SW...

Page 980: ...chronization mechanism is the same as the MOD register synchronization However it is expected that the C n V and C n 1 V registers be synchronized only by the enhanced PWM synchronization SYNCMODE 1 3...

Page 981: ...re trigger n TRIGn bit HWOM bit SWOM bit SWSYNC bit rising edge of system clock update OUTMASK with its buffer value hardware trigger OUTMASK is updated by software trigger OUTMASK is updated by hardw...

Page 982: ...C bit SWSYNC bit software trigger event Figure 39 53 OUTMASK synchronization with SYNCMODE 0 SYNCHOM 1 PWMSYNC 0 and software trigger was used system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 eve...

Page 983: ...INVCTRL register synchronization updates the INVCTRL register with its buffer value The INVCTRL register can be updated at each rising edge of system clock INVC 0 or by the enhanced PWM synchronizatio...

Page 984: ...MODE bit rising edge of system clock update INVCTRL with its buffer value update INVCTRL with its buffer value HWINVC bit TRIGn bit wait hardware trigger n update INVCTRL with its buffer value HWTRIGM...

Page 985: ...r SWOCTRL is updated by hardware trigger enhanced PWM synchronization update SWOCTRL register by PWM synchronization update SWOCTRL register at each rising edge of system clock yes 0 1 0 0 no 1 SWOC b...

Page 986: ...hannel output from transitioning to 1 If no deadtime insertion is selected then the channel n 1 transitions to logical value 1 immediately after the synchronization event occurs synchronization event...

Page 987: ...rdware trigger TRIGn bit 0 0 0 0 0 1 Figure 39 59 FTM counter synchronization flowchart In the case of legacy PWM synchronization the FTM counter synchronization depends on REINIT and PWMSYNC bits acc...

Page 988: ...9 61 FTM counter synchronization with SYNCMODE 0 HWTRIGMODE 0 REINIT 1 PWMSYNC 0 and a hardware trigger was used If SYNCMODE 0 REINIT 1 and PWMSYNC 1 then this synchronization is made on the next enab...

Page 989: ...elected the channel n output behavior is changed to force high at the beginning of the PWM period force low at the channel n match and force high at the channel n 1 match See the following figure NOTE...

Page 990: ...uffer INVCTRL register synchronization INV m bit channel n output after the inverting channel n 1 output after the inverting INV m bit selects the inverting to the pair channels n and n 1 channel n ou...

Page 991: ...TE CH n OCV 1 and CH n 1 OCV 0 SWOCTRL register synchronization SWOCTRL register synchronization write to SWOCTRL register write to SWOCTRL register Figure 39 65 Example of software output control in...

Page 992: ...ls The DTPS 1 0 bits define the prescaler for the system clock and the DTVAL 5 0 bits define the deadtime modulo that is the number of the deadtime prescaler clocks The deadtime delay insertion ensure...

Page 993: ...nA 1 0 POL n 0 and POL n 1 0 FTM counter channel n 1 match channel n output before deadtime insertion channel n 1 output before deadtime insertion channel n output after deadtime insertion channel n 1...

Page 994: ...tch channel n output before deadtime insertion channel n output after deadtime insertion channel n 1 output before deadtime insertion channel n 1 output after deadtime insertion Figure 39 68 Example o...

Page 995: ...the following figure FTM counter channel n output before output mask CHnOM bit channel n output after output mask the beginning of new PWM cycles configured PWM signal starts to be available in the c...

Page 996: ...on counter overflow the counter is reset At the next input transition the counter starts counting again Any pulse that is shorter than the minimum value selected by FFVAL 3 0 bits system clock is rega...

Page 997: ...FAULTEN 1 then outputs are forced to their safe values Channel n output takes the value of POL n Channel n 1 takes the value of POL n 1 The fault interrupt is generated when FAULTF 1 and FAULTIE 1 Th...

Page 998: ...ring and POLn 0 NOTE Figure 39 73 Fault control with automatic fault clearing 39 4 16 2 Manual fault clearing If the manual fault clearing is selected FAULTM 1 0 0 1 or 1 0 then the channels output di...

Page 999: ...nput polarity is high so the logical one at the fault input j indicates a fault If FLTjPOL 1 the fault j input polarity is low so the logical zero at the fault input j indicates a fault 39 4 17 Polari...

Page 1000: ...zero 1 1 is forced to one is forced to one The following table shows the values that channels n and n 1 are forced by initialization when COMP 1 or DTEN 1 Table 39 12 Initialization behavior when COM...

Page 1001: ...EN CH n OC CH n OCV CH n 1 OC CH n 1 OCV DTEN m CH n OM CH n 1 OM FAULTEN m POL n POL n 1 Figure 39 75 Priority of the features used at the generation of channels n and n 1 outputs signals Note The I...

Page 1002: ...1 CH5TRIG 1 d CH0TRIG 1 CH1TRIG 1 CH2TRIG 1 CH3TRIG 1 CH4TRIG 1 CH5TRIG 1 the beginning of new PWM cycles MOD FTM counter C5V FTM counter C4V FTM counter C3V FTM counter C2V FTM counter C1V FTM count...

Page 1003: ...wing figures show these cases CPWMS 0 0x0C 0x0D 0x0E 0x0F 0x00 0x01 0x02 0x03 0x04 0x05 initialization trigger FTM counter system clock CNTIN 0x0000 MOD 0x000F Figure 39 77 Initialization trigger is g...

Page 1004: ...if CNT CNTIN CLKS 1 0 0 0 and a value different from zero is written to CLKS 1 0 bits system clock CNT channel n input CHnF bit C n V XX 0x27 selected channel n input event rising edge NOTE Channel n...

Page 1005: ...er and CHnF bits are set Therefore the FTM counter is updated with its next value according to its configuration Its next value depends on CNTIN MOD and the written value to FTM counter The next reads...

Page 1006: ...1 the CHnF bit is cleared either by channel DMA transfer done or reading CnSC while CHnF is set and then writing a zero to CHnF bit according to CHnIE bit See the following table Table 39 14 Clear CH...

Page 1007: ...pulse width measurement In the Dual Edge Capture mode only channel n input is used and channel n 1 input is ignored If the selected edge by channel n bits is detected at channel n input then CH n F bi...

Page 1008: ...his bit is cleared both edges were captured and the captured values are ready for reading in the C n V and C n 1 V registers Similarly when the CH n 1 F bit is set both edges were captured and the cap...

Page 1009: ...arity pulse width is measured The pulse width measurement can be made in One Shot Capture mode or Continuous Capture mode The following figure shows an example of the Dual Edge Capture One Shot mode u...

Page 1010: ...e for positive polarity pulse width measurement The following figure shows an example of the Dual Edge Capture Continuous mode used to measure the positive polarity pulse width The DECAPEN bit selects...

Page 1011: ...ement If the channels n and n 1 are configured to capture consecutive edges of the same polarity then the period of the channel n input signal is measured If both channels n and n 1 are configured to...

Page 1012: ...CAP clear CH n F and clear CH n 1 F are made by the user 4 9 11 12 13 14 6 15 16 17 18 19 20 21 22 23 24 25 26 27 28 17 20 15 20 23 C n V CH n 1 F bit CH n F bit clear CH n F 1 Problem 1 channel n inp...

Page 1013: ...8 10 12 16 14 24 22 20 18 26 25 21 Figure 39 87 Dual Edge Capture Continuous mode to measure of the period between two consecutive rising edges 39 4 24 5 Read coherency mechanism The Dual Edge Captur...

Page 1014: ...t 1 occurred and the read of C n 1 V returns the FTM counter value when the event 2 occurred read C n 1 V FTM counter channel n input after the filter channel input channel n capture buffer C n V C n...

Page 1015: ...ts in FILTER0 register The phase B input filter is enabled by PHBFLTREN bit and this filter s value is defined by CH1FVAL 3 0 bits CH n 1 FVAL 3 0 bits in FILTER0 register Except for CH0FVAL 3 0 and C...

Page 1016: ...d phase A and B signals define the counting rate The FTM counter is updated when there is an edge either at the phase A or phase B signals If PHAPOL 0 and PHBPOL 0 then the FTM counter increment happe...

Page 1017: ...TM counter overflow occurred phase A phase B FTM counter increment decrement FTM counter MOD CNTIN 0x0000 Time 1 1 1 1 1 1 1 set TOF set TOFDIR set TOF set TOFDIR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Fig...

Page 1018: ...5 1 Quadrature Decoder boundary conditions The following figures show the FTM counter responding to motor jittering typical in motor position control applications phase A phase B FTM counter MOD CNTIN...

Page 1019: ...avoid these oscillations 39 4 26 BDM mode When the chip is in BDM mode the BDMMODE 1 0 bits select the behavior of the FTM counter the CH n F bit the channels output and the writes to the MOD CNTIN an...

Page 1020: ...and the channels outputs are updated to the initial value except for channels in Output Compare mode In the channels outputs initialization the channel n output is forced to the CH n OI bit value when...

Page 1021: ...SEL 0 CH4SEL 1 CH5SEL 0 CH6SEL 1 CH7SEL 0 f LDOK 1 CH0SEL 1 CH1SEL 1 CH2SEL 1 CH3SEL 1 CH4SEL 1 CH5SEL 1 CH6SEL 1 CH7SEL 1 d e f b a FTM counter MOD FTM counter C7V FTM counter C6V FTM counter C5V FTM...

Page 1022: ...s not available on channel j output If CHjIE 1 then the channel j interrupt is generated when the channel j match occurs At the intermediate load neither the channels outputs nor the FTM counter are c...

Page 1023: ...ules the configuration of each FTM module should guarantee that its FTM counter starts counting as soon as the gtb_in signal is 1 The GTB feature does not provide continuous synchronization of FTM cou...

Page 1024: ...ntrol register its value is updated to zero and the pins are not controlled by FTM See the table in the description of CnSC register After the reset the FTM should be configurated item 2 It is necessa...

Page 1025: ...is a write to CNT register item 3 In this case use the software output control Software output control or the initialization Initialization to update the channel output to the selected value item 4 1...

Page 1026: ...utput are in the safe value Re Configuration FTM counter and channels to generation of periodic signals Disable the clock If the selected mode is Quadrature Decoder then disable this mode Examples of...

Page 1027: ...is necessary SWSOC 0 1 and SWOC 0 1 SW Synchronization for Inverting if it is necessary SWINVC 0 1 and INVC 0 1 SW Synchronization for SWOM always SWOM 1 No enable the SW Synchronization for write bu...

Page 1028: ...Initialization Procedure K22F Sub Family Reference Manual Rev 4 08 2016 1028 NXP Semiconductors...

Page 1029: ...s module s instances see the chip configuration information The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels 40 1 1 Block diagram The following figure...

Page 1030: ...ber of PIT channels used in this MCU 40 1 2 Features The main features of this block are Ability of timers to generate DMA trigger pulses Ability of timers to generate interrupts Maskable interrupts I...

Page 1031: ...CVAL1 32 R 0000_0000h 40 3 3 1033 4003_7118 Timer Control Register PIT_TCTRL1 32 R W 0000_0000h 40 3 4 1034 4003_711C Timer Flag Register PIT_TFLG1 32 R W 0000_0000h 40 3 5 1034 4003_7120 Timer Load V...

Page 1032: ...eld is reserved and always has the value 0 2 Reserved This field is reserved 1 MDIS Module Disable PIT section Disables the standard timers This field must be enabled before any other setup is done 0...

Page 1033: ...er expires To abort the current cycle and start a timer period with the new value the timer must be disabled and enabled again 40 3 3 Current Timer Value Register PIT_CVALn These registers indicate th...

Page 1034: ...r n can decrement by 1 Timer 0 cannot be chained 0 Timer is not chained 1 Timer is chained to previous timer For example for Channel 2 if this field is set Timer 2 is chained to Timer 1 1 TIE Timer In...

Page 1035: ...l description This section provides the functional description of the module 40 4 1 General operation This section gives detailed information on the internal operation of the module Each timer can be...

Page 1036: ...lue and then enabling the timer again See the following figure Timer enabled Disable timer p1 p1 Re enable timer Start value p1 Trigger event Set new load value p2 p2 p2 Figure 40 3 Modifying running...

Page 1037: ...e previous timer has expired So if timer n 1 has counted down to 0 counter n will decrement the value by one This allows to chain some of the timers together to form a longer timer The first timer tim...

Page 1038: ...f 100 MHz Timers 1 and 2 are available An interrupt shall be raised every 1 minute The PIT module needs to be activated by writing a 0 to MCR MDIS The 100 MHz clock frequency equates to a clock period...

Page 1039: ...10 counts PIT_TCTRL2 TIE enable Timer 2 interrupt PIT_TCTRL2 CHN chain Timer 2 to Timer 1 PIT_TCTRL2 TEN start Timer 2 Timer 1 PIT_LDVAL1 0x23C345FF setup Timer 1 for 600 000 000 cycles PIT_TCTRL1 TE...

Page 1040: ...Example configuration for chained timers K22F Sub Family Reference Manual Rev 4 08 2016 1040 NXP Semiconductors...

Page 1041: ...et events allowing it to be used as a time of day counter 41 1 1 Features The features of the LPTMR module include 16 bit time counter or pulse counter with compare Optional interrupt can generate asy...

Page 1042: ...ons Table 41 2 LPTMR signal descriptions Signal I O Description LPTMR0_ALTn I Pulse Counter Input pin 41 2 1 Detailed signal descriptions Table 41 3 LPTMR interface detailed signal descriptions Signal...

Page 1043: ...s Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 TCF Timer Compare Flag TCF is set when the LPTMR is enabled and the CNR equals th...

Page 1044: ...disabled 0 CNR is reset whenever TCF is set 1 CNR is reset on overflow 1 TMS Timer Mode Select Configures the mode of the LPTMR TMS must be altered only when the LPTMR is disabled 0 Time Counter mode...

Page 1045: ...scaler clock by 1024 glitch filter recognizes change on input pin after 512 rising clock edges 1010 Prescaler divides the prescaler clock by 2048 glitch filter recognizes change on input pin after 102...

Page 1046: ...CNR equals the value in the CMR and increments TCF is set and the hardware trigger asserts until the next time the CNR increments If the CMR is 0 the hardware trigger will remain asserted until the L...

Page 1047: ...e LPTMR counter is reset to zero following a warm reset 41 4 2 LPTMR clocking The LPTMR prescaler glitch filter can be clocked by one of the four clocks The clock source must be enabled before the LPT...

Page 1048: ...on every clock cycle When the LPTMR is enabled the first increment will take an additional one or two prescaler clock cycles due to synchronization logic 41 4 3 3 Glitch filter In Pulse Counter mode w...

Page 1049: ...is generated CNR is reset if CSR TFC is clear When the LPTMR is enabled the CMR can be altered only when CSR TCF is set When updating the CMR the CMR must be written and CSR TCF must be cleared before...

Page 1050: ...dware trigger is always enabled When Then The CMR is set to 0 with CSR TFC clear The LPTMR hardware trigger will assert on the first compare and does not deassert The CMR is set to a nonzero value or...

Page 1051: ...ion that can correct errors between 0 12 ppm and 3906 ppm Register write protection Lock register requires VBAT POR or software reset to enable write access Access control registers require system res...

Page 1052: ...put I XTAL32 32 768 kHz oscillator output O RTC_CLKOUT 1 Hz square wave output or OSCERCLK O RTC_WAKEUP Wakeup for external device O 42 1 3 1 RTC clock output The clock to the seconds counter is avail...

Page 1053: ...W 0000_0000h 42 2 2 1054 4003_D008 RTC Time Alarm Register RTC_TAR 32 R W 0000_0000h 42 2 3 1054 4003_D00C RTC Time Compensation Register RTC_TCR 32 R W 0000_0000h 42 2 4 1055 4003_D010 RTC Control R...

Page 1054: ...s Field Description 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 TPR Time Prescaler Register When the time counter is enabled the TPR is read only...

Page 1055: ...8 CIR Compensation Interval Register Configures the compensation interval in seconds from 1 to 256 to control how frequently the TCR should adjust the number of 32 768 kHz cycles in each second The va...

Page 1056: ...iption 31 24 Reserved This field is reserved This read only field is reserved and always has the value 0 23 15 Reserved This field is reserved This read only field is reserved and always has the value...

Page 1057: ...nstead outputs the RTC 32kHz clock provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals 3 UM Update Mode Allows SR TCE to be written even when the Status Register is...

Page 1058: ...s has the value 0 2 TAF Time Alarm Flag Time alarm flag is set when the TAR TAR equals the TSR TSR and the TSR TSR increments This bit is cleared by writing the TAR register 0 Time alarm has not occur...

Page 1059: ...locked and writes complete as normal 5 SRL Status Register Lock After being cleared this bit can be set only by VBAT POR or software reset 0 Status Register is locked and writes are ignored 1 Status...

Page 1060: ...ll devices Whenever the wakeup pin is enabled and this bit is set the wakeup pin will assert 0 No effect 1 If the wakeup pin is enabled then the wakeup pin will assert 6 5 Reserved This field is reser...

Page 1061: ...8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 IERW Interrupt Enable Register Write After being cleared this bit is set only by system reset It is not...

Page 1062: ...to the Time Alarm Register are ignored 1 Writes to the Time Alarm Register complete as normal 1 TPRW Time Prescaler Register Write After being cleared this bit is set only by system reset It is not af...

Page 1063: ...to the Control Register are ignored 1 Reads to the Control Register complete as normal 3 TCRR Time Compensation Register Read After being cleared this bit is set only by system reset It is not affect...

Page 1064: ...ers The RTC also monitors the chip power supply and electrically isolates itself when the rest of the chip is powered down NOTE An attempt to access an RTC register except the access control registers...

Page 1065: ...ecommended that two read accesses are performed and that software verifies that the same data was returned for both reads The time seconds register and time prescaler register can be written only when...

Page 1066: ...compensation value is used to adjust the number of clock cycles between 127 and 128 Cycles are added or subtracted from the prescaler register when the prescaler register equals 0x3FFF and then increm...

Page 1067: ...R can be used to block write accesses to certain registers until the next VBAT POR or software reset Locking the Control register CR will disable the software reset Locking LR will block future update...

Page 1068: ...icated interrupt vector that is generated once a second and requires no software overhead there is no corresponding status flag to clear It is enabled in the RTC by the time seconds interrupt enable b...

Page 1069: ...0 Specification usb org 2008 The USB full speed controller interfaces to a USBFS LS transceiver NOTE This chapter describes the following registers that have similar names USB_OTGCTL USB_CTL USB_CTRL...

Page 1070: ...onfigured used and detached while the host and other peripherals are in operation USB software provides a uniform view of the system for all application software hiding implementation details that mak...

Page 1071: ...t directly to a printer or a keyboard can connect to a tablet to exchange data With the USB On The Go product you can develop a fully USB compliant peripheral device that can also assume the role of a...

Page 1072: ...directional endpoints DMA or FIFO data stream interfaces Low power consumption IRC48M with clock recovery is supported to eliminate the 48 MHz crystal It is used for USB device only implementation 43...

Page 1073: ...al 15 k pulldown resistors on the USB_DP and USB_DM signals which are primarily intended for Host mode operation but are also useful in Device mode as explained below NOTE For device operation the int...

Page 1074: ...resistors close to the processor Figure 43 3 Host only diagram VOUT33 USB_DM USB_DP 5v VBUS D D GND VDD 3 3v VREGIN 33 33 Place resistors close to the processor Figure 43 4 Typical Device only diagra...

Page 1075: ...th 16 fully bidirectional endpoints would require 512 bytes of system memory to implement the BDT The two BD entries allows for an EVEN BD and ODD BD entry for each endpoint direction This allows the...

Page 1076: ...is shown in the following diagram Current Endpoint BDT Buffer in Memory BDT Page Start of Buffer 000 ODD TX BDT_PAGE Registers END_POINT System Memory End of Buffer Figure 43 6 Buffer descriptor table...

Page 1077: ...endpoint BD entries are indexed into the BDT to allow easy access via USBFS or MCU core When a USB token on an enabled endpoint is received USBFS uses its integrated DMA controller to interrogate the...

Page 1078: ...wnership upon packet completion No address increment FIFO mode Whether data toggle synchronization is enabled How much data is to be transmitted or received Where the buffer resides in system memory W...

Page 1079: ...from the FIFO When KEEP is set normally the NINC bit is also set to prevent address increment 0 Allows USBFS to release the BD when a token has been processed 1 This bit is unchanged by USBFS Bit 3 o...

Page 1080: ...th directions of the associated endpoint To clear the stall condition 1 Clear the associated USB_ENDPTn EPSTALL bit 2 Write the BDT to clear OWN and BDT_STALL TOK_PID n Bits 5 2 can also represent the...

Page 1081: ...N DATA ACK USB RST SOF IN TOKEN DATA ACK OUT TOKEN DATA ACK USB_RST Interrupt Generated USB Host Function TOK_DNE Interrupt Generated SOF Interrupt Generated TOK_DNE Interrupt Generated TOK_DNE Interr...

Page 1082: ...r is the TOKDNE interrupt triggered because it is assumed that a second attempt is queued and will succeed in the future The packet length field written back to the BDT is the MaxPacket value that rep...

Page 1083: ...shold register USB0_SOFTHLD 8 R W 00h 43 4 20 1100 4007_20B0 BDT Page Register 2 USB0_BDTPAGE2 8 R W 00h 43 4 21 1101 4007_20B4 BDT Page Register 3 USB0_BDTPAGE3 8 R W 00h 43 4 22 1101 4007_20C0 Endpo...

Page 1084: ...43 4 25 1104 4007_2108 USB OTG Control register USB0_CONTROL 8 R W 00h 43 4 26 1104 4007_210C USB Transceiver Control register 0 USB0_USBTRC0 8 R W 00h 43 4 27 1105 4007_2114 Frame Adjust Register USB...

Page 1085: ...et 1 1 1 1 1 0 1 1 USBx_IDCOMP field descriptions Field Description 7 6 Reserved This field is reserved This read only field is reserved and always has the value 1 NID Ones complement of PERID ID bits...

Page 1086: ...ter to determine the event that triggers an interrupt Only bits that have changed since the last software read are set Writing a one to a bit clears the associated interrupt Address 4007_2000h base 10...

Page 1087: ...only field is reserved and always has the value 0 0 Reserved This field is reserved Software should not change the value of this bitfield 43 4 6 OTG Interrupt Control register USBx_OTGICR Enables the...

Page 1088: ...f this bitfield This field is reserved 0 Disables the AVBUSCHG interrupt 1 Enables the AVBUSCHG interrupt 43 4 7 OTG Status register USBx_OTGSTAT Displays the actual value from the one millisecond tim...

Page 1089: ...bove the B session valid threshold 2 Reserved This field is reserved This read only field is reserved and always has the value 0 0 The VBUS voltage is above the B session end threshold 1 The VBUS volt...

Page 1090: ...This read only field is reserved and always has the value 0 43 4 9 Interrupt Status register USBx_ISTAT Contains fields for each of the interrupt sources within the USB Module Each of these fields are...

Page 1091: ...one causes STAT to be cleared or the STAT holding register to be loaded into the STAT register 2 SOFTOK This bit is set when the USB Module receives a Start Of Frame SOF token In Host mode this field...

Page 1092: ...Disables the SLEEP interrupt 1 Enables the SLEEP interrupt 3 TOKDNEEN TOKDNE Interrupt Enable 0 Disables the TOKDNE interrupt 1 Enables the TOKDNE interrupt 2 SOFTOKEN SOFTOK Interrupt Enable 0 Disbl...

Page 1093: ...ize bus request and bus grant latency This bit is also set if a data packet to or from the host is larger than the buffer size allocated in the BDT In this case the data packet is truncated as it is p...

Page 1094: ...rupt Enable 0 Disables the BTSERR interrupt 1 Enables the BTSERR interrupt 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 DMAERREN DMAERR Interrupt Ena...

Page 1095: ...the ISTAT register causes the SIE to update STAT with the contents of the next STAT value If the data in the STAT holding register is valid the SIE immediately reasserts to TOKDNE interrupt Address 4...

Page 1096: ...SB Module to generate USB reset signaling This allows the USB Module to reset USB peripherals This control signal is only valid in Host mode HOSTMODEEN 1 Software must set RESET to 1 for the required...

Page 1097: ...This action initializes the Address register to decode address 0x00 as required by the USB specification Address 4007_2000h base 98h offset 4007_2098h Bit 7 6 5 4 3 2 1 0 Read LSEN ADDR Write Reset 0...

Page 1098: ...0 Reserved This field is reserved This read only field is reserved and always has the value 0 43 4 17 Frame Number register Low USBx_FRMNUML The Frame Number registers low and high contain the 11 bit...

Page 1099: ...writes the TOKEN type and endpoint to this register After this register has been written the USB module begins the specified USB transaction to the address contained in the address register The proces...

Page 1100: ...itiating token packet transactions This register must be set to a value that ensures that other packets are not actively being transmitted when the SOF time counts to zero When the SOF counter reaches...

Page 1101: ...Table resides in system memory 43 4 22 BDT Page Register 3 USBx_BDTPAGE3 Contains an 8 bit value used to compute the address where the current Buffer Descriptor Table BDT resides in system memory See...

Page 1102: ...DIS EPRXEN and EPTXEN define if an endpoint is enabled and define the direction of the endpoint The endpoint enable direction control is defined in the following table Table 43 7 Endpoint enable and d...

Page 1103: ...et enables the endpoint for TX transfers See Table 43 7 1 EPSTALL When set this bit indicates that the endpoint is stalled This bit has priority over all other control bits in this register but it is...

Page 1104: ...he USB transceiver 0 D pulldown disabled 1 D pulldown enabled 5 Reserved This field is reserved This read only field is reserved and always has the value 0 4 DMPD Provides observability of the D Pulld...

Page 1105: ...Address 4007_2000h base 10Ch offset 4007_210Ch Bit 7 6 5 4 Read 0 USBRESMEN 0 Write USBRESET Reset 0 0 0 0 Bit 3 2 1 0 Read 0 USB_CLK_ RECOVERY_INT SYNC_DET USB_RESUME_INT Write Reset 0 0 0 0 USBx_US...

Page 1106: ...the only unmasked USB clock recovery interrupt condition results from an overflow of the frequency trim setting values indicating that the frequency trim calculated is out of the adjustment range of t...

Page 1107: ...se The step to fine tune the IRC 48Mhz by adjusting the trim fine value is different during these two phases The step in rough phase is larger than that in tracking phase Switch back to rough stage wh...

Page 1108: ...COVER_IRC_EN field descriptions Field Description 7 2 Reserved This field is reserved 1 IRC_EN IRC48M enable This bit is used to enable the on chip IRC48Mhz module to generate clocks for crystal less...

Page 1109: ...ved This field is reserved Should always be written as 0 4 OVF_ERROR_ EN Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT 0 The interrupt will be masked 1 Th...

Page 1110: ...UHCI compatible host controller found on PC motherboards Host mode allows bulk isochronous interrupt and control transfers Bulk data transfers are performed at nearly the full USB interface bandwidth...

Page 1111: ...7 Enumerate the attached device by sending the appropriate commands to the default control pipe of the connected device To complete a control transaction to a connected device 1 Complete all the step...

Page 1112: ...to the host When the data packet completes the BDT is written and a Token Done ISTAT DNE interrupt is asserted For control transfers with a single packet data phase this completes the data phase of t...

Page 1113: ...as been released back to the processor and the transfer has completed If the peripheral device asserts NAKs the USB FS continues to retry the transfer indefinitely without processor intervention unles...

Page 1114: ...w acts as a Type B device Go to B_IDLE If the A application wants to use the bus or if the B device is doing an SRP as indicated by an A_SESS_VLD Interrupt or Attach or Port Status Change Interrupt ch...

Page 1115: ...cts in 150 ms then B device is becoming the host Go to A_PERIPHERAL Turn off Host mode If A wants to start another session Go to A_HOST A_PERIPHERAL If ID Interrupt or if A_VBUS_VLD interrupt Go to A_...

Page 1116: ...SRP_INIT If ID Interrupt or SRP Done SRP must be done in less than 100 ms Go to B_IDLE B_PERIPHERAL If HNP enabled and the bus is suspended and B wants the bus the B device can become the host Go to B...

Page 1117: ...t clock can be divided by the USB clock divider so set these fields so no clock division is enabled This is the equation for the divider Divider output clock Divider input clock USBFRAC 1 USBDIV 1 So...

Page 1118: ...Device mode IRC48 operation K22F Sub Family Reference Manual Rev 4 08 2016 1118 NXP Semiconductors...

Page 1119: ...m an input power supply varying from 2 7 V to 5 5 V It consists of one 3 3 V power channel When the input power supply is below 3 6 V the regulator goes to pass through mode The following figure shows...

Page 1120: ...led but a switch disconnects its output from the external pin In STANDBY mode the RUN regulator is disabled and the STANDBY regulator output is connected to the external pin Internal power mode signal...

Page 1121: ...ulator is disabled and the standby regulator is active The switch connecting the STANDBY regulator output to the external pin is closed SHUTDOWN The module is disabled The regulator is enabled by defa...

Page 1122: ...USB Voltage Regulator Module Signal Descriptions K22F Sub Family Reference Manual Rev 4 08 2016 1122 NXP Semiconductors...

Page 1123: ...stances see the chip configuration information The serial peripheral interface SPI module provides a synchronous serial bus for communication between a chip and an external peripheral device 45 1 1 Bl...

Page 1124: ...Full duplex three wire synchronous transfers Master mode Slave mode Data streaming operation in Slave mode with continuous slave selection Buffered transmit operation using the transmit first in first...

Page 1125: ...hip selects PCSes with external demultiplexer DMA support for adding entries to TX FIFO and removing entries from RX FIFO TX FIFO is not full TFFF RX FIFO is not empty RFDF Interrupt conditions End of...

Page 1126: ...eues can reside in system RAM external to the module Data transfers between the queues and the module FIFOs are accomplished by a DMA controller or host CPU The following figure shows a system example...

Page 1127: ...signals are controlled by the module and configured as outputs SCK SOUT PCS x 45 1 4 2 Slave Mode Slave mode allows the module to communicate with SPI bus masters In this mode the module responds to...

Page 1128: ...le signal descriptions This table describes the signals on the boundary of the module that may connect off chip in alphabetical order Table 45 1 Module signal descriptions Signal Master mode Slave mod...

Page 1129: ...O Used only when the peripheral chip select strobe is disabled MCR PCSSE Selects an SPI slave to receive data transmitted by the module Peripheral Chip Select Strobe O Used only when the peripheral c...

Page 1130: ...Attributes Register In Slave Mode SPI0_CTAR0_SLAVE 32 R W 7800_0000h 45 3 4 1140 4002_C010 Clock and Transfer Attributes Register In Master Mode SPI0_CTAR1 32 R W 7800_0000h 45 3 3 1136 4002_C02C Stat...

Page 1131: ...ter SPI1_SR 32 R W 0200_0000h 45 3 5 1142 4002_D030 DMA Interrupt Request Select and Enable Register SPI1_RSER 32 R W 0000_0000h 45 3 6 1145 4002_D034 PUSH TX FIFO Register In Master Mode SPI1_PUSHR 3...

Page 1132: ...OOE Reserved PCSIS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DOZE MDIS DIS_ TXF DIS_ RXF 0 0 SMPL_PT 0 Reserved Reserved HALT W CLR_TXF CLR_RXF Reset 0 1 0 0...

Page 1133: ...the RX FIFO overflow condition configures the module to ignore the incoming serial data or overwrite existing data If the RX FIFO is full and new data is received the data from the transfer generating...

Page 1134: ...the MDIS bit is cleared 0 RX FIFO is enabled 1 RX FIFO is disabled 11 CLR_TXF Clear TX FIFO Flushes the TX FIFO Writing a 1 to CLR_TXF clears the TX FIFO Counter The CLR_TXF bit is always read as zer...

Page 1135: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SPI_TCNT 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIx_TCR field descriptions Field Description 31 16...

Page 1136: ...FMSZ CPOL CPHA LSBFE PCSSCK PASC PDT PBR W Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CSSCK ASC DT BR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIx_CTARn field de...

Page 1137: ...n low power mode disabled inactive state of SCK is not guaranted 0 The inactive state value of SCK is low 1 The inactive state value of SCK is high 25 CPHA Clock Phase Selects which edge of SCK causes...

Page 1138: ...rescaler value is 1 01 Delay after Transfer Prescaler value is 3 10 Delay after Transfer Prescaler value is 5 11 Delay after Transfer Prescaler value is 7 17 16 PBR Baud Rate Prescaler Selects the pre...

Page 1139: ...r Scaler This field is used only in master mode The Delay after Transfer is the time between the negation of the PCS signal at the end of a frame and the assertion of PCS at the beginning of the next...

Page 1140: ...ister In Slave Mode SPIx_CTARn_SLAVE When the module is configured as an SPI bus slave the CTAR0 register is used Address Base address Ch offset 0d i where i 0d to 0d Bit 31 30 29 28 27 26 25 24 23 22...

Page 1141: ...k Phase Selects which edge of SCK causes data to change and which edge causes data to be captured This bit is used in both master and slave mode For successful communication between serial devices the...

Page 1142: ...16 R TCF TXRXS 0 EOQF TFUF 0 TFFF 0 0 0 0 0 RFOF 0 RFDF 0 W w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TXCTR TXNXTPTR RXCTR POPNXTPTR W...

Page 1143: ...eserved This field is reserved This read only field is reserved and always has the value 0 25 TFFF Transmit FIFO Fill Flag Provides a method for the module to request more entries to be added to the T...

Page 1144: ...TXCTR is incremented every time the PUSHR is written The TXCTR is decremented every time an SPI command is executed and the SPI data is transferred to the shift register 11 8 TXNXTPTR Transmit Next Po...

Page 1145: ...ption 31 TCF_RE Transmission Complete Request Enable Enables TCF flag in the SR to generate an interrupt request 0 TCF interrupt requests are disabled 1 TCF interrupt requests are enabled 30 Reserved...

Page 1146: ...e the reset value to this field This field is reserved 22 Reserved Always write the reset value to this field This field is reserved 21 Reserved Always write the reset value to this field This field i...

Page 1147: ...data to be transferred to the TX FIFO An 8 or 16 bit write access transfers all 32 bits to the TX FIFO In Master mode the register transfers 16 bits of data and 16 bits of command information A read a...

Page 1148: ...ware uses this bit to signal to the module that the current SPI transfer is the last in a queue At the end of the transfer the EOQF bit in the SR is set 0 The SPI data is not the last data to transfer...

Page 1149: ...ansferred according to the associated SPI command 45 3 9 POP RX FIFO Register SPIx_POPR POPR is used to read the RX FIFO Eight or sixteen bit read accesses to the POPR have the same effect on the RX F...

Page 1150: ...d contains the command that sets the transfer attributes for the SPI data In Slave mode this field is reserved TXDATA Transmit Data Contains the SPI data to be shifted out 45 3 11 Receive FIFO Registe...

Page 1151: ...frame basis by setting a field in the SPI command See Clock and Transfer Attributes Register In Master Mode SPI_CTARn for information on the fields of CTAR registers Typical master to slave connectio...

Page 1152: ...ode and no transfers are responded to in Slave mode The Stopped state is also a safe state for writing the various configuration registers of the module without causing undetermined results In the Run...

Page 1153: ...transfers initiated by a bus master external to it and the SPI command field space is reserved 45 4 2 1 Master mode In SPI Master mode the module initiates the serial transfers by controlling the SCK...

Page 1154: ...sting of SPI data The number of entries in the TX FIFO is device specific SPI data is added to the TX FIFO by writing to the Data Field of module PUSH FIFO Register PUSHR TX FIFO entries can only be r...

Page 1155: ...nism The RX FIFO functions as a buffer for data received on the SIN pin The RX FIFO holds 4 received SPI data frames The number of entries in the RX FIFO is device specific SPI data is added to the RX...

Page 1156: ...ries from the RX FIFO by reading the module POP RX FIFO Register POPR A read of the POPR decrements the RX FIFO Counter by one Attempts to pop data from an empty RX FIFO are ignored and the RX FIFO Co...

Page 1157: ...equency used to drive this module in the device 45 4 3 2 PCS to SCK Delay tCSC The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edge See Figure 45 6 for an...

Page 1158: ...between negation of the PCS signal for a frame and the assertion of the PCS signal for the next frame See Figure 45 6 for an illustration of the Delay after Transfer The PDT and DT fields in the CTAR...

Page 1159: ...PCSSCK field in the CTAR based on the following formula P At the end of the transfer the delay between PCSS negation and PCS negation is selected by the PASC field in the CTAR based on the following...

Page 1160: ...the bus slave does not control the SCK signal in Slave mode the values of CPOL and CPHA must be identical to the master device settings to ensure proper transmission In SPI Slave mode only CTAR0 is u...

Page 1161: ...ster initiates the transfer by placing its first data bit on the SOUT pin and asserting the appropriate peripheral chip select signals to the slave device The slave responds by placing its first data...

Page 1162: ...5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first LSBFE 1 LSB Figure 45 7 Module transfer timing diagram MTFE 0 CPHA 1 FMSZ 8 The master initiates the transfer by asserting the PCS signal to the slave After the tC...

Page 1163: ...s ratio is below four the master changes SOUT at odd numbered SCK edge The point where the master samples the SIN is selected by the DSPI_MCR SMPL_PT field The master sample point can be delayed by on...

Page 1164: ...fsys represents the protocol clock frequency from which the Baud frequency fsck is derived 2n 2 DSPI samples SIN SMPL_PT 0 D0 D1 D2 Dn D0 D1 D2 Dn D0 D1 D2 Dn sys clk PCS SCK SOUT D1 D0 D2 Dn Tcsc Tvd...

Page 1165: ...following figures show the Modified Transfer Format for CPHA 1 Only the condition where CPOL 0 is shown At the start of a transfer the DSPI asserts the PCS signal to the slave device After the PCS to...

Page 1166: ...correct operations while receiving unequal length frames If PUSHR CONT is also set for back to back frame transfer also configure the frame size of the first frame as less than or equal to the frame...

Page 1167: ...y transfer Other peripherals must remain selected between several sequential serial transfers The Continuous Selection Format provides the flexibility to handle the following case The Continuous Selec...

Page 1168: ...he timing diagram for two four bit transfers with CPHA 1 and CONT 1 PCS Master SIN tCSC PCS to SCK de l ay t ASC After SCK delay SCK CPOL 0 SCK CPOL 1 Master SOUT tCSC t ASC tCSC Figure 45 15 Example...

Page 1169: ...s empty the slave is deselected for any further serial communication otherwise an underflow error occurs 45 4 5 Continuous Serial Communications Clock The module provides the option of generating a Co...

Page 1170: ...e initiating transfer PCS Master SIN SCK CPOL 0 SCK CPOL 1 Master SOUT tDT Figure 45 16 Continuous SCK Timing Diagram CONT 0 If the CONT bit in the TX FIFO entry is set PCS remains asserted between th...

Page 1171: ...SCK edge of each frame defined by frame size programmed to the CTAR0 1 register Then the data from the buffer is transferred to the RXFIFO or DDR register If the SS negates before that last SCK edge t...

Page 1172: ...OQF_RE and the EOQ bit in the executing SPI command is 1 The module generates the interrupt request when the last bit of the SPI frame with EOQ bit set is transmitted 45 4 7 2 Transmit FIFO Fill Inter...

Page 1173: ...FIFO Drain Request is generated when the number of entries in the RX FIFO is not zero and the RFDF_RE bit in the RSER is set The RFDF_DIRS bit in the RSER selects whether a DMA request or an interrup...

Page 1174: ...said to have entered Module Disable Mode This also puts the module in STOPPED state The SR TXRXS bit is cleared to indicate STOPPED state If implemented the Clock Enable signal can stop the clock to t...

Page 1175: ...e request bits in the DMA Controller 6 Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the RXCNT in SR or by checking RFDF in the SR after each read operati...

Page 1176: ...the baud rate scaler BR in the CTARs The values calculated assume a 100 MHz protocol frequency and the double baud rate DBR bit is cleared NOTE The clock frequency mentioned above is given as an examp...

Page 1177: ...uency used to drive this module in the device Table 45 13 Delay values Delay prescaler values 1 3 5 7 Delay scaler values 2 20 0 ns 60 0 ns 100 0 ns 140 0 ns 4 40 0 ns 120 0 ns 200 0 ns 280 0 ns 8 80...

Page 1178: ...illustration but the concepts carry over See Transmit First In First Out TX FIFO buffering mechanism and Receive First In First Out RX FIFO buffering mechanism for details on the FIFO operation Push...

Page 1179: ...emory address of the first in entry in the RX FIFO is computed by the following equation The memory address of the last in entry in the RX FIFO is computed by the following equation RX FIFO Base Base...

Page 1180: ...Initialization application information K22F Sub Family Reference Manual Rev 4 08 2016 1180 NXP Semiconductors...

Page 1181: ...can be connected are limited by a maximum bus capacitance of 400 pF The I2C module also complies with the System Management Bus SMBus Specification version 2 46 1 1 Features The I2C module has the fol...

Page 1182: ...is the basic mode of operation To conserve power in this mode disable the module Wait mode The module continues to operate when the core is in Wait mode and can provide a wakeup interrupt Stop mode Th...

Page 1183: ...Figure 46 1 I2C Functional block diagram 46 2 I2C signal descriptions The signal properties of I2C are shown in the table found here Table 46 1 I2C signal descriptions Signal Description I O SCL Bidi...

Page 1184: ...4006_600A I2C SCL Low Timeout Register High I2C0_SLTH 8 R W 00h 46 3 11 1195 4006_600B I2C SCL Low Timeout Register Low I2C0_SLTL 8 R W 00h 46 3 12 1196 4006_7000 I2C Address Register 1 I2C1_A1 8 R W...

Page 1185: ...4 3 2 1 0 Read MULT ICR Write Reset 0 0 0 0 0 0 0 0 I2Cx_F field descriptions Field Description 7 6 MULT Multiplier Factor Defines the multiplier factor mul This factor is used along with the SCL divi...

Page 1186: ...value For example if the I2C module clock speed is 8 MHz the following table shows the possible hold time values with different ICR and MULT selections to achieve an I2C baud rate of 100 kbit s MULT I...

Page 1187: ...te if FACK is cleared or the current receiving byte if FACK is set 1 No acknowledge signal is sent to the bus on the following receiving data byte if FACK is cleared or the current receiving data byte...

Page 1188: ...I2C data register in transmit mode 0 Transfer in progress 1 Transfer complete 6 IAAS Addressed As A Slave This bit is set by one of the following conditions The calling address matches the programmed...

Page 1189: ...y writing 1 to it such as in the interrupt routine One of the following events can set this bit One byte transfer including ACK NACK bit completes if FACK is 0 An ACK or NACK is sent on the bus by wri...

Page 1190: ...the Data register does not initiate the receive Reading the Data register returns the last byte received while the I2C module is configured in master receive or slave receive mode The Data register do...

Page 1191: ...ters When this bit is set a slave address matching occurs for any address greater than the value of the A1 register and less than or equal to the value of the RA register 0 Range mode disabled No addr...

Page 1192: ...he MCU wakes from the stop mode 0 Stop holdoff is disabled The MCU s entry to stop mode is not gated 1 Stop holdoff is enabled 6 STOPF I2C Bus Stop Detect Flag Hardware sets this bit when the I2C bus...

Page 1193: ...boundary in the range matching mode 0 Reserved This field is reserved This read only field is reserved and always has the value 0 46 3 9 I2C SMBus Control and Status register I2Cx_SMB NOTE When the S...

Page 1194: ...ICAEN Second I2C Address Enable Enables or disables SMBus device default address 0 I2C address register 2 matching is disabled 1 I2C address register 2 matching is enabled 4 TCKSEL Timeout Counter Clo...

Page 1195: ...D 0 Write Reset 1 1 0 0 0 0 1 0 I2Cx_A2 field descriptions Field Description 7 1 SAD SMBus Address Contains the slave address used by the SMBus This field is used on the device default address or othe...

Page 1196: ...ses a serial data line SDA and a serial clock line SCL for data transfers All devices connected to it must have open drain or open collector outputs A logic AND function is exercised on both lines wit...

Page 1197: ...a high to low transition of SDA while SCL is high This signal denotes the beginning of a new data transfer each data transfer might contain several bytes of data and brings all slaves out of their idl...

Page 1198: ...ch is signaled from the receiving device by pulling SDA low at the ninth clock In summary one complete data transfer needs nine clock pulses If the slave receiver does not acknowledge the master in th...

Page 1199: ...is case the transition from master to slave mode does not generate a STOP condition Meanwhile hardware sets a status bit to indicate the loss of arbitration 46 4 1 7 Clock synchronization Because wire...

Page 1200: ...low a slave can drive SCL low for the required period and then release it If the slave s SCL low period is greater than the master s SCL low period the resulting SCL bus signal s low period is stretc...

Page 1201: ...76 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896...

Page 1202: ...rst 7 bits 11110 AD10 AD9 R W 0 A1 Slave address second byte AD 8 1 A2 Data A Data A A P After the master transmitter has sent the first byte of the 10 bit address the slave receiver sees an I2C inter...

Page 1203: ...hing process It provides a 7 bit address If the ADEXT bit is set AD 10 8 in Control Register 2 participates in the address matching process It extends the I2C primary slave address to a 10 bit address...

Page 1204: ...ion and be able to receive a new START condition within the timeframe of TTIMEOUT MAX SMBus defines a clock low timeout TTIMEOUT of 35 ms specifies TLOW SEXT as the cumulative clock low extend time fo...

Page 1205: ...meout intervals TLOW SEXT and TLOW MEXT When in master mode the I2C module must not cumulatively extend its clock cycles for a period greater than TLOW MEXT within a byte where each byte is defined as...

Page 1206: ...ys to acknowledge its own address as a mechanism to detect the presence of a removable device such as a battery or docking station on the bus In addition to indicating a slave device busy condition SM...

Page 1207: ...AAS IICIF IICIE Arbitration lost ARBL IICIF IICIE I2C bus stop detection STOPF IICIF IICIE SSIE I2C bus start detection STARTF IICIF IICIE SSIE SMBus SCL low timeout SLTF IICIF IICIE SMBus SCL high SD...

Page 1208: ...o or more masters try to control the bus at the same time the relative priority of the contending masters is determined by a data arbitration procedure The I2C module asserts the arbitration lost inte...

Page 1209: ...odule The width of the glitch to absorb can be specified in terms of the number of half I2C module clock cycles A single Programmable Input Glitch Filter control register is provided Effectively any d...

Page 1210: ...mode NOTE After I2C address matching wake up the master must wait a time long enough for the slave ISR to finish running and resend start or repeat start signals For the SRW bit to function properly...

Page 1211: ...les used to achieve the routine shown in the following figure Module Initialization Master 1 Write Frequency Divider register to set the I2C baud rate see example in description of ICR 2 Write Control...

Page 1212: ...n I2C driver which implements many of the steps described here is available in AN4342 Using the Inter Integrated Circuit on ColdFire and Kinetis Initialization application information K22F Sub Family...

Page 1213: ...Notes 1 If general call is enabled check to determine if the received address is a general call address 0x00 If the received address is a general call address the general call must be handled by user...

Page 1214: ...data to Data reg Clear IICIF Notes 1 If general call or SIICAEN is enabled check to determine if the received address is a general call address 0x00 or an SMBus device default address In either case t...

Page 1215: ...atures Full duplex operation Standard mark space non return to zero NRZ format Selectable IrDA 1 4 return to zero inverted RZI format with programmable pulse width 13 bit baud rate selection with 32 f...

Page 1216: ...e retry threshold Support for 11 and 12 ETU transfers Detection of initial packet and automated transfer parameter programming Interrupt driven operation with seven ISO 7816 specific interrupts Wait t...

Page 1217: ...ormal mode of operation 47 1 2 2 Wait mode UART operation in the Wait mode depends on the state of the C1 UARTSWAI field If C1 UARTSWAI is cleared and the CPU is in Wait mode the UART operates normall...

Page 1218: ...reception and resets the UART Entering or leaving Stop mode does not initiate any power down or power up procedures for the ISO 7816 smartcard interface 47 2 UART signal descriptions The UART signals...

Page 1219: ...ate TXD O Transmit data Serial data output from transmitter State meaning Whether TXD is interpreted as a 1 or 0 depends on the bit encoding method along with other configuration settings Timing Drive...

Page 1220: ...s UART0_PFIFO 8 R W See section 47 3 16 1242 4006_A011 UART FIFO Control Register UART0_CFIFO 8 R W 00h 47 3 17 1243 4006_A012 UART FIFO Status Register UART0_SFIFO 8 R W C0h 47 3 18 1244 4006_A013 UA...

Page 1221: ...rs High UART1_BDH 8 R W 00h 47 3 1 1224 4006_B001 UART Baud Rate Registers Low UART1_BDL 8 R W 04h 47 3 2 1225 4006_B002 UART Control Register 1 UART1_C1 8 R W 00h 47 3 3 1226 4006_B003 UART Control R...

Page 1222: ...Register UART1_WN7816 8 R W 00h 47 3 27 1252 4006_B01D UART 7816 Wait FD Register UART1_WF7816 8 R W 01h 47 3 28 1253 4006_B01E UART 7816 Error Threshold Register UART1_ET7816 8 R W 00h 47 3 29 1253 4...

Page 1223: ...r UART2_ED 8 R 00h 47 3 13 1239 4006_C00D UART Modem Register UART2_MODEM 8 R W 00h 47 3 14 1240 4006_C00E UART Infrared Register UART2_IR 8 R W 00h 47 3 15 1241 4006_C010 UART FIFO Parameters UART2_P...

Page 1224: ...16B_T0 8 R W 14h 47 3 35 1257 4006_C03D UART 7816 Wait Parameter Register B UART2_WP7816B_T1 8 R W 14h 47 3 36 1257 4006_C03E UART 7816 Wait and Guard Parameter Register UART2_WGP7816_T1 8 R W 06h 47...

Page 1225: ...a in a temporary location until BDL is written 47 3 2 UART Baud Rate Registers Low UARTx_BDL This register along with the BDH register controls the prescale divisor for UART baud rate generation To up...

Page 1226: ...y connected to receiver input The receiver input is determined by RSRC 6 UARTSWAI UART Stops in Wait Mode 0 UART clock continues to run in Wait mode 1 UART clock freezes while CPU is in Wait mode 5 RS...

Page 1227: ...starts after start bit 1 Idle character bit count starts after stop bit 1 PE Parity Enable Enables the parity function When parity is enabled parity function inserts a parity bit in the bit position...

Page 1228: ...s the UART transmitter TE can be used to queue an idle preamble by clearing and then setting TE When C7816 ISO_7816E is set enabled and C7816 TTYPE 1 this field is automatically cleared after the requ...

Page 1229: ...atus of its fields To clear a flag the status register should be read followed by a read or write to D register depending on the interrupt flag type Other instructions can be executed between the two...

Page 1230: ...Writing to D to transmit new data Queuing a preamble by clearing and then setting C2 TE Queuing a break character by writing 1 to SBK in C2 0 Transmitter active sending data a preamble or a break 1 Tr...

Page 1231: ...put NF does not become set in the case of an overrun or while the LIN break detect feature is enabled S2 LBKDE 1 When NF is set it indicates only that a dataword has been received with noise since the...

Page 1232: ...0 0 0 0 0 UARTx_S2 field descriptions Field Description 7 LBKDIF LIN Break Detect Interrupt Flag LBKDIF is set when LBKDE is set and a LIN break character is detected on the receiver input The LIN br...

Page 1233: ...AKE is cleared this field controls whether the idle character that wakes the receiver sets S1 IDLE This field must be cleared when C7816 ISO7816E is set enabled 0 S1 IDLE is not set upon detection of...

Page 1234: ...mat that is if C1 M 1 or C4 M10 1 NOTE If the value of T8 is the same as in the previous transmission T8 does not have to be rewritten The same value is transmitted until T8 is rewritten To correctly...

Page 1235: ...IE Overrun Error Interrupt Enable Enables the overrun error flag S1 OR to generate interrupt requests 0 OR interrupts are disabled 1 OR interrupt requests are enabled 2 NEIE Noise Error Interrupt Enab...

Page 1236: ...ue written by the last write to C3 T8 gets stored in the C3 T8 register Address Base address 7h offset Bit 7 6 5 4 3 2 1 0 Read RT Write Reset 0 0 0 0 0 0 0 0 UARTx_D field descriptions Field Descript...

Page 1237: ...sferred to the data buffer if MAEN2 is cleared 1 All data received with the most significant bit cleared is discarded All data received with the most significant bit set is compared with contents of M...

Page 1238: ...ansmitter DMA Select Configures the transmit data register empty flag S1 TDRE to generate interrupt or DMA requests if C2 TIE is set NOTE If C2 TIE is cleared TDRE DMA and TDRE interrupt request signa...

Page 1239: ...rd was received The importance of this data varies with the application and in some cases maybe completely optional These fields automatically update to reflect the conditions of the next dataword whe...

Page 1240: ...t to send enable Allows the RTS output to control the CTS input of the transmitting device to prevent receiver overrun NOTE Do not set both RXRTSE and TXRTSE 0 The receiver has no effect on RTS 1 RTS...

Page 1241: ...acter If CTS is asserted the character is sent If CTS is deasserted the signal TXD remains in the mark state and transmission is delayed until CTS is asserted Changes in CTS as a character is being se...

Page 1242: ...FO Enable When this field is set the built in FIFO structure for the transmit buffer is enabled The size of the FIFO structure is indicated by TXFIFOSIZE If this field is not set the transmit buffer o...

Page 1243: ...ve FIFO Buffer depth 32 datawords 101 Receive FIFO Buffer depth 64 datawords 110 Receive FIFO Buffer depth 128 datawords 111 Reserved 47 3 17 UART FIFO Control Register UARTx_CFIFO This register provi...

Page 1244: ...e an interrupt to the host 1 TXOF flag generates an interrupt to the host 0 RXUFE Receive FIFO Underflow Interrupt Enable When this field is set the RXUF flag generates an interrupt to the host 0 RXUF...

Page 1245: ...r an interrupt will be issued to the host only if CFIFO TXOFE is set This flag is cleared by writing a 1 0 No transmit buffer overflow has occurred since the last time the flag was cleared 1 At least...

Page 1246: ...ARTx_TCFIFO field descriptions Field Description TXCOUNT Transmit Counter The value in this register indicates the number of datawords that are in the transmit FIFO buffer If a dataword is being trans...

Page 1247: ...XCOUNT Receive Counter The value in this register indicates the number of datawords that are in the receive FIFO buffer If a dataword is being received that is in the receive shift register it is not...

Page 1248: ...a valid initial character If an invalid initial character is identified and ANACK is set a NACK is sent All received data is discarded and error flags blocked S1 NF S1 OR S1 FE S1 PF IS7816 WT IS7816...

Page 1249: ...T does not result in the generation of an interrupt 1 The assertion of IS7816 BWT results in the generation of an interrupt 4 INITDE Initial Character Detected Interrupt Enable 0 The assertion of IS78...

Page 1250: ...g transmitted and the leading edge of the next response character has exceeded the programmed value This flag asserts only when C7816 TTYPE 0 This interrupt is cleared by writing 1 0 Wait time WT has...

Page 1251: ...ternal NACK detection counter is cleared and the count restarts from zero on the next received NACK This interrupt is cleared by writing 1 0 The number of retries and corresponding NACKS does not exce...

Page 1252: ...sed only when C7816 TTYPE 1 See Wait time and guard time parameters 47 3 27 UART 7816 Wait N Register UARTx_WN7816 The WN7816 register contains a parameter that is used in the calculation of the guard...

Page 1253: ...be written to only when C7816 ISO_7816E is not set Address Base address 1Eh offset Bit 7 6 5 4 3 2 1 0 Read TXTHRESHOLD RXTHRESHOLD Write Reset 0 0 0 0 0 0 0 0 UARTx_ET7816 field descriptions Field De...

Page 1254: ...Write Reset 0 0 0 0 0 0 0 0 UARTx_TL7816 field descriptions Field Description TLEN Transmit Length This value plus four indicates the number of characters contained in the block being transmitted Thi...

Page 1255: ...n C7816 TTYPE 0 See ATR Duration Time Counter 47 3 32 UART 7816 ATR Duration Timer Register B UARTx_AP7816B_T0 The AP7816B_T0 register contains variables used in the generation of the ATR Duration Tim...

Page 1256: ...Read WI_H Write Reset 0 0 0 0 0 0 0 0 UARTx_WP7816A_T0 field descriptions Field Description WI_H Wait Time Integer High C7816 TTYPE 0 Used to calculate the value used for the WT counter This register...

Page 1257: ...2 1 0 Read WI_L Write Reset 0 0 0 1 0 1 0 0 UARTx_WP7816B_T0 field descriptions Field Description WI_L Wait Time Integer Low C7816 TTYPE 0 Used to calculate the value used for the WT counter This regi...

Page 1258: ...I1 BGI Write Reset 0 0 0 0 0 1 1 0 UARTx_WGP7816_T1 field descriptions Field Description 7 4 CWI1 Character Wait Time Integer 1 C7816 TTYPE 1 Used to calculate the value used for the CWT counter It re...

Page 1259: ...4 Functional description This section provides a complete functional description of the UART block The UART allows full duplex asynchronous NRZ serial communication between the CPU and remote devices...

Page 1260: ...xD IRQ DMA LOGIC INFRARED LOGIC DMA Requests IRQ Requests TxD LOOP CONTROL LOOPS RSRC UART DATA REGISTER UART_D Figure 47 1 Transmitter Block Diagram 47 4 1 1 Transmitter character length The UART tra...

Page 1261: ...the value indicated by TWFIFO TXWATER The transmit driver routine may respond to this flag by writing additional datawords to the transmit buffer using C3 T8 D as space permits See Application informa...

Page 1262: ...ers the idle state even if there is data pending in the UART transmit data buffer To ensure that all the data written in the FIFO is transmitted on the link before clearing C2 TE wait for S1 TC to set...

Page 1263: ...g C2 TE during a transmission queues an idle character to be sent after the dataword currently being transmitted Note When queuing an idle character the idle character will be transmitted following th...

Page 1264: ...remains asserted for the whole time that the transmitter data buffer has any characters RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely...

Page 1265: ...buffer write CTS_B RTS_B C1 in transmission 1 1 Cn transmit characters Figure 47 2 Transmitter RTS and CTS timing diagram 47 4 2 Receiver Chapter 47 Universal Asynchronous Receiver Transmitter UART K2...

Page 1266: ...acters The states of C1 M C1 PE and C4 M10 determine the length of data characters When receiving 9 or 10 bit data C3 R8 is the ninth bit bit 8 47 4 2 2 Receiver bit ordering When S2 MSBF is set the r...

Page 1267: ...then a NACK is sent by the receiver If the number of consecutive receive errors exceeds the threshold set by ET7816 RXTHRESHOLD then IS7816 RXT is set and an interrupt generated if IE7816 RXTE is set...

Page 1268: ...takes samples at RT3 RT5 and RT7 when C7816 ISO_7816E is cleared disabled and RT8 RT9 and RT10 when C7816 ISO_7816E is set enabled The following table summarizes the results of the start bit verificat...

Page 1269: ...t bit exists To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 The following table summarizes the results of the stop bit samples In the event that C7816 ISO_78...

Page 1270: ...e sets the noise flag Although the perceived bit time is misaligned the data samples RT8 RT9 and RT10 are within the bit time and data recovery is successful SAMPLES Rx pin input RT CLOCK RT CLOCK COU...

Page 1271: ...ET RT CLOCK 1 1 1 1 0 PERCEIVED AND ACTUAL START BIT LSB RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT2 RT3 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 1 1 1 1 1 1 0 Figure 47...

Page 1272: ...0 were high SAMPLES Rx pin input RT CLOCK RT CLOCK COUNT RESET RT CLOCK 1 1 1 1 0 0 START BIT LSB RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT10 RT1 RT2 RT3 1 1 1 1 1 0 0 1 0 1 RT4 RT5 RT6 RT7 R...

Page 1273: ...LBKDE The UART break character detection threshold depends on C1 M C1 PE S2 LBKDE and C4 M10 See the following table Table 47 7 Receive break character detection threshold LBKDE M M10 PE Threshold bit...

Page 1274: ...iver data buffer is full or is overrun If the receiver request to send functionality is disabled the receiver RTS remains deasserted The following figure shows receiver hardware flow control functiona...

Page 1275: ...a rising edge is not seen then the decoder sends a 1 to the receiver If the next bit is a 0 which arrives late then a low bit is detected according to Low bit detection The value sent to the receiver...

Page 1276: ...cycles The maximum percent difference between the receiver count and the transmitter count of a slow 8 bit data character with no errors is 154 147 154 100 4 54 For a 9 bit data character data samplin...

Page 1277: ...receiver counts 170 RT cycles at the point when the count of the transmitting device is 176 RT cycles 11 bit times 16 RT cycles The maximum percent difference between the receiver count and the transm...

Page 1278: ...rmation and the receivers for which the message is addressed process the frames that follow Any receiver for which a message is not addressed can set its C2 RWU and return to the standby state C2 RWU...

Page 1279: ...nsferred only on a match with either register Address match operation is not supported when C7816 ISO_7816E is set enabled 47 4 3 Baud rate generation A 13 bit modulus counter and a 5 bit fractional f...

Page 1280: ...00 0 14 531 00000 0 19 209 0 1200 6 1200 0 11 1062 00000 0 9604 5 600 3 600 0 05 2125 00000 0 4800 0 300 0 300 0 00 4250 00000 0 2400 0 150 0 150 0 00 5795 00000 0 1760 1 110 0 110 0 00 Table 47 9 Bau...

Page 1281: ...T for 8 bit data characters that is eight bits are memory mapped in D A frame with eight data bits has a total of 10 bits The most significant bit of the eight data bits can be used as an address mark...

Page 1282: ...start and stop bits the 9 data character bits and a tenth internal data bit Note that if C4 M10 is set C1 PE must also be set In this case the tenth bit is the internally generated parity bit The nint...

Page 1283: ...format with parity enabled BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 STOP BIT START BIT START BIT PARITY Figure 47 16 Seven bits of data with LSB first and parity BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 B...

Page 1284: ...TART BIT START BIT BIT 8 ADDRESS MARK Figure 47 23 Nine bits of data with MSB first and parity 47 4 5 Single wire operation Normally the UART uses two pins for transmitting and receiving In single wir...

Page 1285: ...s The ISO 7816 protocol is an NRZ single wire half duplex interface The TxD pin is used in open drain mode because the data signal is used for both transmitting and receiving There are multiple subpro...

Page 1286: ...processor with an interrupt if IE7816 INITDE is set Additionally the UART will alter S2 MSBF C3 TXINV and S2 RXINV automatically based on the initial character The corresponding initial character and...

Page 1287: ...s ETU in length The transmitter must wait for at least two time units ETU after detection of the error signal before attempting to retransmit the character It is assumed that the UART and the device s...

Page 1288: ...nfiguration and violation detection of these settings On reset the wait time IS7816 WT defaults to 9600 ETUs and guard time GT to 12 ETUs These values are controlled by parameters in the WP7816 WN7816...

Page 1289: ...corresponding guard time expiring Table 47 13 Wait and guard time calculations Parameter Reset value ETU C7816 TTYPE 0 ETU C7816 TTYPE 1 ETU Wait time WT 9600 WI 480 Not used Character wait time CWT...

Page 1290: ...his feature is only supported in T 0 mode NOTE The ADT counter starts counting on detection of the complete TS Character It must be noted that by this time exactly 10 ETUs have elapsed since the start...

Page 1291: ...ctive low pulses The infrared submodule receives its clock sources from the UART One of these two clocks are selected in the infrared submodule to generate either 3 16 1 16 1 32 or 1 4 narrow pulses d...

Page 1292: ...lso outlines additional details regarding the RXEDGIF interrupt because of its complexity of operation Any of the UART interrupt requests listed in the table can be used to bring the CPU out of Wait m...

Page 1293: ...ring the next cycle A rising edge is detected when the input is seen as a logic 0 during one module clock cycle and then a logic 1 during the next cycle 47 6 1 2 Clearing RXEDGIF interrupt request Wri...

Page 1294: ...to program the UART for ISO 7816 operation Elements such as procedures to power up or power down the smartcard and when to take those actions are beyond the scope of this description To set up the UA...

Page 1295: ...the software must write to set C2 RE 0 and C2 TE 0 The software should then adjust 7816 specific and UART generic parameters to match and configure data that was received during the answer on reset pe...

Page 1296: ...eeded with sufficient urgency to ensure that the block wait time and character wait times are not violated 47 8 3 Initialization sequence non ISO 7816 To initiate a UART transmission 1 Configure the U...

Page 1297: ...g and then setting C2 TE 4 Write the first and subsequent datawords of the second message to C3 T8 D 47 8 4 Overrun OR flag implications To be flexible the overrun flag OR operates slight differently...

Page 1298: ...vior is intended to allow the software sufficient time to read the LIN break character from the data buffer to ensure that a break character was actually detected The checking of the break character w...

Page 1299: ...ceiver is necessary if the required voltage levels of the communication link do not match the voltage levels of the UART s RTS and CTS signals TRANSMITTER UART RECEIVER TRANSMITTER UART RECEIVER TXD C...

Page 1300: ...3 16 of a bit time results in a pulse width of 1 6 s 47 8 9 Clearing 7816 wait timer WT BWT CWT interrupts The 7816 wait timer interrupts associated with IS7816 WT IS7816 BWT and IS7816 CWT will autom...

Page 1301: ...e considered 1 Various reserved registers and register bits are used such as MSFB and M10 2 This module now generates an error when invalid address spaces are used 3 While documentation indicated othe...

Page 1302: ...Application information K22F Sub Family Reference Manual Rev 4 08 2016 1302 NXP Semiconductors...

Page 1303: ...pports operation in Stop modes Interrupt DMA or polled operation Transmit data register empty and transmission complete Receive data register full Receive overrun parity error framing error and noise...

Page 1304: ...op mode provided the asynchronous transmit and receive clock remains enabled The LPUART can generate an interrupt or DMA request to cause a wakeup from Stop mode 48 1 2 2 Wait mode The LPUART can be c...

Page 1305: ...Control Shift Enable Preamble All 1s Break All 0s LPUART Controls TxD TxD Direction TO TxD Pin Logic Loop Control To Receive Data In To TxD Pin Tx Interrupt Request LOOPS RSRC TIE TC TDRE M PT PE TCIE...

Page 1306: ...s to an address outside the valid memory map will generate a bus error LPUART memory map Absolute address hex Register name Width in bits Access Reset value Section page 4002_A000 LPUART Baud Rate Reg...

Page 1307: ...transmission This bit should only be changed when the transmitter and receiver are both disabled 0 Receiver and transmitter use 8 bit or 9 bit data characters 1 Receiver and transmitter use 10 bit dat...

Page 1308: ...mples input data using the rising and falling edge of the baud rate clock 16 RESYNCDIS Resynchronization Disable When set disables the resynchronization of the received data word when a data one follo...

Page 1309: ...t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R LBKDIF RXEDGIF MSBF RXINV RWUID BRK13 LBKDE RAF TDRE TC RDRF IDLE OR NF FE PF W w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Bi...

Page 1310: ...Receive data not inverted 1 Receive data inverted 27 RWUID Receive Wake Up Idle Detect For RWU on idle character RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit...

Page 1311: ...smitter active sending data a preamble or a break 1 Transmitter idle transmission activity complete 21 RDRF Receive Data Register Full Flag RDRF is set when the receive buffer LPUART_DATA is full To c...

Page 1312: ...ext character to be read from LPUART_DATA was received with noise detected within the character To clear NF write logic one to the NF 0 No noise detected 1 Noise detected in the received character in...

Page 1313: ...rmats When reading 9 bit or 10 bit data read R8 before reading LPUART_DATA T9 is the tenth data bit received when the LPUART is configured for 10 bit data formats When writing 10 bit data write T9 bef...

Page 1314: ...OR is set 26 NEIE Noise Error Interrupt Enable This bit enables the noise flag NF to generate hardware interrupt requests 0 NF interrupts disabled use polling 1 Hardware interrupt requested when NF i...

Page 1315: ...lly clears when an RWU event occurs that is an IDLE event when CTRL WAKE is clear or an address match when CTRL WAKE is set with STAT RWUID is clear NOTE RWU must be set only with CTRL WAKE 0 wakeup o...

Page 1316: ...Loop mode or single wire mode where transmitter outputs are internally connected to receiver input see RSRC bit 6 DOZEEN Doze Enable 0 LPUART is enabled in Doze mode 1 LPUART is disabled in Doze mode...

Page 1317: ...tomatically shifted after a received stop bit therefore resetting the idle count 0 Idle character bit count starts after start bit 1 Idle character bit count starts after stop bit 1 PE Parity Enable E...

Page 1318: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NOISY PARITYE FRETSC RXEMPT IDLINE 0 R9T9 R8T8 R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 W Reset 0 0 0 1 0 0 0 0 0 0 0 0 0...

Page 1319: ...ty data returned on read is not valid 11 IDLINE Idle Line Indicates the receiver line was idle before receiving the character in DATA 9 0 Unlike the IDLE flag this bit can set for the first character...

Page 1320: ...MAEN bit is clear 15 10 Reserved This field is reserved This read only field is reserved and always has the value 0 MA1 Match Address 1 The MA1 and MA2 registers are compared to input data addresses w...

Page 1321: ...ansmitter is idle 3 RXRTSE Receiver request to send enable Allows the RTS output to control the CTS input of the transmitting device to prevent receiver overrun NOTE Do not set both RXRTSE and TXRTSE...

Page 1322: ...ges in CTS as a character is being sent do not affect its transmission 48 3 Functional description The LPUART supports full duplex asynchronous NRZ serial communication and comprises a baud rate gener...

Page 1323: ...able in the transmit data buffer Programs store data into the transmit data buffer by writing to the LPUART data register The central element of the LPUART transmitter is the transmit shift register t...

Page 1324: ...r LPUART_STAT FE 1 occurs A break character can also be transmitted by writing to the LPUART_DATA register with bit 13 set and the data bits clear This supports transmitting the break character as par...

Page 1325: ...te of CTS The transmitter s CTS signal can also be enabled even if the same LPUART receiver s RTS signal is disabled 48 3 2 3 Transceiver driver enable The transmitter can use LPUART_RTS as an enable...

Page 1326: ...the receive data register and the receive data register full LPUART_STAT RDRF status flag is set If LPUART_STAT RDRF was already set indicating the receive data register buffer was already full the o...

Page 1327: ...ization has been disabled This improves the reliability of the receiver in the presence of noise or mismatched baud rates It does not improve worst case analysis because some characters do not have an...

Page 1328: ...haracters 0 1 10 X1 Address match on and address match off IDLE flag set for discarded characters 48 3 3 2 1 Idle line wakeup When wake is cleared the receiver is configured for idle line wakeup In th...

Page 1329: ...ets the LPUART_STAT RDRF flag In this case the character with the MSB set is received even though the receiver was sleeping during most of this character time 48 3 3 2 3 Data match wakeup When LPUART_...

Page 1330: ...address and is compared with the associated MA1 or MA2 register The character is only transferred to the receive buffer and LPUART_STAT RDRF is set if the comparison matches All subsequent characters...

Page 1331: ...To support hardware flow control the receiver can be programmed to automatically deassert and assert LPUART_RTS LPUART_RTS remains asserted until the transfer is complete even if the transmitter is d...

Page 1332: ...of the infrared decoder counter are ignored by the decoder Any pulses less than one oversampling baud clock can be undetected by it regardless of whether it is seen in the first or second half of the...

Page 1333: ...time data is transferred from LPUART_DATA 7 0 to the shifter The 9 bit data mode is typically used with parity to allow eight bits of data plus the parity in the ninth bit or it is used with address...

Page 1334: ...nnected to the transmitter output and to the LPUART_TX pin the LPUART_RX pin is not used In single wire mode the LPUART_CTRL TXDIR bit controls the direction of serial data on the LPUART_TX pin When L...

Page 1335: ...is sent at the start of the bit with a duration of 1 OSR 2 OSR 3 OSR or 4 OSR of a bit time A narrow low pulse is transmitted for a zero bit when LPUART_CTRL TXINV is cleared while a narrow high puls...

Page 1336: ...After LPUART_STAT IDLE has been cleared it cannot become set again until the receiver has received at least one new character and has set LPUART_STAT RDRF If the associated error was detected in the...

Page 1337: ...he chip specific information in the first section of this chapter Transmitter with independent bit clock and frame sync supporting 1 data line Receiver with independent bit clock and frame sync suppor...

Page 1338: ...es of operation The module operates in these power modes Run mode stop modes low leakage modes and Debug mode 49 1 3 1 Run mode In Run mode the SAI transmitter and receiver operate normally 49 1 3 2 S...

Page 1339: ...bit is clear and Debug mode is entered the SAI is disabled after completing the current transmit or receive frame The transmitter and receiver bit clocks are not affected by Debug mode 49 2 External s...

Page 1340: ...Configuration 4 Register I2S0_TCR4 32 R W 0000_0000h 49 3 5 1347 4002_F014 SAI Transmit Configuration 5 Register I2S0_TCR5 32 R W 0000_0000h 49 3 6 1349 4002_F020 SAI Transmit Data Register I2S0_TDR0...

Page 1341: ...SAI Transmit Control Register I2Sx_TCSR Address 4002_F000h base 0h offset 4002_F000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R TE STOPE DBGE BCE 0 0 SR 0 WSF SEF FEF FWF FRF W FR w1c w1c w...

Page 1342: ...en software clears this field the transmit bit clock remains enabled and this bit remains set until the end of the current frame 0 Transmit bit clock is disabled 1 Transmit bit clock is enabled 27 26...

Page 1343: ...s than or equal to the transmit FIFO watermark 0 Transmit FIFO watermark has not been reached 1 Transmit FIFO watermark has been reached 15 13 Reserved This field is reserved This read only field is r...

Page 1344: ...t DMA Enable Enables disables DMA requests 0 Disables the DMA request 1 Enables the DMA request 49 3 2 SAI Transmit Configuration 1 Register I2Sx_TCR1 Address 4002_F000h base 4h offset 4002_F004h Bit...

Page 1345: ...ansmitter BCS field and receiver BCS field must be set to the same value When both are set the transmitter and receiver are both clocked by the transmitter bit clock SAI_TX_BCLK but use the receiver f...

Page 1346: ...irection Configures the direction of the bit clock 0 Bit clock is generated externally in Slave mode 1 Bit clock is generated internally in Master mode 23 8 Reserved This field is reserved This read o...

Page 1347: ...e writing 0 configures the first word in the frame When configured to a value greater than TCR4 FRSZ then the start of word flag is never set 49 3 5 SAI Transmit Configuration 4 Register I2Sx_TCR4 Thi...

Page 1348: ...of words in each frame The value written must be one less than the number of words in the frame For example write 0 for one word per frame The maximum supported frame size is 16 words 15 13 Reserved...

Page 1349: ...ept the first in the frame The value written must be one less than the number of bits per word Word width of less than 8 bits is not supported 23 21 Reserved This field is reserved This read only fiel...

Page 1350: ...set before accessing the channel s transmit data register Writes to this register when the transmit FIFO is not full will push the data written into the transmit data FIFO Writes to this register whe...

Page 1351: ...the masked words in each frame to change from frame to frame Address 4002_F000h base 60h offset 4002_F060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R...

Page 1352: ...nable Enables disables the receiver When software clears this field the receiver remains enabled and this bit remains set until the end of the current frame 0 Receiver is disabled 1 Receiver is enable...

Page 1353: ...reset 24 SR Software Reset Resets the internal receiver logic including the FIFO pointers Software visible registers are not affected except for the status registers 0 No effect 1 Software reset 23 2...

Page 1354: ...disables sync error interrupts 0 Disables interrupt 1 Enables interrupt 10 FEIE FIFO Error Interrupt Enable Enables disables FIFO error interrupts 0 Disables the interrupt 1 Enables the interrupt 9 F...

Page 1355: ...ns Field Description 31 3 Reserved This field is reserved This read only field is reserved and always has the value 0 RFW Receive FIFO Watermark Configures the watermark level for all enabled receiver...

Page 1356: ...he clock was externally generated This has the effect of decreasing the data input setup time but increasing the data output valid time The slave mode timing from the datasheet should be used for the...

Page 1357: ...reserved and always has the value 0 23 17 Reserved This field is reserved This read only field is reserved and always has the value 0 16 RCE Receive Channel Enable Enables the corresponding data chan...

Page 1358: ...e word that caused the FIFO error to set after the FIFO warning flag has been cleared 27 26 Reserved This field is reserved This read only field is reserved and always has the value 0 25 24 FPACK FIFO...

Page 1359: ...value 0 4 MF MSB First Configures whether the LSB or the MSB is received first 0 LSB is received first 1 MSB is received first 3 FSE Frame Sync Early 0 Frame sync asserts with the first bit of the fr...

Page 1360: ...t supported if there is only one word per frame 15 13 Reserved This field is reserved This read only field is reserved and always has the value 0 12 8 FBT First Bit Shifted Configures the bit index fo...

Page 1361: ...0d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 WFP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 RFP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2Sx...

Page 1362: ...d and not written to receive FIFO for the corresponding word in the frame 0 Word N is enabled 1 Word N is masked 49 3 19 SAI MCLK Control Register I2Sx_MCR The MCLK Control Register MCR controls the c...

Page 1363: ...ivider input clock 2 is selected 11 MCLK divider input clock 3 is selected Reserved This field is reserved This read only field is reserved and always has the value 0 49 3 20 SAI MCLK Divide Register...

Page 1364: ...master clock The audio master clock is used to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock The transmitter and receiver can independentl...

Page 1365: ...divide ratios and will approach 50 50 for large non integer divide ratios There is no cycle to cycle jitter or duty cycle variance when the divide ratio is an integer or half integer otherwise the div...

Page 1366: ...The SAI is asynchronously reset on system reset The SAI has a software reset and a FIFO reset 49 4 2 1 Software reset The SAI transmitter includes a software reset that resets all transmitter internal...

Page 1367: ...mode the receiver is enabled only when both the transmitter and receiver are enabled It is recommended that the transmitter is the last enabled and the first disabled If the receiver bit clock and fr...

Page 1368: ...Assert with the first bit in frame or asserts one bit early Assert for a duration between 1 bit clock and the first word length Frame length from 1 to 16 words per frame Word length to support 8 to 3...

Page 1369: ...8 bit writes should only be used when transmitting up to 8 bit data and 16 bit writes should only be used when transmitting up to 16 bit data Writes to a TDR are ignored if the corresponding bit of T...

Page 1370: ...ransmit shift register is loaded at the start of each frame and after every second unmasked transmit word The first word transmitted is taken from 16 bit word at byte offset 0 first bit is selected by...

Page 1371: ...1 FIFO request flag The FIFO request flag is set based on the number of entries in the FIFO and the FIFO watermark configuration The transmit FIFO request flag is set when the number of entries in an...

Page 1372: ...a is transmitted in the correct order the transmitter will continue from the same word number in the frame that caused the FIFO to underflow but only after new data has been written to the transmit FI...

Page 1373: ...flag is set the transmitter or receiver continues checking for frame sync assertion when idle or at the end of each frame The sync error flag can generate an interrupt only 49 4 7 5 Word start flag Th...

Page 1374: ...Functional description K22F Sub Family Reference Manual Rev 4 08 2016 1374 NXP Semiconductors...

Page 1375: ...orresponding Port Control and Interrupt module for that pin is enabled Efficient bit manipulation of the general purpose outputs is supported through the addition of set clear and toggle write only re...

Page 1376: ...rt are implemented on each device See the chapter on signal multiplexing for the number of GPIO ports available in the device 50 1 3 1 Detailed signal description Table 50 3 GPIO interface detailed si...

Page 1377: ...ear Output Register GPIOA_PCOR 32 W always reads 0 0000_0000h 50 2 3 1380 400F_F00C Port Toggle Output Register GPIOA_PTOR 32 W always reads 0 0000_0000h 50 2 4 1380 400F_F010 Port Data Input Register...

Page 1378: ...lways reads 0 0000_0000h 50 2 3 1380 400F_F0CC Port Toggle Output Register GPIOD_PTOR 32 W always reads 0 0000_0000h 50 2 4 1380 400F_F0D0 Port Data Input Register GPIOD_PDIR 32 R 0000_0000h 50 2 5 13...

Page 1379: ...gured for general purpose output 1 Logic level 1 is driven on pin provided pin is configured for general purpose output 50 2 2 Port Set Output Register GPIOx_PSOR This register configures whether to s...

Page 1380: ...in PDORn does not change 1 Corresponding bit in PDORn is cleared to logic 0 50 2 4 Port Toggle Output Register GPIOx_PTOR Address Base address Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 1381: ...rrupt module is disabled then the corresponding bit in PDIR does not update 0 Pin logic level is logic 0 or is not configured for use by digital function 1 Pin logic level is logic 1 50 2 6 Port Data...

Page 1382: ...ion registers provided the pin is configured for the GPIO function The following table depicts the conditions for a pin to be configured as input output If Then A pin is configured for the GPIO functi...

Page 1383: ...ot in test mode Testing is performed via a boundary scan technique as defined in the IEEE 1149 1 2001 standard All data input to and output from the JTAGC block is communicated in serial format 51 1 1...

Page 1384: ...at supports several IEEE 1149 1 2001 defined instructions as well as several public and private device specific instructions Refer to Table 51 3 for a list of supported instructions Bypass register bo...

Page 1385: ...struction register while the JTAGC is enabled Supported test instructions include EXTEST HIGHZ CLAMP SAMPLE and SAMPLE PRELOAD Each instruction defines the set of data register s that may operate and...

Page 1386: ...est Clock Input TCK is an input pin used to synchronize the test logic and control register access through the TAP 51 2 2 TDI Test data input Test Data Input TDI is an input pin that receives serial t...

Page 1387: ...st Logic Reset TAP controller states Synchronous entry into the Test Logic Reset state results in the IDCODE instruction being loaded on the falling edge of TCK Asynchronous entry into the Test Logic...

Page 1388: ...ce the PIN mirrors bits 9 0 of the SIM_SDID REVID field Please see the SIM_SDID register description for more detail DC Design Center Indicates the design center Value is 0x2C PIN Part Identification...

Page 1389: ...the selected register starting with the least significant bit as illustrated in the following figure This applies for the instruction register test data registers and the bypass register Selected Reg...

Page 1390: ...T DR EXIT1 DR EXIT1 IR P AUSE DR P AUSE IR EXIT2 IR EXIT2 DR UPDA TE DR UPDA TE IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 51 4 IEEE 1149 1 2001 TAP controller finite st...

Page 1391: ...1149 1 2001 standard for more details All undefined opcodes are reserved Table 51 3 4 bit JTAG instructions Instruction Code 3 0 Instruction summary IDCODE 0000 Selects device identification register...

Page 1392: ...AD instruction has two functions The SAMPLE portion of the instruction obtains a sample of the system data and control signals present at the MCU input pins and just before the boundary scan register...

Page 1393: ...ry scan register using the SAMPLE PRELOAD instruction before the selection of EXTEST EXTEST asserts the internal system reset for the MCU to force a predictable internal state while performing externa...

Page 1394: ...esign The boundary scan register consists of this shift register chain and is connected between TDI and TDO when the EXTEST SAMPLE or SAMPLE PRELOAD instructions are loaded The shift register chain co...

Page 1395: ...as follows This chip includes an internal 5 V to 3 3 V USB regulator that powers the USB transceiver and USB device charger detection module The regulator output may optionally be used to power the MC...

Page 1396: ...7 Power Management chapter changes No substantial content changes A 8 Security chapter changes No substantial content changes A 9 Debug chapter changes Updated MDM AP Status register assignments and M...

Page 1397: ...Flowchart and added a note In topics The Kinetis Bootloader Configuration Area BCA and CRC 32 Check on Application Data added notes Correction to Kinetis Flashloader Start up Flowchart for I2Cn and SP...

Page 1398: ...alue updated the description of RAMStartAddress and RAMSizeInBytes properties A 14 RCM changes Updated the name of AN4503 to AN4503 Power Management for Kinetis MCUs A 15 SMC changes Updated the name...

Page 1399: ...dited General operation Corrected misspellings in Memory map register definition A 21 DMAMUX module changes Updated the offset address of the registers Updated the offset address of registers in the c...

Page 1400: ...MA_CR register Error Status Register DMA_ES Added two causes of channel errors to list in register description DMA_TCDn_CSR ACTIVE Changed access from RW to RO Error Status Register DMA_ES Removed bul...

Page 1401: ...or mode security in Error Handling table for Verify Backdoor Access Key and Read 1s All Blocks commands Change column heading from Byte to Offset Address in configuration field description table Add s...

Page 1402: ...ar clarifications to bit field RDAH description In Initializing a chip select section added Before using any other chip select to take it out of global chip select mode you must initialize CS0 Basic R...

Page 1403: ...nged Enables the pulse output Only lower Y bits are implemented in this MCU to Enables the pulse output Only lower 8 bits are implemented in this MCU A 39 FTM changes Added the following note to Intro...

Page 1404: ...even when there is the channel n match For section Modes of operation and section Counter clock source changed MCU to chip For section Counter clock source changed Refer to the chip specific documenta...

Page 1405: ...edge of SCK to After the tCSC delay elapses Updated SPI_MCR MDIS bit field description for setting default reset value to 1 instead of 0 In SPI_CTARn FMSZ updated description of fr to register interfa...

Page 1406: ...changes Updated the field descriptions of WATER RXWATER and STAT RDRF A 49 I2S SAI changes In RDR and TDR registers removed 31 0 from 2 bitfield names The bitfield definitions did not change just the...

Page 1407: ...mages Typical parameters that may be provided in NXP data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters incl...

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