NXP Semiconductors K22F series, Reference Manual, Page: 1047 / 1407

LPTMRx_CNR field descriptions (continued)
Field Description
COUNTER Counter Value
41.4 Functional description
41.4.1 LPTMR power and reset
The LPTMR remains powered in all power modes, including low-leakage modes. If the
LPTMR is not required to remain operating during a low-power mode, then it must be
disabled before entering the mode.
The LPTMR is reset only on global Power On Reset (POR) or Low Voltage Detect
(LVD). When configuring the LPTMR registers, the CSR must be initially written with
the timer disabled, before configuring the PSR and CMR. Then, CSR[TIE] must be set as
the last step in the initialization. This ensures the LPTMR is configured correctly and the
LPTMR counter is reset to zero following a warm reset.
41.4.2 LPTMR clocking
The LPTMR prescaler/glitch filter can be clocked by one of the four clocks. The clock
source must be enabled before the LPTMR is enabled.
NOTE
The clock source selected need to be configured to remain
enabled in low-power modes, otherwise the LPTMR will not
operate during low-power modes.
In Pulse Counter mode with the prescaler/glitch filter bypassed, the selected input source
directly clocks the CNR and no other clock source is required. To minimize power in this
case, configure the prescaler clock source for a clock that is not toggling.
NOTE
The clock source or pulse input source selected for the LPTMR
should not exceed the frequency f
LPTMR
defined in the device
datasheet.
Chapter 41 Low-Power Timer (LPTMR)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1047