NXP Semiconductors K22F series, Reference Manual, Page: 1138 / 1407

SPIx_CTARn field descriptions (continued)
Field Description
00 PCS to SCK Prescaler value is 1.
01 PCS to SCK Prescaler value is 3.
10 PCS to SCK Prescaler value is 5.
11 PCS to SCK Prescaler value is 7.
21–20
PASC After SCK Delay Prescaler
Selects the prescaler value for the delay between the last edge of SCK and the negation of PCS. See the
ASC field description for information on how to compute the After SCK Delay. Refer
After SCK Delay
(t
ASC
) for more details.
00 Delay after Transfer Prescaler value is 1.
01 Delay after Transfer Prescaler value is 3.
10 Delay after Transfer Prescaler value is 5.
11 Delay after Transfer Prescaler value is 7.
19–18
PDT
Delay after Transfer Prescaler
Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame and
the assertion of PCS at the beginning of the next frame. The PDT field is only used in master mode. See
the DT field description for details on how to compute the Delay after Transfer. Refer
Delay after Transfer
(t
DT
) for more details.
00 Delay after Transfer Prescaler value is 1.
01 Delay after Transfer Prescaler value is 3.
10 Delay after Transfer Prescaler value is 5.
11 Delay after Transfer Prescaler value is 7.
17–16
PBR
Baud Rate Prescaler
Selects the prescaler value for the baud rate. This field is used only in master mode. The baud rate is the
frequency of the SCK. The protocol clock is divided by the prescaler value before the baud rate selection
takes place. See the BR field description for details on how to compute the baud rate.
00 Baud Rate Prescaler value is 2.
01 Baud Rate Prescaler value is 3.
10 Baud Rate Prescaler value is 5.
11 Baud Rate Prescaler value is 7.
15–12
CSSCK
PCS to SCK Delay Scaler
Selects the scaler value for the PCS to SCK delay. This field is used only in master mode. The PCS to
SCK Delay is the delay between the assertion of PCS and the first edge of the SCK. The delay is a
multiple of the protocol clock period, and it is computed according to the following equation:
t
CSC
= (1/f
P
) x PCSSCK x CSSCK.
The following table lists the delay scaler values.
Table 45-3. Delay Scaler Encoding
Field Value Delay Scaler Value
0000 2
0001 4
0010 8
Table continues on the next page...
Memory Map/Register Definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1138 NXP Semiconductors