NXP Semiconductors K22F series, Reference Manual, Page: 961 / 1407

TOF bit
CHnF bit
CNT
channel (n) output
MOD = 0x0008
CnV = 0x0005
counter
overflow
channel (n)
match
counter
overflow
...
0 1 2 3 4 5 6 7 8 0 1 2
...
previous value
Figure 39-21. EPWM signal with ELSnB:ELSnA = X:1
If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal and
CHnF bit is not set even when there is the channel (n) match.
If (CnV > MOD), then the channel (n) output is a 100% duty cycle EPWM signal and
CHnF bit is not set.Therefore, MOD must be less than 0xFFFF in order to get a 100%
duty cycle EPWM signal.
Note
When CNTIN is different from zero the following EPWM
signals can be generated:
• 0% EPWM signal if CnV = CNTIN,
• EPWM signal between 0% and 100% if CNTIN < CnV <=
MOD,
• 100% EPWM signal when CNTIN > CnV or CnV > MOD.
39.4.7 Center-Aligned PWM (CPWM) mode
The Center-Aligned mode is selected when:
• QUADEN = 0
• DECAPEN = 0
• COMBINE = 0, and
• CPWMS = 1
The CPWM pulse width (duty cycle) is determined by 2 × (CnV − CNTIN) and the
period is determined by 2 × (MOD − CNTIN). See the following figure. MOD must be
kept in the range of 0x0001 to 0x7FFF because values outside this range can produce
ambiguous results.
In the CPWM mode, the FTM counter counts up until it reaches MOD and then counts
down until it reaches CNTIN.
Chapter 39 FlexTimer Module (FTM)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 961