NXP Semiconductors K22F series, Reference Manual, Page: 1353 / 1407

I2Sx_RCSR field descriptions (continued)
Field Description
Enables/disables receiver operation in Debug mode. The receive bit clock is not affected by Debug mode.
0 Receiver is disabled in Debug mode, after completing the current frame.
1 Receiver is enabled in Debug mode.
28
BCE
Bit Clock Enable
Enables the receive bit clock, separately from RE. This field is automatically set whenever RE is set.
When software clears this field, the receive bit clock remains enabled, and this field remains set, until the
end of the current frame.
0 Receive bit clock is disabled.
1 Receive bit clock is enabled.
27–26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
25
FR
FIFO Reset
Resets the FIFO pointers. Reading this field will always return zero. FIFO pointers should only be reset
when the receiver is disabled or the FIFO error flag is set.
0 No effect.
1 FIFO reset.
24
SR
Software Reset
Resets the internal receiver logic including the FIFO pointers. Software-visible registers are not affected,
except for the status registers.
0 No effect.
1 Software reset.
23–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
20
WSF
Word Start Flag
Indicates that the start of the configured word has been detected. Write a logic 1 to this field to clear this
flag.
0 Start of word not detected.
1 Start of word detected.
19
SEF
Sync Error Flag
Indicates that an error in the externally-generated frame sync has been detected. Write a logic 1 to this
field to clear this flag.
0 Sync error not detected.
1 Frame sync error detected.
18
FEF
FIFO Error Flag
Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to this field to clear this flag.
0 Receive overflow not detected.
1 Receive overflow detected.
17
FWF
FIFO Warning Flag
Table continues on the next page...
Chapter 49 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1353