• Write any value other than 0xC520 or 0xD928 to the unlock register.
• ALLOW_UPDATE is set and a gap of more than 20 bus clock cycles is inserted
between the writing of the unlock sequence values.
An attempted refresh operation between the two writes of the unlock sequence and in the
WCT time following a successful unlock, goes undetected. Also, see
for guidelines related to 8-bit accesses to the unlock register.
Note
A context switch during unlocking and refreshing may lead to a
watchdog reset.
24.3.2 Watchdog configuration time (WCT)
To prevent unintended modification of the watchdog's control and configuration register
bits, you are allowed to update them only within a period of 256 bus clock cycles after
unlocking. This period is known as the watchdog configuration time (WCT). In addition,
these register bits can be modified only once after unlocking them for editing, even after
reset.
You must unlock the registers within WCT after system reset, failing which the WDOG
issues a reset to the system. In other words, you must write at least the first word of the
unlocking sequence within the WCT after reset. After this is done, you have a further 20
bus clock cycles, the maximum allowed gap between the words of the unlock sequence,
to complete the unlocking operation. Thereafter, to make sure that you do not forget to
configure the watchdog, the watchdog issues a reset if none of the WDOG control and
configuration registers is updated in the WCT after unlock. After the close of this
window or after the first write, these register bits are locked out from any further
changes.
The watchdog timer keeps running according to its default configuration through
unlocking and update operations that can extend up to a maximum total of 2xWCT + 20
bus clock cycles. Therefore, it must be ensured that the time-out value for the watchdog
is always greater than 2xWCT time + 20 bus clock cycles.
Updates in the write-once registers take effect only after the WCT window closes with
the following exceptions for which changes take effect immediately:
• Stop, Wait, and Debug mode enable
• IRQ_RST_EN
The operations of refreshing the watchdog goes undetected during the WCT.
Chapter 24 Watchdog Timer (WDOG)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors
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Summary of Contents for K22F series
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